//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARTSC_H_INC_
#define ___ARTSC_H_INC_
#define NV_MOBILE_ARTSC_H_UNIT_OF_OFFSET 1B


// Register TSC_MTSCACR_0
#define TSC_MTSCACR_0                   _MK_ADDR_CONST(0x0)
#define TSC_MTSCACR_0_SECURE                    0x0
#define TSC_MTSCACR_0_DUAL                      0x0
#define TSC_MTSCACR_0_SCR                       TSCSCR_0
#define TSC_MTSCACR_0_WORD_COUNT                        0x1
#define TSC_MTSCACR_0_RESET_VAL                         _MK_MASK_CONST(0x2)
#define TSC_MTSCACR_0_RESET_MASK                        _MK_MASK_CONST(0xf3)
#define TSC_MTSCACR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TSC_MTSCACR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TSC_MTSCACR_0_READ_MASK                         _MK_MASK_CONST(0xf3)
#define TSC_MTSCACR_0_WRITE_MASK                        _MK_MASK_CONST(0xf3)
#define TSC_MTSCACR_0_EN_SHIFT                  _MK_SHIFT_CONST(0)
#define TSC_MTSCACR_0_EN_FIELD                  _MK_FIELD_CONST(0x1, TSC_MTSCACR_0_EN_SHIFT)
#define TSC_MTSCACR_0_EN_RANGE                  0:0
#define TSC_MTSCACR_0_EN_WOFFSET                        0x0
#define TSC_MTSCACR_0_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define TSC_MTSCACR_0_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define TSC_MTSCACR_0_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_MTSCACR_0_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TSC_MTSCACR_0_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define TSC_MTSCACR_0_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define TSC_MTSCACR_0_EN_DISABLE                        _MK_ENUM_CONST(0)
#define TSC_MTSCACR_0_EN_ENABLE                 _MK_ENUM_CONST(1)

#define TSC_MTSCACR_0_DIR_SHIFT                 _MK_SHIFT_CONST(1)
#define TSC_MTSCACR_0_DIR_FIELD                 _MK_FIELD_CONST(0x1, TSC_MTSCACR_0_DIR_SHIFT)
#define TSC_MTSCACR_0_DIR_RANGE                 1:1
#define TSC_MTSCACR_0_DIR_WOFFSET                       0x0
#define TSC_MTSCACR_0_DIR_DEFAULT                       _MK_MASK_CONST(0x1)
#define TSC_MTSCACR_0_DIR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define TSC_MTSCACR_0_DIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define TSC_MTSCACR_0_DIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TSC_MTSCACR_0_DIR_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define TSC_MTSCACR_0_DIR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define TSC_MTSCACR_0_ABS_SHIFT                 _MK_SHIFT_CONST(4)
#define TSC_MTSCACR_0_ABS_FIELD                 _MK_FIELD_CONST(0xf, TSC_MTSCACR_0_ABS_SHIFT)
#define TSC_MTSCACR_0_ABS_RANGE                 7:4
#define TSC_MTSCACR_0_ABS_WOFFSET                       0x0
#define TSC_MTSCACR_0_ABS_DEFAULT                       _MK_MASK_CONST(0x0)
#define TSC_MTSCACR_0_ABS_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define TSC_MTSCACR_0_ABS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define TSC_MTSCACR_0_ABS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TSC_MTSCACR_0_ABS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define TSC_MTSCACR_0_ABS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register TSC_MTSCADR_0
#define TSC_MTSCADR_0                   _MK_ADDR_CONST(0x4)
#define TSC_MTSCADR_0_SECURE                    0x0
#define TSC_MTSCADR_0_DUAL                      0x0
#define TSC_MTSCADR_0_SCR                       TSCSCR_0
#define TSC_MTSCADR_0_WORD_COUNT                        0x1
#define TSC_MTSCADR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define TSC_MTSCADR_0_RESET_MASK                        _MK_MASK_CONST(0xfff0fff)
#define TSC_MTSCADR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TSC_MTSCADR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TSC_MTSCADR_0_READ_MASK                         _MK_MASK_CONST(0xfff0fff)
#define TSC_MTSCADR_0_WRITE_MASK                        _MK_MASK_CONST(0xfff0fff)
#define TSC_MTSCADR_0_N1_SHIFT                  _MK_SHIFT_CONST(0)
#define TSC_MTSCADR_0_N1_FIELD                  _MK_FIELD_CONST(0xfff, TSC_MTSCADR_0_N1_SHIFT)
#define TSC_MTSCADR_0_N1_RANGE                  11:0
#define TSC_MTSCADR_0_N1_WOFFSET                        0x0
#define TSC_MTSCADR_0_N1_DEFAULT                        _MK_MASK_CONST(0x0)
#define TSC_MTSCADR_0_N1_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define TSC_MTSCADR_0_N1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_MTSCADR_0_N1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TSC_MTSCADR_0_N1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define TSC_MTSCADR_0_N1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define TSC_MTSCADR_0_D1_SHIFT                  _MK_SHIFT_CONST(16)
#define TSC_MTSCADR_0_D1_FIELD                  _MK_FIELD_CONST(0xfff, TSC_MTSCADR_0_D1_SHIFT)
#define TSC_MTSCADR_0_D1_RANGE                  27:16
#define TSC_MTSCADR_0_D1_WOFFSET                        0x0
#define TSC_MTSCADR_0_D1_DEFAULT                        _MK_MASK_CONST(0x0)
#define TSC_MTSCADR_0_D1_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define TSC_MTSCADR_0_D1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_MTSCADR_0_D1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TSC_MTSCADR_0_D1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define TSC_MTSCADR_0_D1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register TSC_MTSCANNR_0
#define TSC_MTSCANNR_0                  _MK_ADDR_CONST(0x8)
#define TSC_MTSCANNR_0_SECURE                   0x0
#define TSC_MTSCANNR_0_DUAL                     0x0
#define TSC_MTSCANNR_0_SCR                      TSCSCR_0
#define TSC_MTSCANNR_0_WORD_COUNT                       0x1
#define TSC_MTSCANNR_0_RESET_VAL                        _MK_MASK_CONST(0x56503b9)
#define TSC_MTSCANNR_0_RESET_MASK                       _MK_MASK_CONST(0xfff0fff)
#define TSC_MTSCANNR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define TSC_MTSCANNR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define TSC_MTSCANNR_0_READ_MASK                        _MK_MASK_CONST(0xfff0fff)
#define TSC_MTSCANNR_0_WRITE_MASK                       _MK_MASK_CONST(0xfff0fff)
#define TSC_MTSCANNR_0_R0_SHIFT                 _MK_SHIFT_CONST(0)
#define TSC_MTSCANNR_0_R0_FIELD                 _MK_FIELD_CONST(0xfff, TSC_MTSCANNR_0_R0_SHIFT)
#define TSC_MTSCANNR_0_R0_RANGE                 11:0
#define TSC_MTSCANNR_0_R0_WOFFSET                       0x0
#define TSC_MTSCANNR_0_R0_DEFAULT                       _MK_MASK_CONST(0x3b9)
#define TSC_MTSCANNR_0_R0_DEFAULT_MASK                  _MK_MASK_CONST(0xfff)
#define TSC_MTSCANNR_0_R0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define TSC_MTSCANNR_0_R0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TSC_MTSCANNR_0_R0_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define TSC_MTSCANNR_0_R0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define TSC_MTSCANNR_0_M0_SHIFT                 _MK_SHIFT_CONST(16)
#define TSC_MTSCANNR_0_M0_FIELD                 _MK_FIELD_CONST(0xfff, TSC_MTSCANNR_0_M0_SHIFT)
#define TSC_MTSCANNR_0_M0_RANGE                 27:16
#define TSC_MTSCANNR_0_M0_WOFFSET                       0x0
#define TSC_MTSCANNR_0_M0_DEFAULT                       _MK_MASK_CONST(0x565)
#define TSC_MTSCANNR_0_M0_DEFAULT_MASK                  _MK_MASK_CONST(0xfff)
#define TSC_MTSCANNR_0_M0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define TSC_MTSCANNR_0_M0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TSC_MTSCANNR_0_M0_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define TSC_MTSCANNR_0_M0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register TSC_MTSCANDR_0
#define TSC_MTSCANDR_0                  _MK_ADDR_CONST(0xc)
#define TSC_MTSCANDR_0_SECURE                   0x0
#define TSC_MTSCANDR_0_DUAL                     0x0
#define TSC_MTSCANDR_0_SCR                      TSCSCR_0
#define TSC_MTSCANDR_0_WORD_COUNT                       0x1
#define TSC_MTSCANDR_0_RESET_VAL                        _MK_MASK_CONST(0x800)
#define TSC_MTSCANDR_0_RESET_MASK                       _MK_MASK_CONST(0xfff)
#define TSC_MTSCANDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define TSC_MTSCANDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define TSC_MTSCANDR_0_READ_MASK                        _MK_MASK_CONST(0xfff)
#define TSC_MTSCANDR_0_WRITE_MASK                       _MK_MASK_CONST(0xfff)
#define TSC_MTSCANDR_0_D0_SHIFT                 _MK_SHIFT_CONST(0)
#define TSC_MTSCANDR_0_D0_FIELD                 _MK_FIELD_CONST(0xfff, TSC_MTSCANDR_0_D0_SHIFT)
#define TSC_MTSCANDR_0_D0_RANGE                 11:0
#define TSC_MTSCANDR_0_D0_WOFFSET                       0x0
#define TSC_MTSCANDR_0_D0_DEFAULT                       _MK_MASK_CONST(0x800)
#define TSC_MTSCANDR_0_D0_DEFAULT_MASK                  _MK_MASK_CONST(0xfff)
#define TSC_MTSCANDR_0_D0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define TSC_MTSCANDR_0_D0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TSC_MTSCANDR_0_D0_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define TSC_MTSCANDR_0_D0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register TSC_MTSCCNTCV0_0
#define TSC_MTSCCNTCV0_0                        _MK_ADDR_CONST(0x10)
#define TSC_MTSCCNTCV0_0_SECURE                         0x0
#define TSC_MTSCCNTCV0_0_DUAL                   0x0
#define TSC_MTSCCNTCV0_0_SCR                    TSCSCR_0
#define TSC_MTSCCNTCV0_0_WORD_COUNT                     0x1
#define TSC_MTSCCNTCV0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define TSC_MTSCCNTCV0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define TSC_MTSCCNTCV0_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV0_0_CV_SHIFT                       _MK_SHIFT_CONST(0)
#define TSC_MTSCCNTCV0_0_CV_FIELD                       _MK_FIELD_CONST(0xffffffff, TSC_MTSCCNTCV0_0_CV_SHIFT)
#define TSC_MTSCCNTCV0_0_CV_RANGE                       31:0
#define TSC_MTSCCNTCV0_0_CV_WOFFSET                     0x0
#define TSC_MTSCCNTCV0_0_CV_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV0_0_CV_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define TSC_MTSCCNTCV0_0_CV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV0_0_CV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV0_0_CV_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV0_0_CV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register TSC_MTSCCNTCV1_0
#define TSC_MTSCCNTCV1_0                        _MK_ADDR_CONST(0x14)
#define TSC_MTSCCNTCV1_0_SECURE                         0x0
#define TSC_MTSCCNTCV1_0_DUAL                   0x0
#define TSC_MTSCCNTCV1_0_SCR                    TSCSCR_0
#define TSC_MTSCCNTCV1_0_WORD_COUNT                     0x1
#define TSC_MTSCCNTCV1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV1_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define TSC_MTSCCNTCV1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV1_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define TSC_MTSCCNTCV1_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV1_0_CV_SHIFT                       _MK_SHIFT_CONST(0)
#define TSC_MTSCCNTCV1_0_CV_FIELD                       _MK_FIELD_CONST(0xffffffff, TSC_MTSCCNTCV1_0_CV_SHIFT)
#define TSC_MTSCCNTCV1_0_CV_RANGE                       31:0
#define TSC_MTSCCNTCV1_0_CV_WOFFSET                     0x0
#define TSC_MTSCCNTCV1_0_CV_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV1_0_CV_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define TSC_MTSCCNTCV1_0_CV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV1_0_CV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV1_0_CV_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TSC_MTSCCNTCV1_0_CV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x18

// Reserved address 0x1c

// Reserved address 0x20

// Reserved address 0x24

// Reserved address 0x28

// Reserved address 0x2c

// Reserved address 0x30

// Reserved address 0x34

// Reserved address 0x38

// Reserved address 0x3c

// Reserved address 0x40

// Reserved address 0x44

// Reserved address 0x48

// Reserved address 0x4c

// Reserved address 0x50

// Reserved address 0x54

// Reserved address 0x58

// Reserved address 0x5c

// Reserved address 0x60

// Reserved address 0x64

// Reserved address 0x68

// Reserved address 0x6c

// Reserved address 0x70

// Reserved address 0x74

// Reserved address 0x78

// Reserved address 0x7c

// Reserved address 0x80

// Reserved address 0x84

// Reserved address 0x88

// Reserved address 0x8c

// Reserved address 0x90

// Reserved address 0x94

// Reserved address 0x98

// Reserved address 0x9c

// Reserved address 0xa0

// Reserved address 0xa4

// Reserved address 0xa8

// Reserved address 0xac

// Reserved address 0xb0

// Reserved address 0xb4

// Reserved address 0xb8

// Reserved address 0xbc

// Reserved address 0xc0

// Reserved address 0xc4

// Reserved address 0xc8

// Reserved address 0xcc

// Reserved address 0xd0

// Reserved address 0xd4

// Reserved address 0xd8

// Reserved address 0xdc

// Reserved address 0xe0

// Reserved address 0xe4

// Reserved address 0xe8

// Reserved address 0xec

// Reserved address 0xf0

// Reserved address 0xf4

// Reserved address 0xf8

// Reserved address 0xfc

// Register TSC_STSCCR_0
#define TSC_STSCCR_0                    _MK_ADDR_CONST(0x100)
#define TSC_STSCCR_0_SECURE                     0x0
#define TSC_STSCCR_0_DUAL                       0x0
#define TSC_STSCCR_0_SCR                        TSCSCR_0
#define TSC_STSCCR_0_WORD_COUNT                         0x1
#define TSC_STSCCR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_RESET_MASK                         _MK_MASK_CONST(0x12f)
#define TSC_STSCCR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_READ_MASK                  _MK_MASK_CONST(0x12f)
#define TSC_STSCCR_0_WRITE_MASK                         _MK_MASK_CONST(0x12f)
#define TSC_STSCCR_0_INIT_SHIFT                 _MK_SHIFT_CONST(0)
#define TSC_STSCCR_0_INIT_FIELD                 _MK_FIELD_CONST(0x1, TSC_STSCCR_0_INIT_SHIFT)
#define TSC_STSCCR_0_INIT_RANGE                 0:0
#define TSC_STSCCR_0_INIT_WOFFSET                       0x0
#define TSC_STSCCR_0_INIT_DEFAULT                       _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_INIT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define TSC_STSCCR_0_INIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_INIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_INIT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_INIT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define TSC_STSCCR_0_DIS_SHIFT                  _MK_SHIFT_CONST(1)
#define TSC_STSCCR_0_DIS_FIELD                  _MK_FIELD_CONST(0x1, TSC_STSCCR_0_DIS_SHIFT)
#define TSC_STSCCR_0_DIS_RANGE                  1:1
#define TSC_STSCCR_0_DIS_WOFFSET                        0x0
#define TSC_STSCCR_0_DIS_DEFAULT                        _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_DIS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define TSC_STSCCR_0_DIS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_DIS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_DIS_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define TSC_STSCCR_0_DIS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define TSC_STSCCR_0_FP_SHIFT                   _MK_SHIFT_CONST(2)
#define TSC_STSCCR_0_FP_FIELD                   _MK_FIELD_CONST(0x1, TSC_STSCCR_0_FP_SHIFT)
#define TSC_STSCCR_0_FP_RANGE                   2:2
#define TSC_STSCCR_0_FP_WOFFSET                 0x0
#define TSC_STSCCR_0_FP_DEFAULT                 _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_FP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define TSC_STSCCR_0_FP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_FP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_FP_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define TSC_STSCCR_0_FP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define TSC_STSCCR_0_SRC_SHIFT                  _MK_SHIFT_CONST(3)
#define TSC_STSCCR_0_SRC_FIELD                  _MK_FIELD_CONST(0x1, TSC_STSCCR_0_SRC_SHIFT)
#define TSC_STSCCR_0_SRC_RANGE                  3:3
#define TSC_STSCCR_0_SRC_WOFFSET                        0x0
#define TSC_STSCCR_0_SRC_DEFAULT                        _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_SRC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define TSC_STSCCR_0_SRC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_SRC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_SRC_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define TSC_STSCCR_0_SRC_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define TSC_STSCCR_0_FCREQ_DISABLE_SHIFT                        _MK_SHIFT_CONST(5)
#define TSC_STSCCR_0_FCREQ_DISABLE_FIELD                        _MK_FIELD_CONST(0x1, TSC_STSCCR_0_FCREQ_DISABLE_SHIFT)
#define TSC_STSCCR_0_FCREQ_DISABLE_RANGE                        5:5
#define TSC_STSCCR_0_FCREQ_DISABLE_WOFFSET                      0x0
#define TSC_STSCCR_0_FCREQ_DISABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_FCREQ_DISABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define TSC_STSCCR_0_FCREQ_DISABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_FCREQ_DISABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_FCREQ_DISABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define TSC_STSCCR_0_FCREQ_DISABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define TSC_STSCCR_0_FCREQ_DISABLE_DISABLE                      _MK_ENUM_CONST(0)
#define TSC_STSCCR_0_FCREQ_DISABLE_ENABLE                       _MK_ENUM_CONST(1)

#define TSC_STSCCR_0_FCREQ_SHIFT                        _MK_SHIFT_CONST(8)
#define TSC_STSCCR_0_FCREQ_FIELD                        _MK_FIELD_CONST(0x1, TSC_STSCCR_0_FCREQ_SHIFT)
#define TSC_STSCCR_0_FCREQ_RANGE                        8:8
#define TSC_STSCCR_0_FCREQ_WOFFSET                      0x0
#define TSC_STSCCR_0_FCREQ_DEFAULT                      _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_FCREQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define TSC_STSCCR_0_FCREQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_FCREQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_FCREQ_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define TSC_STSCCR_0_FCREQ_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register TSC_STSCRSR_0
#define TSC_STSCRSR_0                   _MK_ADDR_CONST(0x104)
#define TSC_STSCRSR_0_SECURE                    0x0
#define TSC_STSCRSR_0_DUAL                      0x0
#define TSC_STSCRSR_0_SCR                       TSCSCR_0
#define TSC_STSCRSR_0_WORD_COUNT                        0x1
#define TSC_STSCRSR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define TSC_STSCRSR_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define TSC_STSCRSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TSC_STSCRSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TSC_STSCRSR_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define TSC_STSCRSR_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define TSC_STSCRSR_0_FR_SHIFT                  _MK_SHIFT_CONST(0)
#define TSC_STSCRSR_0_FR_FIELD                  _MK_FIELD_CONST(0x1, TSC_STSCRSR_0_FR_SHIFT)
#define TSC_STSCRSR_0_FR_RANGE                  0:0
#define TSC_STSCRSR_0_FR_WOFFSET                        0x0
#define TSC_STSCRSR_0_FR_DEFAULT                        _MK_MASK_CONST(0x0)
#define TSC_STSCRSR_0_FR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define TSC_STSCRSR_0_FR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_STSCRSR_0_FR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TSC_STSCRSR_0_FR_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define TSC_STSCRSR_0_FR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define TSC_STSCRSR_0_FR_LOCKEN                 _MK_ENUM_CONST(0)
#define TSC_STSCRSR_0_FR_LOCKDIS                        _MK_ENUM_CONST(1)

#define TSC_STSCRSR_0_RANGE_SHIFT                       _MK_SHIFT_CONST(1)
#define TSC_STSCRSR_0_RANGE_FIELD                       _MK_FIELD_CONST(0x1, TSC_STSCRSR_0_RANGE_SHIFT)
#define TSC_STSCRSR_0_RANGE_RANGE                       1:1
#define TSC_STSCRSR_0_RANGE_WOFFSET                     0x0
#define TSC_STSCRSR_0_RANGE_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_STSCRSR_0_RANGE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define TSC_STSCRSR_0_RANGE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TSC_STSCRSR_0_RANGE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TSC_STSCRSR_0_RANGE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define TSC_STSCRSR_0_RANGE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define TSC_STSCRSR_0_RANGE_SMALL                       _MK_ENUM_CONST(0)
#define TSC_STSCRSR_0_RANGE_LARGE                       _MK_ENUM_CONST(1)


// Register TSC_STSCIR0_0
#define TSC_STSCIR0_0                   _MK_ADDR_CONST(0x108)
#define TSC_STSCIR0_0_SECURE                    0x0
#define TSC_STSCIR0_0_DUAL                      0x0
#define TSC_STSCIR0_0_SCR                       TSCSCR_0
#define TSC_STSCIR0_0_WORD_COUNT                        0x1
#define TSC_STSCIR0_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define TSC_STSCIR0_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define TSC_STSCIR0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TSC_STSCIR0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TSC_STSCIR0_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define TSC_STSCIR0_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define TSC_STSCIR0_0_K_SHIFT                   _MK_SHIFT_CONST(0)
#define TSC_STSCIR0_0_K_FIELD                   _MK_FIELD_CONST(0xf, TSC_STSCIR0_0_K_SHIFT)
#define TSC_STSCIR0_0_K_RANGE                   3:0
#define TSC_STSCIR0_0_K_WOFFSET                 0x0
#define TSC_STSCIR0_0_K_DEFAULT                 _MK_MASK_CONST(0x1)
#define TSC_STSCIR0_0_K_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define TSC_STSCIR0_0_K_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TSC_STSCIR0_0_K_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TSC_STSCIR0_0_K_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define TSC_STSCIR0_0_K_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register TSC_STSCIR1_0
#define TSC_STSCIR1_0                   _MK_ADDR_CONST(0x10c)
#define TSC_STSCIR1_0_SECURE                    0x0
#define TSC_STSCIR1_0_DUAL                      0x0
#define TSC_STSCIR1_0_SCR                       TSCSCR_0
#define TSC_STSCIR1_0_WORD_COUNT                        0x1
#define TSC_STSCIR1_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define TSC_STSCIR1_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define TSC_STSCIR1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TSC_STSCIR1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TSC_STSCIR1_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define TSC_STSCIR1_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define TSC_STSCIR1_0_K_SHIFT                   _MK_SHIFT_CONST(0)
#define TSC_STSCIR1_0_K_FIELD                   _MK_FIELD_CONST(0xf, TSC_STSCIR1_0_K_SHIFT)
#define TSC_STSCIR1_0_K_RANGE                   3:0
#define TSC_STSCIR1_0_K_WOFFSET                 0x0
#define TSC_STSCIR1_0_K_DEFAULT                 _MK_MASK_CONST(0x1)
#define TSC_STSCIR1_0_K_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define TSC_STSCIR1_0_K_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TSC_STSCIR1_0_K_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TSC_STSCIR1_0_K_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define TSC_STSCIR1_0_K_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register TSC_STSCSR_0
#define TSC_STSCSR_0                    _MK_ADDR_CONST(0x110)
#define TSC_STSCSR_0_SECURE                     0x0
#define TSC_STSCSR_0_DUAL                       0x0
#define TSC_STSCSR_0_SCR                        TSCSCR_0
#define TSC_STSCSR_0_WORD_COUNT                         0x1
#define TSC_STSCSR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_RESET_MASK                         _MK_MASK_CONST(0x1ff)
#define TSC_STSCSR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
#define TSC_STSCSR_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_OFS_SHIFT                  _MK_SHIFT_CONST(0)
#define TSC_STSCSR_0_OFS_FIELD                  _MK_FIELD_CONST(0xff, TSC_STSCSR_0_OFS_SHIFT)
#define TSC_STSCSR_0_OFS_RANGE                  7:0
#define TSC_STSCSR_0_OFS_WOFFSET                        0x0
#define TSC_STSCSR_0_OFS_DEFAULT                        _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_OFS_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define TSC_STSCSR_0_OFS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_OFS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_OFS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_OFS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define TSC_STSCSR_0_FCACK_SHIFT                        _MK_SHIFT_CONST(8)
#define TSC_STSCSR_0_FCACK_FIELD                        _MK_FIELD_CONST(0x1, TSC_STSCSR_0_FCACK_SHIFT)
#define TSC_STSCSR_0_FCACK_RANGE                        8:8
#define TSC_STSCSR_0_FCACK_WOFFSET                      0x0
#define TSC_STSCSR_0_FCACK_DEFAULT                      _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_FCACK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define TSC_STSCSR_0_FCACK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_FCACK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_FCACK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define TSC_STSCSR_0_FCACK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register TSC_TSCDCR_0
#define TSC_TSCDCR_0                    _MK_ADDR_CONST(0x114)
#define TSC_TSCDCR_0_SECURE                     0x0
#define TSC_TSCDCR_0_DUAL                       0x0
#define TSC_TSCDCR_0_SCR                        TSCSCR_0
#define TSC_TSCDCR_0_WORD_COUNT                         0x1
#define TSC_TSCDCR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_RESET_MASK                         _MK_MASK_CONST(0xf037f)
#define TSC_TSCDCR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_READ_MASK                  _MK_MASK_CONST(0xf037f)
#define TSC_TSCDCR_0_WRITE_MASK                         _MK_MASK_CONST(0xf037f)
#define TSC_TSCDCR_0_K_SHIFT                    _MK_SHIFT_CONST(0)
#define TSC_TSCDCR_0_K_FIELD                    _MK_FIELD_CONST(0xf, TSC_TSCDCR_0_K_SHIFT)
#define TSC_TSCDCR_0_K_RANGE                    3:0
#define TSC_TSCDCR_0_K_WOFFSET                  0x0
#define TSC_TSCDCR_0_K_DEFAULT                  _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_K_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define TSC_TSCDCR_0_K_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_K_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_K_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define TSC_TSCDCR_0_K_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define TSC_TSCDCR_0_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define TSC_TSCDCR_0_EN_FIELD                   _MK_FIELD_CONST(0x1, TSC_TSCDCR_0_EN_SHIFT)
#define TSC_TSCDCR_0_EN_RANGE                   4:4
#define TSC_TSCDCR_0_EN_WOFFSET                 0x0
#define TSC_TSCDCR_0_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define TSC_TSCDCR_0_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define TSC_TSCDCR_0_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define TSC_TSCDCR_0_EN_DISABLE                 _MK_ENUM_CONST(0)
#define TSC_TSCDCR_0_EN_ENABLE                  _MK_ENUM_CONST(1)

#define TSC_TSCDCR_0_SYNC_SHIFT                 _MK_SHIFT_CONST(5)
#define TSC_TSCDCR_0_SYNC_FIELD                 _MK_FIELD_CONST(0x1, TSC_TSCDCR_0_SYNC_SHIFT)
#define TSC_TSCDCR_0_SYNC_RANGE                 5:5
#define TSC_TSCDCR_0_SYNC_WOFFSET                       0x0
#define TSC_TSCDCR_0_SYNC_DEFAULT                       _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_SYNC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define TSC_TSCDCR_0_SYNC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_SYNC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_SYNC_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_SYNC_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define TSC_TSCDCR_0_DISABLE_PERIODIC_SHIFT                     _MK_SHIFT_CONST(6)
#define TSC_TSCDCR_0_DISABLE_PERIODIC_FIELD                     _MK_FIELD_CONST(0x1, TSC_TSCDCR_0_DISABLE_PERIODIC_SHIFT)
#define TSC_TSCDCR_0_DISABLE_PERIODIC_RANGE                     6:6
#define TSC_TSCDCR_0_DISABLE_PERIODIC_WOFFSET                   0x0
#define TSC_TSCDCR_0_DISABLE_PERIODIC_DEFAULT                   _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_DISABLE_PERIODIC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define TSC_TSCDCR_0_DISABLE_PERIODIC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_DISABLE_PERIODIC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_DISABLE_PERIODIC_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define TSC_TSCDCR_0_DISABLE_PERIODIC_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define TSC_TSCDCR_0_DISABLE_PERIODIC_DISABLE                   _MK_ENUM_CONST(0)
#define TSC_TSCDCR_0_DISABLE_PERIODIC_ENABLE                    _MK_ENUM_CONST(1)

#define TSC_TSCDCR_0_RES_SHIFT                  _MK_SHIFT_CONST(8)
#define TSC_TSCDCR_0_RES_FIELD                  _MK_FIELD_CONST(0x3, TSC_TSCDCR_0_RES_SHIFT)
#define TSC_TSCDCR_0_RES_RANGE                  9:8
#define TSC_TSCDCR_0_RES_WOFFSET                        0x0
#define TSC_TSCDCR_0_RES_DEFAULT                        _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_RES_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define TSC_TSCDCR_0_RES_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_RES_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_RES_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define TSC_TSCDCR_0_RES_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define TSC_TSCDCR_0_SYNCEP_SHIFT                       _MK_SHIFT_CONST(16)
#define TSC_TSCDCR_0_SYNCEP_FIELD                       _MK_FIELD_CONST(0xf, TSC_TSCDCR_0_SYNCEP_SHIFT)
#define TSC_TSCDCR_0_SYNCEP_RANGE                       19:16
#define TSC_TSCDCR_0_SYNCEP_WOFFSET                     0x0
#define TSC_TSCDCR_0_SYNCEP_DEFAULT                     _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_SYNCEP_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define TSC_TSCDCR_0_SYNCEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_SYNCEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TSC_TSCDCR_0_SYNCEP_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define TSC_TSCDCR_0_SYNCEP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register TSC_TSCDHCR_0
#define TSC_TSCDHCR_0                   _MK_ADDR_CONST(0x118)
#define TSC_TSCDHCR_0_SECURE                    0x0
#define TSC_TSCDHCR_0_DUAL                      0x0
#define TSC_TSCDHCR_0_SCR                       TSCSCR_0
#define TSC_TSCDHCR_0_WORD_COUNT                        0x1
#define TSC_TSCDHCR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define TSC_TSCDHCR_0_RESET_MASK                        _MK_MASK_CONST(0x10001)
#define TSC_TSCDHCR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TSC_TSCDHCR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TSC_TSCDHCR_0_READ_MASK                         _MK_MASK_CONST(0x10001)
#define TSC_TSCDHCR_0_WRITE_MASK                        _MK_MASK_CONST(0x10001)
#define TSC_TSCDHCR_0_HDBG_CPU_SHIFT                    _MK_SHIFT_CONST(0)
#define TSC_TSCDHCR_0_HDBG_CPU_FIELD                    _MK_FIELD_CONST(0x1, TSC_TSCDHCR_0_HDBG_CPU_SHIFT)
#define TSC_TSCDHCR_0_HDBG_CPU_RANGE                    0:0
#define TSC_TSCDHCR_0_HDBG_CPU_WOFFSET                  0x0
#define TSC_TSCDHCR_0_HDBG_CPU_DEFAULT                  _MK_MASK_CONST(0x0)
#define TSC_TSCDHCR_0_HDBG_CPU_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define TSC_TSCDHCR_0_HDBG_CPU_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define TSC_TSCDHCR_0_HDBG_CPU_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define TSC_TSCDHCR_0_HDBG_CPU_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define TSC_TSCDHCR_0_HDBG_CPU_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define TSC_TSCDHCR_0_STOP_CPU_TSC_SHIFT                        _MK_SHIFT_CONST(16)
#define TSC_TSCDHCR_0_STOP_CPU_TSC_FIELD                        _MK_FIELD_CONST(0x1, TSC_TSCDHCR_0_STOP_CPU_TSC_SHIFT)
#define TSC_TSCDHCR_0_STOP_CPU_TSC_RANGE                        16:16
#define TSC_TSCDHCR_0_STOP_CPU_TSC_WOFFSET                      0x0
#define TSC_TSCDHCR_0_STOP_CPU_TSC_DEFAULT                      _MK_MASK_CONST(0x0)
#define TSC_TSCDHCR_0_STOP_CPU_TSC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define TSC_TSCDHCR_0_STOP_CPU_TSC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define TSC_TSCDHCR_0_STOP_CPU_TSC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define TSC_TSCDHCR_0_STOP_CPU_TSC_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define TSC_TSCDHCR_0_STOP_CPU_TSC_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register TSC_CLK_OVR_ON_0
#define TSC_CLK_OVR_ON_0                        _MK_ADDR_CONST(0x11c)
#define TSC_CLK_OVR_ON_0_SECURE                         0x0
#define TSC_CLK_OVR_ON_0_DUAL                   0x0
#define TSC_CLK_OVR_ON_0_SCR                    TSCSCR_0
#define TSC_CLK_OVR_ON_0_WORD_COUNT                     0x1
#define TSC_CLK_OVR_ON_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define TSC_CLK_OVR_ON_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define TSC_CLK_OVR_ON_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define TSC_CLK_OVR_ON_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TSC_CLK_OVR_ON_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define TSC_CLK_OVR_ON_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define TSC_CLK_OVR_ON_0_CK32K_SHIFT                    _MK_SHIFT_CONST(0)
#define TSC_CLK_OVR_ON_0_CK32K_FIELD                    _MK_FIELD_CONST(0x1, TSC_CLK_OVR_ON_0_CK32K_SHIFT)
#define TSC_CLK_OVR_ON_0_CK32K_RANGE                    0:0
#define TSC_CLK_OVR_ON_0_CK32K_WOFFSET                  0x0
#define TSC_CLK_OVR_ON_0_CK32K_DEFAULT                  _MK_MASK_CONST(0x0)
#define TSC_CLK_OVR_ON_0_CK32K_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define TSC_CLK_OVR_ON_0_CK32K_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define TSC_CLK_OVR_ON_0_CK32K_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define TSC_CLK_OVR_ON_0_CK32K_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define TSC_CLK_OVR_ON_0_CK32K_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define TSC_CLK_OVR_ON_0_CK32K_DISABLE                  _MK_ENUM_CONST(0)
#define TSC_CLK_OVR_ON_0_CK32K_ENABLE                   _MK_ENUM_CONST(1)


//
// REGISTER LIST
//
#define LIST_ARTSC_REGS(_op_) \
_op_(TSC_MTSCACR_0) \
_op_(TSC_MTSCADR_0) \
_op_(TSC_MTSCANNR_0) \
_op_(TSC_MTSCANDR_0) \
_op_(TSC_MTSCCNTCV0_0) \
_op_(TSC_MTSCCNTCV1_0) \
_op_(TSC_STSCCR_0) \
_op_(TSC_STSCRSR_0) \
_op_(TSC_STSCIR0_0) \
_op_(TSC_STSCIR1_0) \
_op_(TSC_STSCSR_0) \
_op_(TSC_TSCDCR_0) \
_op_(TSC_TSCDHCR_0) \
_op_(TSC_CLK_OVR_ON_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_TSC        0x00000000

//
// ARTSC REGISTER BANKS
//

#define TSC0_FIRST_REG 0x0000 // TSC_MTSCACR_0
#define TSC0_LAST_REG 0x0014 // TSC_MTSCCNTCV1_0
#define TSC1_FIRST_REG 0x0100 // TSC_STSCCR_0
#define TSC1_LAST_REG 0x011c // TSC_CLK_OVR_ON_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARTSC_H_INC_
