//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARAPB_MISC_H_INC_
#define ___ARAPB_MISC_H_INC_
#define NV_MOBILE_ARAPB_MISC_H_UNIT_OF_OFFSET 1B


// Reserved address 0x800

// Register APB_MISC_GP_HIDREV_0
#define APB_MISC_GP_HIDREV_0                    _MK_ADDR_CONST(0x804)
#define APB_MISC_GP_HIDREV_0_SECURE                     0x0
#define APB_MISC_GP_HIDREV_0_DUAL                       0x0
#define APB_MISC_GP_HIDREV_0_SCR                        0
#define APB_MISC_GP_HIDREV_0_WORD_COUNT                         0x1
#define APB_MISC_GP_HIDREV_0_RESET_VAL                  _MK_MASK_CONST(0x21917)
#define APB_MISC_GP_HIDREV_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
#define APB_MISC_GP_HIDREV_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_HIDREV_0_HIDFAM_FIELD                       _MK_FIELD_CONST(0xf, APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT)
#define APB_MISC_GP_HIDREV_0_HIDFAM_RANGE                       3:0
#define APB_MISC_GP_HIDREV_0_HIDFAM_WOFFSET                     0x0
#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT                     _MK_MASK_CONST(0x7)
#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_HIDFAM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_HIDFAM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_HIDREV_0_HIDFAM_GPU                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD                    _MK_ENUM_CONST(1)
#define APB_MISC_GP_HIDREV_0_HIDFAM_BR_CHIPS                    _MK_ENUM_CONST(2)
#define APB_MISC_GP_HIDREV_0_HIDFAM_CRUSH                       _MK_ENUM_CONST(3)
#define APB_MISC_GP_HIDREV_0_HIDFAM_MCP                 _MK_ENUM_CONST(4)
#define APB_MISC_GP_HIDREV_0_HIDFAM_CK                  _MK_ENUM_CONST(5)
#define APB_MISC_GP_HIDREV_0_HIDFAM_VAIO                        _MK_ENUM_CONST(6)
#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD_SOC                        _MK_ENUM_CONST(7)

#define APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT                     _MK_SHIFT_CONST(4)
#define APB_MISC_GP_HIDREV_0_MAJORREV_FIELD                     _MK_FIELD_CONST(0xf, APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT)
#define APB_MISC_GP_HIDREV_0_MAJORREV_RANGE                     7:4
#define APB_MISC_GP_HIDREV_0_MAJORREV_WOFFSET                   0x0
#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_MAJORREV_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_MAJORREV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_HIDREV_0_MAJORREV_EMULATION                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_HIDREV_0_MAJORREV_A01                       _MK_ENUM_CONST(1)

#define APB_MISC_GP_HIDREV_0_CHIPID_SHIFT                       _MK_SHIFT_CONST(8)
#define APB_MISC_GP_HIDREV_0_CHIPID_FIELD                       _MK_FIELD_CONST(0xff, APB_MISC_GP_HIDREV_0_CHIPID_SHIFT)
#define APB_MISC_GP_HIDREV_0_CHIPID_RANGE                       15:8
#define APB_MISC_GP_HIDREV_0_CHIPID_WOFFSET                     0x0
#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT                     _MK_MASK_CONST(0x19)
#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_CHIPID_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_CHIPID_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_HIDREV_0_MINORREV_SHIFT                     _MK_SHIFT_CONST(16)
#define APB_MISC_GP_HIDREV_0_MINORREV_FIELD                     _MK_FIELD_CONST(0xf, APB_MISC_GP_HIDREV_0_MINORREV_SHIFT)
#define APB_MISC_GP_HIDREV_0_MINORREV_RANGE                     19:16
#define APB_MISC_GP_HIDREV_0_MINORREV_WOFFSET                   0x0
#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT                   _MK_MASK_CONST(0x2)
#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_MINORREV_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_MINORREV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Reserved address 0x808

// Reserved address 0x80c

// Register APB_MISC_GP_ASDBGREG_0
#define APB_MISC_GP_ASDBGREG_0                  _MK_ADDR_CONST(0x810)
#define APB_MISC_GP_ASDBGREG_0_SECURE                   0x0
#define APB_MISC_GP_ASDBGREG_0_DUAL                     0x0
#define APB_MISC_GP_ASDBGREG_0_SCR                      0
#define APB_MISC_GP_ASDBGREG_0_WORD_COUNT                       0x1
#define APB_MISC_GP_ASDBGREG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_RESET_MASK                       _MK_MASK_CONST(0x3ff000c6)
#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_READ_MASK                        _MK_MASK_CONST(0x3ff000c6)
#define APB_MISC_GP_ASDBGREG_0_WRITE_MASK                       _MK_MASK_CONST(0x3ff000c6)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_RANGE                  1:1
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_WOFFSET                        0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DISABLE                        _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_ENABLE                 _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_RANGE                        2:2
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_ENABLE                       _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT                        _MK_SHIFT_CONST(6)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_FIELD                        _MK_FIELD_CONST(0x3, APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_RANGE                        7:6
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_ENABLE                       _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT                   _MK_SHIFT_CONST(20)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_FIELD                   _MK_FIELD_CONST(0x3, APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_RANGE                   21:20
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_WOFFSET                 0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_ENABLE                  _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT                        _MK_SHIFT_CONST(22)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_FIELD                        _MK_FIELD_CONST(0x3, APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_RANGE                        23:22
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT                       _MK_SHIFT_CONST(24)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_FIELD                       _MK_FIELD_CONST(0x3, APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_RANGE                       25:24
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_WOFFSET                     0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT                       _MK_SHIFT_CONST(26)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_FIELD                       _MK_FIELD_CONST(0x3, APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_RANGE                       27:26
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_WOFFSET                     0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT                        _MK_SHIFT_CONST(28)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_FIELD                        _MK_FIELD_CONST(0x3, APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_RANGE                        29:28
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x814

// Reserved address 0x818

// Reserved address 0x81c

// Reserved address 0x820

// Reserved address 0x824

// Reserved address 0x828

// Reserved address 0x82c

// Reserved address 0x830

// Reserved address 0x834

// Reserved address 0x838

// Reserved address 0x83c

// Reserved address 0x840

// Reserved address 0x844

// Reserved address 0x848

// Reserved address 0x84c

// Reserved address 0x850

// Reserved address 0x854

// Reserved address 0x858

// Reserved address 0x85c

// Register APB_MISC_GP_EMU_REVID_0
#define APB_MISC_GP_EMU_REVID_0                 _MK_ADDR_CONST(0x860)
#define APB_MISC_GP_EMU_REVID_0_SECURE                  0x0
#define APB_MISC_GP_EMU_REVID_0_DUAL                    0x0
#define APB_MISC_GP_EMU_REVID_0_SCR                     0
#define APB_MISC_GP_EMU_REVID_0_WORD_COUNT                      0x1
#define APB_MISC_GP_EMU_REVID_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_RESET_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_EMU_REVID_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_FIELD                   _MK_FIELD_CONST(0xff, APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_RANGE                   7:0
#define APB_MISC_GP_EMU_REVID_0_NETLIST_WOFFSET                 0x0
#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT                     _MK_SHIFT_CONST(8)
#define APB_MISC_GP_EMU_REVID_0_PATCH_FIELD                     _MK_FIELD_CONST(0xff, APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT)
#define APB_MISC_GP_EMU_REVID_0_PATCH_RANGE                     15:8
#define APB_MISC_GP_EMU_REVID_0_PATCH_WOFFSET                   0x0
#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_PATCH_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_PATCH_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMU_REVID_0_CORE_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_GP_EMU_REVID_0_CORE_FIELD                      _MK_FIELD_CONST(0xff, APB_MISC_GP_EMU_REVID_0_CORE_SHIFT)
#define APB_MISC_GP_EMU_REVID_0_CORE_RANGE                      23:16
#define APB_MISC_GP_EMU_REVID_0_CORE_WOFFSET                    0x0
#define APB_MISC_GP_EMU_REVID_0_CORE_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_CORE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_CORE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_CORE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_CORE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_CORE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMU_REVID_0_BOARD_SHIFT                     _MK_SHIFT_CONST(24)
#define APB_MISC_GP_EMU_REVID_0_BOARD_FIELD                     _MK_FIELD_CONST(0xff, APB_MISC_GP_EMU_REVID_0_BOARD_SHIFT)
#define APB_MISC_GP_EMU_REVID_0_BOARD_RANGE                     31:24
#define APB_MISC_GP_EMU_REVID_0_BOARD_WOFFSET                   0x0
#define APB_MISC_GP_EMU_REVID_0_BOARD_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_BOARD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_BOARD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_BOARD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_BOARD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_BOARD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_TRANSACTOR_SCRATCH_0
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0                        _MK_ADDR_CONST(0x864)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SECURE                         0x0
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_DUAL                   0x0
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SCR                    0
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WORD_COUNT                     0x1
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_FIELD                       _MK_FIELD_CONST(0xffffffff, APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_RANGE                       31:0
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_WOFFSET                     0x0
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_PADCTL_DFT_0
#define APB_MISC_GP_PADCTL_DFT_0                        _MK_ADDR_CONST(0x868)
#define APB_MISC_GP_PADCTL_DFT_0_SECURE                         0x0
#define APB_MISC_GP_PADCTL_DFT_0_DUAL                   0x0
#define APB_MISC_GP_PADCTL_DFT_0_SCR                    0
#define APB_MISC_GP_PADCTL_DFT_0_WORD_COUNT                     0x1
#define APB_MISC_GP_PADCTL_DFT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_PADCTL_DFT_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_FIELD                      _MK_FIELD_CONST(0x1, APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_RANGE                      0:0
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_WOFFSET                    0x0
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_ENABLE                     _MK_ENUM_CONST(1)

#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT                     _MK_SHIFT_CONST(1)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_FIELD                     _MK_FIELD_CONST(0x1, APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_RANGE                     1:1
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_WOFFSET                   0x0
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0                    _MK_ADDR_CONST(0x880)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SECURE                     0x0
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_DUAL                       0x0
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SCR                        0
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_WORD_COUNT                         0x1
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_FIELD                       _MK_FIELD_CONST(0xffffffff, APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SHIFT)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_RANGE                       31:0
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_WOFFSET                     0x0
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0                   _MK_ADDR_CONST(0x884)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SECURE                    0x0
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_DUAL                      0x0
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SCR                       0
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_WORD_COUNT                        0x1
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_FIELD                     _MK_FIELD_CONST(0xffffffff, APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SHIFT)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_RANGE                     31:0
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_WOFFSET                   0x0
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0                   _MK_ADDR_CONST(0x888)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SECURE                    0x0
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_DUAL                      0x0
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SCR                       0
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_WORD_COUNT                        0x1
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_FIELD                     _MK_FIELD_CONST(0xffffffff, APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SHIFT)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_RANGE                     31:0
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_WOFFSET                   0x0
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0                   _MK_ADDR_CONST(0x88c)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_SECURE                    0x0
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_DUAL                      0x0
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_SCR                       0
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_WORD_COUNT                        0x1
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_FIELD                     _MK_FIELD_CONST(0xffffffff, APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_SHIFT)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_RANGE                     31:0
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_WOFFSET                   0x0
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0_CPU2_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0                   _MK_ADDR_CONST(0x890)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_SECURE                    0x0
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_DUAL                      0x0
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_SCR                       0
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_WORD_COUNT                        0x1
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_FIELD                     _MK_FIELD_CONST(0xffffffff, APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_SHIFT)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_RANGE                     31:0
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_WOFFSET                   0x0
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0_CPU3_TRANSACTOR_SCRATCH_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Reserved address 0x894

// Reserved address 0x898

// Reserved address 0x89c

// Reserved address 0x8a0

// Reserved address 0x8a4

// Reserved address 0x8a8

// Reserved address 0x8ac

// Reserved address 0x8b0

// Reserved address 0x8b4

// Reserved address 0x8b8

// Reserved address 0x8bc

// Reserved address 0x8c0

// Reserved address 0x8c4

// Reserved address 0x8c8

// Reserved address 0x8cc

// Register APB_MISC_GP_ECO_SCRATCH0_0
#define APB_MISC_GP_ECO_SCRATCH0_0                      _MK_ADDR_CONST(0x8d0)
#define APB_MISC_GP_ECO_SCRATCH0_0_SECURE                       0x0
#define APB_MISC_GP_ECO_SCRATCH0_0_DUAL                         0x0
#define APB_MISC_GP_ECO_SCRATCH0_0_SCR                  0
#define APB_MISC_GP_ECO_SCRATCH0_0_WORD_COUNT                   0x1
#define APB_MISC_GP_ECO_SCRATCH0_0_RESET_VAL                    _MK_MASK_CONST(0xffff0000)
#define APB_MISC_GP_ECO_SCRATCH0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_ECO_SCRATCH0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ECO_SCRATCH0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ECO_SCRATCH0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_ECO_SCRATCH0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_FIELD                       _MK_FIELD_CONST(0xffffffff, APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_SHIFT)
#define APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_RANGE                       31:0
#define APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_WOFFSET                     0x0
#define APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_DEFAULT                     _MK_MASK_CONST(0xffff0000)
#define APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ECO_SCRATCH0_0_ECO_DATA_INIT_ENUM                   -65536


// Register APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0                   _MK_ADDR_CONST(0x8d4)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SECURE                    0x0
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_DUAL                      0x0
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SCR                       0
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_WORD_COUNT                        0x1
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SDMMC1_CLK_PAD_E_LPBK_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SDMMC1_CLK_PAD_E_LPBK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SDMMC1_CLK_PAD_E_LPBK_SHIFT)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SDMMC1_CLK_PAD_E_LPBK_RANGE                       0:0
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SDMMC1_CLK_PAD_E_LPBK_WOFFSET                     0x0
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SDMMC1_CLK_PAD_E_LPBK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SDMMC1_CLK_PAD_E_LPBK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SDMMC1_CLK_PAD_E_LPBK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SDMMC1_CLK_PAD_E_LPBK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SDMMC1_CLK_PAD_E_LPBK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0_SDMMC1_CLK_PAD_E_LPBK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0                   _MK_ADDR_CONST(0x8d8)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SECURE                    0x0
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_DUAL                      0x0
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SCR                       0
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_WORD_COUNT                        0x1
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SDMMC3_CLK_PAD_E_LPBK_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SDMMC3_CLK_PAD_E_LPBK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SDMMC3_CLK_PAD_E_LPBK_SHIFT)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SDMMC3_CLK_PAD_E_LPBK_RANGE                       0:0
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SDMMC3_CLK_PAD_E_LPBK_WOFFSET                     0x0
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SDMMC3_CLK_PAD_E_LPBK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SDMMC3_CLK_PAD_E_LPBK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SDMMC3_CLK_PAD_E_LPBK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SDMMC3_CLK_PAD_E_LPBK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SDMMC3_CLK_PAD_E_LPBK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0_SDMMC3_CLK_PAD_E_LPBK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0                     _MK_ADDR_CONST(0x8dc)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_SECURE                      0x0
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_DUAL                        0x0
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_SCR                         0
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0xff37)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0xff37)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0xff37)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0xff37)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_SHIFT                     _MK_SHIFT_CONST(8)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_FIELD                     _MK_FIELD_CONST(0xff, APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_RANGE                     15:8
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_WOFFSET                   0x0
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DEFAULT                   _MK_MASK_CONST(0xff)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLK_SHIFT                 _MK_SHIFT_CONST(5)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLK_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLK_RANGE                 5:5
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLK_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLK_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLKB_SHIFT                        _MK_SHIFT_CONST(4)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLKB_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLKB_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLKB_RANGE                        4:4
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLKB_WOFFSET                      0x0
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLKB_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLKB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLKB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLKB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLKB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_CLKB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQS_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQS_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQS_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQS_RANGE                 2:2
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQS_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQS_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQSB_SHIFT                        _MK_SHIFT_CONST(1)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQSB_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQSB_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQSB_RANGE                        1:1
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQSB_WOFFSET                      0x0
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQSB_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQSB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQSB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQSB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQSB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_INPUT_DQSB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_DEEP_LPBK_CLK_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_DEEP_LPBK_CLK_FIELD                     _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_DEEP_LPBK_CLK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_DEEP_LPBK_CLK_RANGE                     0:0
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_DEEP_LPBK_CLK_WOFFSET                   0x0
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_DEEP_LPBK_CLK_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_DEEP_LPBK_CLK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_DEEP_LPBK_CLK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_DEEP_LPBK_CLK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_DEEP_LPBK_CLK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0_EMMC2_PAD_E_DEEP_LPBK_CLK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0                     _MK_ADDR_CONST(0x8e0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_SECURE                      0x0
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_DUAL                        0x0
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_SCR                         0
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0xff37)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0xff37)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0xff37)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0xff37)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_SHIFT                     _MK_SHIFT_CONST(8)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_FIELD                     _MK_FIELD_CONST(0xff, APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_RANGE                     15:8
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_WOFFSET                   0x0
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DEFAULT                   _MK_MASK_CONST(0xff)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLK_SHIFT                 _MK_SHIFT_CONST(5)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLK_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLK_RANGE                 5:5
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLK_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLK_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLKB_SHIFT                        _MK_SHIFT_CONST(4)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLKB_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLKB_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLKB_RANGE                        4:4
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLKB_WOFFSET                      0x0
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLKB_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLKB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLKB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLKB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLKB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_CLKB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQS_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQS_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQS_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQS_RANGE                 2:2
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQS_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQS_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQSB_SHIFT                        _MK_SHIFT_CONST(1)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQSB_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQSB_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQSB_RANGE                        1:1
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQSB_WOFFSET                      0x0
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQSB_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQSB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQSB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQSB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQSB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_INPUT_DQSB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_DEEP_LPBK_CLK_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_DEEP_LPBK_CLK_FIELD                     _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_DEEP_LPBK_CLK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_DEEP_LPBK_CLK_RANGE                     0:0
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_DEEP_LPBK_CLK_WOFFSET                   0x0
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_DEEP_LPBK_CLK_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_DEEP_LPBK_CLK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_DEEP_LPBK_CLK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_DEEP_LPBK_CLK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_DEEP_LPBK_CLK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0_EMMC4_PAD_E_DEEP_LPBK_CLK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Reserved address 0x8e4

// Reserved address 0x8e8

// Reserved address 0x8ec

// Reserved address 0x8f0

// Reserved address 0x8f4

// Reserved address 0x8f8

// Reserved address 0x8fc

// Reserved address 0x900

// Reserved address 0x904

// Reserved address 0x908

// Reserved address 0x90c

// Reserved address 0x910

// Reserved address 0x914

// Reserved address 0x918

// Reserved address 0x91c

// Reserved address 0x920

// Reserved address 0x924

// Reserved address 0x928

// Reserved address 0x92c

// Reserved address 0x930

// Reserved address 0x934

// Reserved address 0x938

// Reserved address 0x93c

// Reserved address 0x940

// Reserved address 0x944

// Reserved address 0x948

// Reserved address 0x94c

// Reserved address 0x950

// Reserved address 0x954

// Reserved address 0x958

// Reserved address 0x95c

// Reserved address 0x960

// Reserved address 0x964

// Reserved address 0x968

// Reserved address 0x96c

// Reserved address 0x970

// Reserved address 0x974

// Reserved address 0x978

// Reserved address 0x97c

// Reserved address 0x980

// Reserved address 0x984

// Reserved address 0x988

// Reserved address 0x98c

// Reserved address 0x990

// Reserved address 0x994

// Reserved address 0x998

// Reserved address 0x99c

// Reserved address 0x9a0

// Reserved address 0x9a4

// Reserved address 0x9a8

// Reserved address 0x9ac

// Reserved address 0x9b0

// Reserved address 0x9b4

// Reserved address 0x9b8

// Reserved address 0x9bc

// Reserved address 0x9c0

// Reserved address 0x9c4

// Reserved address 0x9c8

// Reserved address 0x9cc

// Reserved address 0x9d0

// Reserved address 0x9d4

// Reserved address 0x9d8

// Reserved address 0x9dc

// Reserved address 0x9e0

// Reserved address 0x9e4

// Reserved address 0x9e8

// Reserved address 0x9ec

// Reserved address 0x9f0

// Reserved address 0x9f4

// Reserved address 0x9f8

// Reserved address 0x9fc

// Reserved address 0xa00

// Reserved address 0xa04

// Reserved address 0xa08

// Reserved address 0xa0c

// Reserved address 0xa10

// Reserved address 0xa14

// Reserved address 0xa18

// Reserved address 0xa1c

// Reserved address 0xa20

// Reserved address 0xa24

// Reserved address 0xa28

// Reserved address 0xa2c

// Reserved address 0xa30

// Reserved address 0xa34

// Reserved address 0xa38

// Reserved address 0xa3c

// Reserved address 0xa40

// Reserved address 0xa44

// Reserved address 0xa48

// Reserved address 0xa4c

// Reserved address 0xa50

// Reserved address 0xa54

// Reserved address 0xa58

// Reserved address 0xa5c

// Reserved address 0xa60

// Reserved address 0xa64

// Reserved address 0xa68

// Reserved address 0xa6c

// Reserved address 0xa70

// Reserved address 0xa74

// Register APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0                      _MK_ADDR_CONST(0xa78)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_SECURE                       0x0
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_DUAL                         0x0
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_SCR                  0
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_WORD_COUNT                   0x1
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_RESET_VAL                    _MK_MASK_CONST(0x808000)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_RESET_MASK                   _MK_MASK_CONST(0x7f7f000)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_READ_MASK                    _MK_MASK_CONST(0x7f7f000)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x7f7f000)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVDN_SHIFT                        _MK_SHIFT_CONST(12)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVDN_FIELD                        _MK_FIELD_CONST(0x7f, APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVDN_RANGE                        18:12
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVDN_WOFFSET                      0x0
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVDN_DEFAULT                      _MK_MASK_CONST(0x8)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVDN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVUP_SHIFT                        _MK_SHIFT_CONST(20)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVUP_FIELD                        _MK_FIELD_CONST(0x7f, APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVUP_RANGE                        26:20
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVUP_WOFFSET                      0x0
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVUP_DEFAULT                      _MK_MASK_CONST(0x8)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVUP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0_CFG2TMC_QSPI_COMP_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0xa7c

// Reserved address 0xa80

// Reserved address 0xa84

// Reserved address 0xa88

// Reserved address 0xa8c

// Register APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0                       _MK_ADDR_CONST(0xa90)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_SECURE                        0x0
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_DUAL                  0x0
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_SCR                   0
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_WORD_COUNT                    0x1
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_RESET_VAL                     _MK_MASK_CONST(0x50000000)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_RESET_MASK                    _MK_MASK_CONST(0xf0000000)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_READ_MASK                     _MK_MASK_CONST(0xf0000000)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xf0000000)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVDN_SLWR_FIELD                     _MK_FIELD_CONST(0x3, APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVDN_SLWR_RANGE                     29:28
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVDN_SLWR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVDN_SLWR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVUP_SLWF_FIELD                     _MK_FIELD_CONST(0x3, APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVUP_SLWF_RANGE                     31:30
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVUP_SLWF_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0_CFG2TMC_QSPI_SCK_CFG_CAL_DRVUP_SLWF_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Reserved address 0xa94

// Register APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0                     _MK_ADDR_CONST(0xa98)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_DUAL                        0x0
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_SCR                         0
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0x808000)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf7f7f000)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf7f7f000)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf7f7f000)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVDN_FIELD                  _MK_FIELD_CONST(0x7f, APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVDN_RANGE                  18:12
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVDN_WOFFSET                        0x0
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x8)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVDN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVDN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVUP_FIELD                  _MK_FIELD_CONST(0x7f, APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVUP_RANGE                  26:20
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVUP_WOFFSET                        0x0
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x8)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVUP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_PAD_CAL_DRVUP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVUP_SLWF_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVUP_SLWF_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVUP_SLWF_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0                      _MK_ADDR_CONST(0xa9c)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_SECURE                       0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_DUAL                         0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_SCR                  0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_WORD_COUNT                   0x1
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_RESET_VAL                    _MK_MASK_CONST(0x7ffc310)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_RESET_MASK                   _MK_MASK_CONST(0xf7ffffff)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_READ_MASK                    _MK_MASK_CONST(0xf7ffffff)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_WRITE_MASK                   _MK_MASK_CONST(0xf7ffffff)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_SCH_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_SCH_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_SCH_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_SCH_RANGE                        0:0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_SCH_WOFFSET                      0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_SCH_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_SCH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_SCH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_SCH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_SCH_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_SCH_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_PREEMP_SHIFT                     _MK_SHIFT_CONST(1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_PREEMP_FIELD                     _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_PREEMP_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_PREEMP_RANGE                     1:1
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_PREEMP_WOFFSET                   0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_PREEMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_PREEMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_PREEMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_PREEMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_PREEMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_E_PREEMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_COMP_SHIFT                   _MK_SHIFT_CONST(2)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_COMP_FIELD                   _MK_FIELD_CONST(0x3f, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_COMP_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_COMP_RANGE                   7:2
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_COMP_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_COMP_DEFAULT                 _MK_MASK_CONST(0x4)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_COMP_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_COMP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_COMP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_COMP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_COMP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_COMP_SHIFT                   _MK_SHIFT_CONST(8)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_COMP_FIELD                   _MK_FIELD_CONST(0x3f, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_COMP_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_COMP_RANGE                   13:8
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_COMP_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_COMP_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_COMP_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_COMP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_COMP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_COMP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_COMP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLK_PARK_SHIFT                        _MK_SHIFT_CONST(14)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLK_PARK_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLK_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLK_PARK_RANGE                        14:14
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLK_PARK_WOFFSET                      0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLK_PARK_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLK_PARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLK_PARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLK_PARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLK_PARK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLK_PARK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLKB_PARK_SHIFT                       _MK_SHIFT_CONST(15)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLKB_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLKB_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLKB_PARK_RANGE                       15:15
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLKB_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLKB_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLKB_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLKB_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLKB_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLKB_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CLKB_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQS_PARK_SHIFT                        _MK_SHIFT_CONST(16)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQS_PARK_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQS_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQS_PARK_RANGE                        16:16
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQS_PARK_WOFFSET                      0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQS_PARK_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQS_PARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQS_PARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQS_PARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQS_PARK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQS_PARK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQSB_PARK_SHIFT                       _MK_SHIFT_CONST(17)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQSB_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQSB_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQSB_PARK_RANGE                       17:17
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQSB_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQSB_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQSB_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQSB_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQSB_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQSB_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DQSB_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CMD_PARK_SHIFT                        _MK_SHIFT_CONST(18)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CMD_PARK_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CMD_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CMD_PARK_RANGE                        18:18
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CMD_PARK_WOFFSET                      0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CMD_PARK_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CMD_PARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CMD_PARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CMD_PARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CMD_PARK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_CMD_PARK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT0_PARK_SHIFT                       _MK_SHIFT_CONST(19)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT0_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT0_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT0_PARK_RANGE                       19:19
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT0_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT0_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT0_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT0_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT0_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT0_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT0_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT1_PARK_SHIFT                       _MK_SHIFT_CONST(20)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT1_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT1_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT1_PARK_RANGE                       20:20
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT1_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT1_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT1_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT1_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT1_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT1_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT1_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT2_PARK_SHIFT                       _MK_SHIFT_CONST(21)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT2_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT2_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT2_PARK_RANGE                       21:21
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT2_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT2_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT2_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT2_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT2_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT2_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT2_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT3_PARK_SHIFT                       _MK_SHIFT_CONST(22)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT3_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT3_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT3_PARK_RANGE                       22:22
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT3_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT3_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT3_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT3_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT3_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT3_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT3_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT4_PARK_SHIFT                       _MK_SHIFT_CONST(23)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT4_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT4_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT4_PARK_RANGE                       23:23
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT4_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT4_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT4_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT4_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT4_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT4_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT4_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT5_PARK_SHIFT                       _MK_SHIFT_CONST(24)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT5_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT5_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT5_PARK_RANGE                       24:24
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT5_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT5_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT5_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT5_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT5_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT5_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT5_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT6_PARK_SHIFT                       _MK_SHIFT_CONST(25)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT6_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT6_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT6_PARK_RANGE                       25:25
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT6_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT6_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT6_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT6_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT6_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT6_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT6_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT7_PARK_SHIFT                       _MK_SHIFT_CONST(26)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT7_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT7_PARK_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT7_PARK_RANGE                       26:26
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT7_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT7_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT7_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT7_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT7_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT7_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_MISC2PMC_EMMC2_DAT7_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_SLWR_SHIFT                   _MK_SHIFT_CONST(28)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_SLWR_FIELD                   _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_SLWR_RANGE                   29:28
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_SLWR_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_SLWR_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_SLWR_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_SLWR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_SLWR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_SLWR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVDN_SLWR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_SLWF_SHIFT                   _MK_SHIFT_CONST(30)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_SLWF_FIELD                   _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_SLWF_RANGE                   31:30
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_SLWF_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_SLWF_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_SLWF_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_SLWF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_SLWF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_SLWF_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DRVUP_SLWF_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0                     _MK_ADDR_CONST(0xaa0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_DUAL                        0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_SCR                         0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0x155555)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0x3fffff)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffff)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_DRV_TYPE_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_DRV_TYPE_FIELD                        _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_DRV_TYPE_RANGE                        1:0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_DRV_TYPE_WOFFSET                      0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_DRV_TYPE_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_DRV_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_DRV_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_DRV_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_DRV_TYPE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_DRV_TYPE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_DRV_TYPE_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_DRV_TYPE_FIELD                        _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_DRV_TYPE_RANGE                        3:2
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_DRV_TYPE_WOFFSET                      0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_DRV_TYPE_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_DRV_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_DRV_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_DRV_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_DRV_TYPE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_DRV_TYPE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_DRV_TYPE_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_DRV_TYPE_FIELD                       _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_DRV_TYPE_RANGE                       5:4
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_DRV_TYPE_WOFFSET                     0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_DRV_TYPE_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_DRV_TYPE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_DRV_TYPE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_DRV_TYPE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_DRV_TYPE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_DRV_TYPE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(6)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_DRV_TYPE_RANGE                 7:6
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(8)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_DRV_TYPE_RANGE                 9:8
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(10)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_DRV_TYPE_RANGE                 11:10
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(12)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_DRV_TYPE_RANGE                 13:12
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(14)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_DRV_TYPE_RANGE                 15:14
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(16)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_DRV_TYPE_RANGE                 17:16
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(18)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_DRV_TYPE_RANGE                 19:18
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(20)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_DRV_TYPE_RANGE                 21:20
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0                 _MK_ADDR_CONST(0xaa4)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_SECURE                  0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_DUAL                    0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_SCR                     0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_WORD_COUNT                      0x1
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_RESET_VAL                       _MK_MASK_CONST(0x26aaaa6)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_RESET_MASK                      _MK_MASK_CONST(0x3ffffff)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_READ_MASK                       _MK_MASK_CONST(0x3ffffff)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x3ffffff)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLD_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLD_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLD_RANGE                  0:0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLD_WOFFSET                        0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLU_SHIFT                  _MK_SHIFT_CONST(1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLU_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLU_RANGE                  1:1
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLU_WOFFSET                        0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLU_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLU_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CMD_PUPD_PULLU_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLD_SHIFT                  _MK_SHIFT_CONST(2)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLD_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLD_RANGE                  2:2
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLD_WOFFSET                        0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLD_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLU_SHIFT                  _MK_SHIFT_CONST(3)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLU_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLU_RANGE                  3:3
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLU_WOFFSET                        0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLU_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLU_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLK_PUPD_PULLU_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLD_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLD_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLD_RANGE                 4:4
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLD_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLU_SHIFT                 _MK_SHIFT_CONST(5)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLU_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLU_RANGE                 5:5
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLU_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLU_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLU_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_CLKB_PUPD_PULLU_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(6)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLD_RANGE                   6:6
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(7)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLU_RANGE                   7:7
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D0_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(8)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLD_RANGE                   8:8
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(9)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLU_RANGE                   9:9
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D1_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(10)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLD_RANGE                   10:10
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(11)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLU_RANGE                   11:11
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D2_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(12)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLD_RANGE                   12:12
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(13)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLU_RANGE                   13:13
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D3_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(14)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLD_RANGE                   14:14
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(15)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLU_RANGE                   15:15
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D4_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(16)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLD_RANGE                   16:16
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(17)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLU_RANGE                   17:17
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D5_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(18)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLD_RANGE                   18:18
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(19)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLU_RANGE                   19:19
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D6_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(20)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLD_RANGE                   20:20
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(21)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLU_RANGE                   21:21
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_D7_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLD_SHIFT                  _MK_SHIFT_CONST(22)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLD_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLD_RANGE                  22:22
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLD_WOFFSET                        0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLD_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLU_SHIFT                  _MK_SHIFT_CONST(23)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLU_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLU_RANGE                  23:23
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLU_WOFFSET                        0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLU_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLU_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQS_PUPD_PULLU_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLD_SHIFT                 _MK_SHIFT_CONST(24)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLD_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLD_RANGE                 24:24
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLD_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLU_SHIFT                 _MK_SHIFT_CONST(25)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLU_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLU_RANGE                 25:25
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLU_WOFFSET                       0x0
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLU_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLU_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC2_PAD_DQSB_PUPD_PULLU_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Reserved address 0xaa8

// Reserved address 0xaac

// Register APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0                     _MK_ADDR_CONST(0xab0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_DUAL                        0x0
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_SCR                         0
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0x808000)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf7f7f000)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf7f7f000)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf7f7f000)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVDN_FIELD                  _MK_FIELD_CONST(0x7f, APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVDN_RANGE                  18:12
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVDN_WOFFSET                        0x0
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x8)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVDN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVDN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVUP_FIELD                  _MK_FIELD_CONST(0x7f, APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVUP_RANGE                  26:20
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVUP_WOFFSET                        0x0
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x8)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVUP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_PAD_CAL_DRVUP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVDN_SLWR_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVDN_SLWR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVDN_SLWR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVUP_SLWF_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVUP_SLWF_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0_CFG2TMC_SDMMC3_CLK_CFG_CAL_DRVUP_SLWF_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0                      _MK_ADDR_CONST(0xab4)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_SECURE                       0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_DUAL                         0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_SCR                  0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_WORD_COUNT                   0x1
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_RESET_VAL                    _MK_MASK_CONST(0x7ffc310)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_RESET_MASK                   _MK_MASK_CONST(0xf7ffffff)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_READ_MASK                    _MK_MASK_CONST(0xf7ffffff)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_WRITE_MASK                   _MK_MASK_CONST(0xf7ffffff)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_SCH_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_SCH_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_SCH_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_SCH_RANGE                        0:0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_SCH_WOFFSET                      0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_SCH_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_SCH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_SCH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_SCH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_SCH_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_SCH_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_PREEMP_SHIFT                     _MK_SHIFT_CONST(1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_PREEMP_FIELD                     _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_PREEMP_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_PREEMP_RANGE                     1:1
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_PREEMP_WOFFSET                   0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_PREEMP_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_PREEMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_PREEMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_PREEMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_PREEMP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_E_PREEMP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT                   _MK_SHIFT_CONST(2)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_COMP_FIELD                   _MK_FIELD_CONST(0x3f, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_COMP_RANGE                   7:2
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_COMP_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_COMP_DEFAULT                 _MK_MASK_CONST(0x4)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_COMP_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_COMP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_COMP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_COMP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_COMP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT                   _MK_SHIFT_CONST(8)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_COMP_FIELD                   _MK_FIELD_CONST(0x3f, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_COMP_RANGE                   13:8
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_COMP_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_COMP_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_COMP_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_COMP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_COMP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_COMP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_COMP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLK_PARK_SHIFT                        _MK_SHIFT_CONST(14)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLK_PARK_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLK_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLK_PARK_RANGE                        14:14
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLK_PARK_WOFFSET                      0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLK_PARK_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLK_PARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLK_PARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLK_PARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLK_PARK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLK_PARK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLKB_PARK_SHIFT                       _MK_SHIFT_CONST(15)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLKB_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLKB_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLKB_PARK_RANGE                       15:15
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLKB_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLKB_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLKB_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLKB_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLKB_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLKB_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CLKB_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQS_PARK_SHIFT                        _MK_SHIFT_CONST(16)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQS_PARK_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQS_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQS_PARK_RANGE                        16:16
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQS_PARK_WOFFSET                      0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQS_PARK_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQS_PARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQS_PARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQS_PARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQS_PARK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQS_PARK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQSB_PARK_SHIFT                       _MK_SHIFT_CONST(17)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQSB_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQSB_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQSB_PARK_RANGE                       17:17
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQSB_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQSB_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQSB_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQSB_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQSB_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQSB_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DQSB_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CMD_PARK_SHIFT                        _MK_SHIFT_CONST(18)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CMD_PARK_FIELD                        _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CMD_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CMD_PARK_RANGE                        18:18
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CMD_PARK_WOFFSET                      0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CMD_PARK_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CMD_PARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CMD_PARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CMD_PARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CMD_PARK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_CMD_PARK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT0_PARK_SHIFT                       _MK_SHIFT_CONST(19)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT0_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT0_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT0_PARK_RANGE                       19:19
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT0_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT0_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT0_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT0_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT0_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT0_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT0_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT1_PARK_SHIFT                       _MK_SHIFT_CONST(20)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT1_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT1_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT1_PARK_RANGE                       20:20
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT1_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT1_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT1_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT1_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT1_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT1_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT1_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT2_PARK_SHIFT                       _MK_SHIFT_CONST(21)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT2_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT2_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT2_PARK_RANGE                       21:21
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT2_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT2_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT2_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT2_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT2_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT2_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT2_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT3_PARK_SHIFT                       _MK_SHIFT_CONST(22)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT3_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT3_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT3_PARK_RANGE                       22:22
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT3_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT3_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT3_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT3_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT3_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT3_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT3_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT4_PARK_SHIFT                       _MK_SHIFT_CONST(23)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT4_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT4_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT4_PARK_RANGE                       23:23
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT4_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT4_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT4_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT4_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT4_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT4_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT4_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT5_PARK_SHIFT                       _MK_SHIFT_CONST(24)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT5_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT5_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT5_PARK_RANGE                       24:24
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT5_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT5_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT5_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT5_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT5_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT5_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT5_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT6_PARK_SHIFT                       _MK_SHIFT_CONST(25)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT6_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT6_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT6_PARK_RANGE                       25:25
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT6_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT6_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT6_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT6_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT6_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT6_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT6_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT7_PARK_SHIFT                       _MK_SHIFT_CONST(26)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT7_PARK_FIELD                       _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT7_PARK_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT7_PARK_RANGE                       26:26
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT7_PARK_WOFFSET                     0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT7_PARK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT7_PARK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT7_PARK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT7_PARK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT7_PARK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_MISC2PMC_EMMC4_DAT7_PARK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_SLWR_SHIFT                   _MK_SHIFT_CONST(28)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_SLWR_FIELD                   _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_SLWR_RANGE                   29:28
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_SLWR_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_SLWR_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_SLWR_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_SLWR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_SLWR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_SLWR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVDN_SLWR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_SLWF_SHIFT                   _MK_SHIFT_CONST(30)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_SLWF_FIELD                   _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_SLWF_RANGE                   31:30
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_SLWF_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_SLWF_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_SLWF_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_SLWF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_SLWF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_SLWF_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DRVUP_SLWF_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0                     _MK_ADDR_CONST(0xab8)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_DUAL                        0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_SCR                         0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0x155555)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0x3fffff)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffff)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_DRV_TYPE_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_DRV_TYPE_FIELD                        _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_DRV_TYPE_RANGE                        1:0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_DRV_TYPE_WOFFSET                      0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_DRV_TYPE_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_DRV_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_DRV_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_DRV_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_DRV_TYPE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_DRV_TYPE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_DRV_TYPE_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_DRV_TYPE_FIELD                        _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_DRV_TYPE_RANGE                        3:2
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_DRV_TYPE_WOFFSET                      0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_DRV_TYPE_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_DRV_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_DRV_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_DRV_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_DRV_TYPE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_DRV_TYPE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_DRV_TYPE_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_DRV_TYPE_FIELD                       _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_DRV_TYPE_RANGE                       5:4
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_DRV_TYPE_WOFFSET                     0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_DRV_TYPE_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_DRV_TYPE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_DRV_TYPE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_DRV_TYPE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_DRV_TYPE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_DRV_TYPE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(6)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_DRV_TYPE_RANGE                 7:6
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(8)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_DRV_TYPE_RANGE                 9:8
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(10)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_DRV_TYPE_RANGE                 11:10
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(12)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_DRV_TYPE_RANGE                 13:12
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(14)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_DRV_TYPE_RANGE                 15:14
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(16)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_DRV_TYPE_RANGE                 17:16
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(18)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_DRV_TYPE_RANGE                 19:18
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_DRV_TYPE_SHIFT                 _MK_SHIFT_CONST(20)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_DRV_TYPE_FIELD                 _MK_FIELD_CONST(0x3, APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_DRV_TYPE_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_DRV_TYPE_RANGE                 21:20
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_DRV_TYPE_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_DRV_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_DRV_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_DRV_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_DRV_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_DRV_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_DRV_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0                 _MK_ADDR_CONST(0xabc)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_SECURE                  0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_DUAL                    0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_SCR                     0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_WORD_COUNT                      0x1
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_RESET_VAL                       _MK_MASK_CONST(0x26aaaa6)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_RESET_MASK                      _MK_MASK_CONST(0x3ffffff)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_READ_MASK                       _MK_MASK_CONST(0x3ffffff)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x3ffffff)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLD_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLD_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLD_RANGE                  0:0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLD_WOFFSET                        0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU_SHIFT                  _MK_SHIFT_CONST(1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU_RANGE                  1:1
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU_WOFFSET                        0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD_SHIFT                  _MK_SHIFT_CONST(2)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD_RANGE                  2:2
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD_WOFFSET                        0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLU_SHIFT                  _MK_SHIFT_CONST(3)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLU_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLU_RANGE                  3:3
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLU_WOFFSET                        0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLU_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLU_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLU_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLD_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLD_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLD_RANGE                 4:4
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLD_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLU_SHIFT                 _MK_SHIFT_CONST(5)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLU_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLU_RANGE                 5:5
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLU_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLU_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLU_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_CLKB_PUPD_PULLU_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(6)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLD_RANGE                   6:6
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(7)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLU_RANGE                   7:7
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D0_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(8)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLD_RANGE                   8:8
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(9)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLU_RANGE                   9:9
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D1_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(10)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLD_RANGE                   10:10
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(11)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLU_RANGE                   11:11
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D2_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(12)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLD_RANGE                   12:12
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(13)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLU_RANGE                   13:13
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D3_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(14)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLD_RANGE                   14:14
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(15)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLU_RANGE                   15:15
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D4_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(16)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLD_RANGE                   16:16
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(17)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLU_RANGE                   17:17
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D5_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(18)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLD_RANGE                   18:18
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(19)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLU_RANGE                   19:19
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D6_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLD_SHIFT                   _MK_SHIFT_CONST(20)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLD_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLD_RANGE                   20:20
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLD_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLU_SHIFT                   _MK_SHIFT_CONST(21)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLU_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLU_RANGE                   21:21
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLU_WOFFSET                 0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLU_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLU_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_D7_PUPD_PULLU_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD_SHIFT                  _MK_SHIFT_CONST(22)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD_RANGE                  22:22
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD_WOFFSET                        0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLU_SHIFT                  _MK_SHIFT_CONST(23)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLU_FIELD                  _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLU_RANGE                  23:23
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLU_WOFFSET                        0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLU_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLU_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLU_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLD_SHIFT                 _MK_SHIFT_CONST(24)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLD_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLD_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLD_RANGE                 24:24
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLD_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLU_SHIFT                 _MK_SHIFT_CONST(25)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLU_FIELD                 _MK_FIELD_CONST(0x1, APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLU_SHIFT)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLU_RANGE                 25:25
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLU_WOFFSET                       0x0
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLU_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLU_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0_CFG2TMC_EMMC4_PAD_DQSB_PUPD_PULLU_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Reserved address 0xac0

// Reserved address 0xac4

// Reserved address 0xac8

// Reserved address 0xacc

// Reserved address 0xad0

// Reserved address 0xad4

// Reserved address 0xad8

// Reserved address 0xadc

// Reserved address 0xae0

// Reserved address 0xae4

// Reserved address 0xae8

// Reserved address 0xaec

// Reserved address 0xaf0

// Reserved address 0xaf4

// Reserved address 0xaf8

// Reserved address 0xafc

// Reserved address 0xb00

// Reserved address 0xb04

// Reserved address 0xb08

// Reserved address 0xb0c

// Reserved address 0xb10

// Reserved address 0xb14

// Reserved address 0xb18

// Reserved address 0xb1c

// Reserved address 0xb20

// Reserved address 0xb24

// Reserved address 0xb28

// Reserved address 0xb2c

// Reserved address 0xb30

// Reserved address 0xb34

// Reserved address 0xb38

// Reserved address 0xb3c

// Reserved address 0xb40

// Reserved address 0xb44

// Reserved address 0xb48

// Reserved address 0xb4c

// Reserved address 0xb50

// Reserved address 0xb54

// Reserved address 0xb58

// Reserved address 0xb5c

// Reserved address 0xb60

// Reserved address 0xb64

// Reserved address 0xb68

// Reserved address 0xb6c

// Reserved address 0xb70

// Reserved address 0xb74

// Register APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0                     _MK_ADDR_CONST(0xb78)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_SECURE                      0x0
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_DUAL                        0x0
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_SCR                         0
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_QSPI_SCK_PAD_E_LPBK_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_QSPI_SCK_PAD_E_LPBK_FIELD                   _MK_FIELD_CONST(0x1, APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_QSPI_SCK_PAD_E_LPBK_SHIFT)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_QSPI_SCK_PAD_E_LPBK_RANGE                   0:0
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_QSPI_SCK_PAD_E_LPBK_WOFFSET                 0x0
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_QSPI_SCK_PAD_E_LPBK_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_QSPI_SCK_PAD_E_LPBK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_QSPI_SCK_PAD_E_LPBK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_QSPI_SCK_PAD_E_LPBK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_QSPI_SCK_PAD_E_LPBK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0_QSPI_SCK_PAD_E_LPBK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARAPB_MISC_REGS(_op_) \
_op_(APB_MISC_GP_HIDREV_0) \
_op_(APB_MISC_GP_ASDBGREG_0) \
_op_(APB_MISC_GP_EMU_REVID_0) \
_op_(APB_MISC_GP_TRANSACTOR_SCRATCH_0) \
_op_(APB_MISC_GP_PADCTL_DFT_0) \
_op_(APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0) \
_op_(APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0) \
_op_(APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0) \
_op_(APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH_0) \
_op_(APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0) \
_op_(APB_MISC_GP_ECO_SCRATCH0_0) \
_op_(APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL_0) \
_op_(APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL_0) \
_op_(APB_MISC_GP_EMMC2_PAD_CFG_CONTROL_0) \
_op_(APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0) \
_op_(APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0) \
_op_(APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0) \
_op_(APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0) \
_op_(APB_MISC_GP_EMMC2_PAD_CFGPADCTRL_0) \
_op_(APB_MISC_GP_EMMC2_PAD_DRV_TYPE_CFGPADCTRL_0) \
_op_(APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0) \
_op_(APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0) \
_op_(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL_0) \
_op_(APB_MISC_GP_EMMC4_PAD_DRV_TYPE_CFGPADCTRL_0) \
_op_(APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0) \
_op_(APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_APB_MISC   0x00000000
#define BASE_ADDRESS_APB_MISC_GP        0x00000800

//
// ARAPB_MISC REGISTER BANKS
//

#define APB_MISC_GP0_FIRST_REG 0x0804 // APB_MISC_GP_HIDREV_0
#define APB_MISC_GP0_LAST_REG 0x0804 // APB_MISC_GP_HIDREV_0
#define APB_MISC_GP1_FIRST_REG 0x0810 // APB_MISC_GP_ASDBGREG_0
#define APB_MISC_GP1_LAST_REG 0x0810 // APB_MISC_GP_ASDBGREG_0
#define APB_MISC_GP2_FIRST_REG 0x0860 // APB_MISC_GP_EMU_REVID_0
#define APB_MISC_GP2_LAST_REG 0x0868 // APB_MISC_GP_PADCTL_DFT_0
#define APB_MISC_GP3_FIRST_REG 0x0880 // APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0
#define APB_MISC_GP3_LAST_REG 0x0890 // APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH_0
#define APB_MISC_GP4_FIRST_REG 0x08d0 // APB_MISC_GP_ECO_SCRATCH0_0
#define APB_MISC_GP4_LAST_REG 0x08e0 // APB_MISC_GP_EMMC4_PAD_CFG_CONTROL_0
#define APB_MISC_GP5_FIRST_REG 0x0a78 // APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0
#define APB_MISC_GP5_LAST_REG 0x0a78 // APB_MISC_GP_QSPI_COMP_CFGPADCTRL_0
#define APB_MISC_GP6_FIRST_REG 0x0a90 // APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0
#define APB_MISC_GP6_LAST_REG 0x0a90 // APB_MISC_GP_QSPI_SCK_CFGPADCTRL_0
#define APB_MISC_GP7_FIRST_REG 0x0a98 // APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL_0
#define APB_MISC_GP7_LAST_REG 0x0aa4 // APB_MISC_GP_EMMC2_PAD_PUPD_CFGPADCTRL_0
#define APB_MISC_GP8_FIRST_REG 0x0ab0 // APB_MISC_GP_SDMMC3_PAD_CFGPADCTRL_0
#define APB_MISC_GP8_LAST_REG 0x0abc // APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL_0
#define APB_MISC_GP9_FIRST_REG 0x0b78 // APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0
#define APB_MISC_GP9_LAST_REG 0x0b78 // APB_MISC_GP_QSPI_SCK_LPBK_CONTROL_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARAPB_MISC_H_INC_
