//
// Copyright (c) 2016 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARINTR_CTLR_H_INC_
#define ___ARINTR_CTLR_H_INC_

// Register INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0                        _MK_ADDR_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0                        _MK_ADDR_CONST(0x4)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE0_IER_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0                 _MK_ADDR_CONST(0x8)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0                     _MK_ADDR_CONST(0xc)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0                     _MK_ADDR_CONST(0x10)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0                   _MK_ADDR_CONST(0x14)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0                 _MK_ADDR_CONST(0x18)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0                 _MK_ADDR_CONST(0x1c)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0                     _MK_ADDR_CONST(0x20)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0                     _MK_ADDR_CONST(0x24)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0                        _MK_ADDR_CONST(0x40)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0                        _MK_ADDR_CONST(0x44)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE1_IER_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0                 _MK_ADDR_CONST(0x48)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0                     _MK_ADDR_CONST(0x4c)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0                     _MK_ADDR_CONST(0x50)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0                   _MK_ADDR_CONST(0x54)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0                 _MK_ADDR_CONST(0x58)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0                 _MK_ADDR_CONST(0x5c)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0                     _MK_ADDR_CONST(0x60)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0                     _MK_ADDR_CONST(0x64)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0                        _MK_ADDR_CONST(0x80)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0                        _MK_ADDR_CONST(0x84)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE2_IER_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0                 _MK_ADDR_CONST(0x88)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0                     _MK_ADDR_CONST(0x8c)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0                     _MK_ADDR_CONST(0x90)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0                   _MK_ADDR_CONST(0x94)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0                 _MK_ADDR_CONST(0x98)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0                 _MK_ADDR_CONST(0x9c)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0                     _MK_ADDR_CONST(0xa0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0                     _MK_ADDR_CONST(0xa4)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0                        _MK_ADDR_CONST(0xc0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0                        _MK_ADDR_CONST(0xc4)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE3_IER_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0                 _MK_ADDR_CONST(0xc8)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0                     _MK_ADDR_CONST(0xcc)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0                     _MK_ADDR_CONST(0xd0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0                   _MK_ADDR_CONST(0xd4)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0                 _MK_ADDR_CONST(0xd8)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0                 _MK_ADDR_CONST(0xdc)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0                     _MK_ADDR_CONST(0xe0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0                     _MK_ADDR_CONST(0xe4)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0                        _MK_ADDR_CONST(0x100)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0                        _MK_ADDR_CONST(0x104)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE4_IER_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0                 _MK_ADDR_CONST(0x108)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0                     _MK_ADDR_CONST(0x10c)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0                     _MK_ADDR_CONST(0x110)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0                   _MK_ADDR_CONST(0x114)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0                 _MK_ADDR_CONST(0x118)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0                 _MK_ADDR_CONST(0x11c)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0                     _MK_ADDR_CONST(0x120)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0                     _MK_ADDR_CONST(0x124)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0                        _MK_ADDR_CONST(0x140)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0                        _MK_ADDR_CONST(0x144)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE5_IER_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0                 _MK_ADDR_CONST(0x148)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0                     _MK_ADDR_CONST(0x14c)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0                     _MK_ADDR_CONST(0x150)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0                   _MK_ADDR_CONST(0x154)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0                 _MK_ADDR_CONST(0x158)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0                 _MK_ADDR_CONST(0x15c)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0                     _MK_ADDR_CONST(0x160)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0                     _MK_ADDR_CONST(0x164)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0                        _MK_ADDR_CONST(0x180)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0                        _MK_ADDR_CONST(0x184)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE6_IER_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0                 _MK_ADDR_CONST(0x188)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0                     _MK_ADDR_CONST(0x18c)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0                     _MK_ADDR_CONST(0x190)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0                   _MK_ADDR_CONST(0x194)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0                 _MK_ADDR_CONST(0x198)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0                 _MK_ADDR_CONST(0x19c)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0                     _MK_ADDR_CONST(0x1a0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0                     _MK_ADDR_CONST(0x1a4)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0                        _MK_ADDR_CONST(0x1c0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0                        _MK_ADDR_CONST(0x1c4)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE7_IER_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0                 _MK_ADDR_CONST(0x1c8)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0                     _MK_ADDR_CONST(0x1cc)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0                     _MK_ADDR_CONST(0x1d0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0                   _MK_ADDR_CONST(0x1d4)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0                 _MK_ADDR_CONST(0x1d8)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0                 _MK_ADDR_CONST(0x1dc)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0                     _MK_ADDR_CONST(0x1e0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0                     _MK_ADDR_CONST(0x1e4)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0                        _MK_ADDR_CONST(0x200)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0                        _MK_ADDR_CONST(0x204)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE8_IER_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0                 _MK_ADDR_CONST(0x208)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0                     _MK_ADDR_CONST(0x20c)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0                     _MK_ADDR_CONST(0x210)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0                   _MK_ADDR_CONST(0x214)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0                 _MK_ADDR_CONST(0x218)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0                 _MK_ADDR_CONST(0x21c)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0                     _MK_ADDR_CONST(0x220)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0                     _MK_ADDR_CONST(0x224)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0                  _MK_ADDR_CONST(0x7c0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0                  _MK_ADDR_CONST(0x7c4)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0                        _MK_ADDR_CONST(0x800)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0                        _MK_ADDR_CONST(0x804)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE0_IER_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0                 _MK_ADDR_CONST(0x808)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0                     _MK_ADDR_CONST(0x80c)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0                     _MK_ADDR_CONST(0x810)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0                   _MK_ADDR_CONST(0x814)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0                 _MK_ADDR_CONST(0x818)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0                 _MK_ADDR_CONST(0x81c)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0                     _MK_ADDR_CONST(0x820)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0                     _MK_ADDR_CONST(0x824)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0                        _MK_ADDR_CONST(0x840)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0                        _MK_ADDR_CONST(0x844)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE1_IER_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0                 _MK_ADDR_CONST(0x848)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0                     _MK_ADDR_CONST(0x84c)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0                     _MK_ADDR_CONST(0x850)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0                   _MK_ADDR_CONST(0x854)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0                 _MK_ADDR_CONST(0x858)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0                 _MK_ADDR_CONST(0x85c)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0                     _MK_ADDR_CONST(0x860)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0                     _MK_ADDR_CONST(0x864)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0                        _MK_ADDR_CONST(0x880)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0                        _MK_ADDR_CONST(0x884)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE2_IER_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0                 _MK_ADDR_CONST(0x888)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0                     _MK_ADDR_CONST(0x88c)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0                     _MK_ADDR_CONST(0x890)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0                   _MK_ADDR_CONST(0x894)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0                 _MK_ADDR_CONST(0x898)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0                 _MK_ADDR_CONST(0x89c)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0                     _MK_ADDR_CONST(0x8a0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0                     _MK_ADDR_CONST(0x8a4)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0                        _MK_ADDR_CONST(0x8c0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0                        _MK_ADDR_CONST(0x8c4)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE3_IER_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0                 _MK_ADDR_CONST(0x8c8)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0                     _MK_ADDR_CONST(0x8cc)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0                     _MK_ADDR_CONST(0x8d0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0                   _MK_ADDR_CONST(0x8d4)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0                 _MK_ADDR_CONST(0x8d8)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0                 _MK_ADDR_CONST(0x8dc)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0                     _MK_ADDR_CONST(0x8e0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0                     _MK_ADDR_CONST(0x8e4)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0                        _MK_ADDR_CONST(0x900)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0                        _MK_ADDR_CONST(0x904)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE4_IER_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0                 _MK_ADDR_CONST(0x908)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0                     _MK_ADDR_CONST(0x90c)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0                     _MK_ADDR_CONST(0x910)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0                   _MK_ADDR_CONST(0x914)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0                 _MK_ADDR_CONST(0x918)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0                 _MK_ADDR_CONST(0x91c)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0                     _MK_ADDR_CONST(0x920)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0                     _MK_ADDR_CONST(0x924)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0                        _MK_ADDR_CONST(0x940)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0                        _MK_ADDR_CONST(0x944)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE5_IER_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0                 _MK_ADDR_CONST(0x948)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0                     _MK_ADDR_CONST(0x94c)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0                     _MK_ADDR_CONST(0x950)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0                   _MK_ADDR_CONST(0x954)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0                 _MK_ADDR_CONST(0x958)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0                 _MK_ADDR_CONST(0x95c)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0                     _MK_ADDR_CONST(0x960)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0                     _MK_ADDR_CONST(0x964)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0                        _MK_ADDR_CONST(0x980)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0                        _MK_ADDR_CONST(0x984)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE6_IER_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0                 _MK_ADDR_CONST(0x988)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0                     _MK_ADDR_CONST(0x98c)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0                     _MK_ADDR_CONST(0x990)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0                   _MK_ADDR_CONST(0x994)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0                 _MK_ADDR_CONST(0x998)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0                 _MK_ADDR_CONST(0x99c)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0                     _MK_ADDR_CONST(0x9a0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0                     _MK_ADDR_CONST(0x9a4)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0                        _MK_ADDR_CONST(0x9c0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0                        _MK_ADDR_CONST(0x9c4)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE7_IER_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0                 _MK_ADDR_CONST(0x9c8)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0                     _MK_ADDR_CONST(0x9cc)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0                     _MK_ADDR_CONST(0x9d0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0                   _MK_ADDR_CONST(0x9d4)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0                 _MK_ADDR_CONST(0x9d8)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0                 _MK_ADDR_CONST(0x9dc)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0                     _MK_ADDR_CONST(0x9e0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0                     _MK_ADDR_CONST(0x9e4)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0                        _MK_ADDR_CONST(0xa00)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0                        _MK_ADDR_CONST(0xa04)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE8_IER_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0                 _MK_ADDR_CONST(0xa08)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0                     _MK_ADDR_CONST(0xa0c)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0                     _MK_ADDR_CONST(0xa10)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0                   _MK_ADDR_CONST(0xa14)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0                 _MK_ADDR_CONST(0xa18)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0                 _MK_ADDR_CONST(0xa1c)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0                     _MK_ADDR_CONST(0xa20)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0                     _MK_ADDR_CONST(0xa24)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0                  _MK_ADDR_CONST(0xfc0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0                  _MK_ADDR_CONST(0xfc4)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0                        _MK_ADDR_CONST(0x1000)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0                        _MK_ADDR_CONST(0x1004)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE0_IER_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0                 _MK_ADDR_CONST(0x1008)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0                     _MK_ADDR_CONST(0x100c)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0                     _MK_ADDR_CONST(0x1010)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0                   _MK_ADDR_CONST(0x1014)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0                 _MK_ADDR_CONST(0x1018)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0                 _MK_ADDR_CONST(0x101c)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0                     _MK_ADDR_CONST(0x1020)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0                     _MK_ADDR_CONST(0x1024)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0                        _MK_ADDR_CONST(0x1040)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0                        _MK_ADDR_CONST(0x1044)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE1_IER_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0                 _MK_ADDR_CONST(0x1048)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0                     _MK_ADDR_CONST(0x104c)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0                     _MK_ADDR_CONST(0x1050)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0                   _MK_ADDR_CONST(0x1054)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0                 _MK_ADDR_CONST(0x1058)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0                 _MK_ADDR_CONST(0x105c)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0                     _MK_ADDR_CONST(0x1060)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0                     _MK_ADDR_CONST(0x1064)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0                        _MK_ADDR_CONST(0x1080)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0                        _MK_ADDR_CONST(0x1084)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE2_IER_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0                 _MK_ADDR_CONST(0x1088)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0                     _MK_ADDR_CONST(0x108c)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0                     _MK_ADDR_CONST(0x1090)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0                   _MK_ADDR_CONST(0x1094)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0                 _MK_ADDR_CONST(0x1098)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0                 _MK_ADDR_CONST(0x109c)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0                     _MK_ADDR_CONST(0x10a0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0                     _MK_ADDR_CONST(0x10a4)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0                        _MK_ADDR_CONST(0x10c0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0                        _MK_ADDR_CONST(0x10c4)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE3_IER_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0                 _MK_ADDR_CONST(0x10c8)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0                     _MK_ADDR_CONST(0x10cc)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0                     _MK_ADDR_CONST(0x10d0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0                   _MK_ADDR_CONST(0x10d4)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0                 _MK_ADDR_CONST(0x10d8)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0                 _MK_ADDR_CONST(0x10dc)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0                     _MK_ADDR_CONST(0x10e0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0                     _MK_ADDR_CONST(0x10e4)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0                        _MK_ADDR_CONST(0x1100)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0                        _MK_ADDR_CONST(0x1104)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE4_IER_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0                 _MK_ADDR_CONST(0x1108)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0                     _MK_ADDR_CONST(0x110c)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0                     _MK_ADDR_CONST(0x1110)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0                   _MK_ADDR_CONST(0x1114)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0                 _MK_ADDR_CONST(0x1118)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0                 _MK_ADDR_CONST(0x111c)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0                     _MK_ADDR_CONST(0x1120)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0                     _MK_ADDR_CONST(0x1124)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0                        _MK_ADDR_CONST(0x1140)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0                        _MK_ADDR_CONST(0x1144)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE5_IER_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0                 _MK_ADDR_CONST(0x1148)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0                     _MK_ADDR_CONST(0x114c)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0                     _MK_ADDR_CONST(0x1150)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0                   _MK_ADDR_CONST(0x1154)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0                 _MK_ADDR_CONST(0x1158)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0                 _MK_ADDR_CONST(0x115c)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0                     _MK_ADDR_CONST(0x1160)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0                     _MK_ADDR_CONST(0x1164)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0                        _MK_ADDR_CONST(0x1180)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0                        _MK_ADDR_CONST(0x1184)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE6_IER_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0                 _MK_ADDR_CONST(0x1188)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0                     _MK_ADDR_CONST(0x118c)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0                     _MK_ADDR_CONST(0x1190)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0                   _MK_ADDR_CONST(0x1194)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0                 _MK_ADDR_CONST(0x1198)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0                 _MK_ADDR_CONST(0x119c)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0                     _MK_ADDR_CONST(0x11a0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0                     _MK_ADDR_CONST(0x11a4)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0                        _MK_ADDR_CONST(0x11c0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0                        _MK_ADDR_CONST(0x11c4)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE7_IER_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0                 _MK_ADDR_CONST(0x11c8)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0                     _MK_ADDR_CONST(0x11cc)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0                     _MK_ADDR_CONST(0x11d0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0                   _MK_ADDR_CONST(0x11d4)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0                 _MK_ADDR_CONST(0x11d8)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0                 _MK_ADDR_CONST(0x11dc)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0                     _MK_ADDR_CONST(0x11e0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0                     _MK_ADDR_CONST(0x11e4)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0                        _MK_ADDR_CONST(0x1200)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0                        _MK_ADDR_CONST(0x1204)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE8_IER_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0                 _MK_ADDR_CONST(0x1208)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0                     _MK_ADDR_CONST(0x120c)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0                     _MK_ADDR_CONST(0x1210)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0                   _MK_ADDR_CONST(0x1214)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0                 _MK_ADDR_CONST(0x1218)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0                 _MK_ADDR_CONST(0x121c)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0                     _MK_ADDR_CONST(0x1220)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0                     _MK_ADDR_CONST(0x1224)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0                  _MK_ADDR_CONST(0x17c0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0                  _MK_ADDR_CONST(0x17c4)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0                        _MK_ADDR_CONST(0x1800)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0                        _MK_ADDR_CONST(0x1804)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE0_IER_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0                 _MK_ADDR_CONST(0x1808)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0                     _MK_ADDR_CONST(0x180c)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0                     _MK_ADDR_CONST(0x1810)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0                   _MK_ADDR_CONST(0x1814)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0                 _MK_ADDR_CONST(0x1818)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0                 _MK_ADDR_CONST(0x181c)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0                     _MK_ADDR_CONST(0x1820)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0                     _MK_ADDR_CONST(0x1824)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0                        _MK_ADDR_CONST(0x1840)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0                        _MK_ADDR_CONST(0x1844)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE1_IER_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0                 _MK_ADDR_CONST(0x1848)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0                     _MK_ADDR_CONST(0x184c)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0                     _MK_ADDR_CONST(0x1850)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0                   _MK_ADDR_CONST(0x1854)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0                 _MK_ADDR_CONST(0x1858)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0                 _MK_ADDR_CONST(0x185c)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0                     _MK_ADDR_CONST(0x1860)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0                     _MK_ADDR_CONST(0x1864)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0                        _MK_ADDR_CONST(0x1880)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0                        _MK_ADDR_CONST(0x1884)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE2_IER_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0                 _MK_ADDR_CONST(0x1888)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0                     _MK_ADDR_CONST(0x188c)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0                     _MK_ADDR_CONST(0x1890)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0                   _MK_ADDR_CONST(0x1894)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0                 _MK_ADDR_CONST(0x1898)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0                 _MK_ADDR_CONST(0x189c)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0                     _MK_ADDR_CONST(0x18a0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0                     _MK_ADDR_CONST(0x18a4)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0                        _MK_ADDR_CONST(0x18c0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0                        _MK_ADDR_CONST(0x18c4)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE3_IER_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0                 _MK_ADDR_CONST(0x18c8)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0                     _MK_ADDR_CONST(0x18cc)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0                     _MK_ADDR_CONST(0x18d0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0                   _MK_ADDR_CONST(0x18d4)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0                 _MK_ADDR_CONST(0x18d8)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0                 _MK_ADDR_CONST(0x18dc)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0                     _MK_ADDR_CONST(0x18e0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0                     _MK_ADDR_CONST(0x18e4)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0                        _MK_ADDR_CONST(0x1900)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0                        _MK_ADDR_CONST(0x1904)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE4_IER_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0                 _MK_ADDR_CONST(0x1908)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0                     _MK_ADDR_CONST(0x190c)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0                     _MK_ADDR_CONST(0x1910)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0                   _MK_ADDR_CONST(0x1914)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0                 _MK_ADDR_CONST(0x1918)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0                 _MK_ADDR_CONST(0x191c)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0                     _MK_ADDR_CONST(0x1920)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0                     _MK_ADDR_CONST(0x1924)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0                        _MK_ADDR_CONST(0x1940)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0                        _MK_ADDR_CONST(0x1944)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE5_IER_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0                 _MK_ADDR_CONST(0x1948)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0                     _MK_ADDR_CONST(0x194c)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0                     _MK_ADDR_CONST(0x1950)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0                   _MK_ADDR_CONST(0x1954)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0                 _MK_ADDR_CONST(0x1958)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0                 _MK_ADDR_CONST(0x195c)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0                     _MK_ADDR_CONST(0x1960)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0                     _MK_ADDR_CONST(0x1964)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0                        _MK_ADDR_CONST(0x1980)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0                        _MK_ADDR_CONST(0x1984)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE6_IER_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0                 _MK_ADDR_CONST(0x1988)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0                     _MK_ADDR_CONST(0x198c)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0                     _MK_ADDR_CONST(0x1990)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0                   _MK_ADDR_CONST(0x1994)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0                 _MK_ADDR_CONST(0x1998)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0                 _MK_ADDR_CONST(0x199c)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0                     _MK_ADDR_CONST(0x19a0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0                     _MK_ADDR_CONST(0x19a4)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0                        _MK_ADDR_CONST(0x19c0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0                        _MK_ADDR_CONST(0x19c4)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE7_IER_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0                 _MK_ADDR_CONST(0x19c8)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0                     _MK_ADDR_CONST(0x19cc)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0                     _MK_ADDR_CONST(0x19d0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0                   _MK_ADDR_CONST(0x19d4)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0                 _MK_ADDR_CONST(0x19d8)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0                 _MK_ADDR_CONST(0x19dc)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0                     _MK_ADDR_CONST(0x19e0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0                     _MK_ADDR_CONST(0x19e4)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0                        _MK_ADDR_CONST(0x1a00)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0                        _MK_ADDR_CONST(0x1a04)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE8_IER_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0                 _MK_ADDR_CONST(0x1a08)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0                     _MK_ADDR_CONST(0x1a0c)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0                     _MK_ADDR_CONST(0x1a10)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0                   _MK_ADDR_CONST(0x1a14)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0                 _MK_ADDR_CONST(0x1a18)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0                 _MK_ADDR_CONST(0x1a1c)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0                     _MK_ADDR_CONST(0x1a20)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0                     _MK_ADDR_CONST(0x1a24)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0                  _MK_ADDR_CONST(0x1fc0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0                  _MK_ADDR_CONST(0x1fc4)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0                        _MK_ADDR_CONST(0x2000)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0                        _MK_ADDR_CONST(0x2004)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE0_IER_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0                 _MK_ADDR_CONST(0x2008)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0                     _MK_ADDR_CONST(0x200c)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0                     _MK_ADDR_CONST(0x2010)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0                   _MK_ADDR_CONST(0x2014)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0                 _MK_ADDR_CONST(0x2018)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0                 _MK_ADDR_CONST(0x201c)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0                     _MK_ADDR_CONST(0x2020)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0                     _MK_ADDR_CONST(0x2024)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0                        _MK_ADDR_CONST(0x2040)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0                        _MK_ADDR_CONST(0x2044)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE1_IER_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0                 _MK_ADDR_CONST(0x2048)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0                     _MK_ADDR_CONST(0x204c)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0                     _MK_ADDR_CONST(0x2050)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0                   _MK_ADDR_CONST(0x2054)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0                 _MK_ADDR_CONST(0x2058)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0                 _MK_ADDR_CONST(0x205c)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0                     _MK_ADDR_CONST(0x2060)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0                     _MK_ADDR_CONST(0x2064)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0                        _MK_ADDR_CONST(0x2080)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0                        _MK_ADDR_CONST(0x2084)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE2_IER_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0                 _MK_ADDR_CONST(0x2088)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0                     _MK_ADDR_CONST(0x208c)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0                     _MK_ADDR_CONST(0x2090)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0                   _MK_ADDR_CONST(0x2094)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0                 _MK_ADDR_CONST(0x2098)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0                 _MK_ADDR_CONST(0x209c)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0                     _MK_ADDR_CONST(0x20a0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0                     _MK_ADDR_CONST(0x20a4)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0                        _MK_ADDR_CONST(0x20c0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0                        _MK_ADDR_CONST(0x20c4)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE3_IER_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0                 _MK_ADDR_CONST(0x20c8)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0                     _MK_ADDR_CONST(0x20cc)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0                     _MK_ADDR_CONST(0x20d0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0                   _MK_ADDR_CONST(0x20d4)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0                 _MK_ADDR_CONST(0x20d8)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0                 _MK_ADDR_CONST(0x20dc)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0                     _MK_ADDR_CONST(0x20e0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0                     _MK_ADDR_CONST(0x20e4)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0                        _MK_ADDR_CONST(0x2100)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0                        _MK_ADDR_CONST(0x2104)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE4_IER_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0                 _MK_ADDR_CONST(0x2108)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0                     _MK_ADDR_CONST(0x210c)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0                     _MK_ADDR_CONST(0x2110)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0                   _MK_ADDR_CONST(0x2114)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0                 _MK_ADDR_CONST(0x2118)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0                 _MK_ADDR_CONST(0x211c)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0                     _MK_ADDR_CONST(0x2120)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0                     _MK_ADDR_CONST(0x2124)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0                        _MK_ADDR_CONST(0x2140)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0                        _MK_ADDR_CONST(0x2144)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE5_IER_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0                 _MK_ADDR_CONST(0x2148)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0                     _MK_ADDR_CONST(0x214c)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0                     _MK_ADDR_CONST(0x2150)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0                   _MK_ADDR_CONST(0x2154)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0                 _MK_ADDR_CONST(0x2158)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0                 _MK_ADDR_CONST(0x215c)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0                     _MK_ADDR_CONST(0x2160)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0                     _MK_ADDR_CONST(0x2164)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0                        _MK_ADDR_CONST(0x2180)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0                        _MK_ADDR_CONST(0x2184)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE6_IER_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0                 _MK_ADDR_CONST(0x2188)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0                     _MK_ADDR_CONST(0x218c)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0                     _MK_ADDR_CONST(0x2190)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0                   _MK_ADDR_CONST(0x2194)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0                 _MK_ADDR_CONST(0x2198)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0                 _MK_ADDR_CONST(0x219c)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0                     _MK_ADDR_CONST(0x21a0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0                     _MK_ADDR_CONST(0x21a4)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0                        _MK_ADDR_CONST(0x21c0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0                        _MK_ADDR_CONST(0x21c4)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE7_IER_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0                 _MK_ADDR_CONST(0x21c8)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0                     _MK_ADDR_CONST(0x21cc)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0                     _MK_ADDR_CONST(0x21d0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0                   _MK_ADDR_CONST(0x21d4)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0                 _MK_ADDR_CONST(0x21d8)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0                 _MK_ADDR_CONST(0x21dc)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0                     _MK_ADDR_CONST(0x21e0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0                     _MK_ADDR_CONST(0x21e4)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0                        _MK_ADDR_CONST(0x2200)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0                        _MK_ADDR_CONST(0x2204)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE8_IER_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0                 _MK_ADDR_CONST(0x2208)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0                     _MK_ADDR_CONST(0x220c)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0                     _MK_ADDR_CONST(0x2210)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0                   _MK_ADDR_CONST(0x2214)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0                 _MK_ADDR_CONST(0x2218)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0                 _MK_ADDR_CONST(0x221c)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0                     _MK_ADDR_CONST(0x2220)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0                     _MK_ADDR_CONST(0x2224)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0                  _MK_ADDR_CONST(0x27c0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0                  _MK_ADDR_CONST(0x27c4)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0                        _MK_ADDR_CONST(0x2800)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0                        _MK_ADDR_CONST(0x2804)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE0_IER_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0                 _MK_ADDR_CONST(0x2808)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0                     _MK_ADDR_CONST(0x280c)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0                     _MK_ADDR_CONST(0x2810)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0                   _MK_ADDR_CONST(0x2814)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0                 _MK_ADDR_CONST(0x2818)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0                 _MK_ADDR_CONST(0x281c)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0                     _MK_ADDR_CONST(0x2820)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0                     _MK_ADDR_CONST(0x2824)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0                        _MK_ADDR_CONST(0x2840)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0                        _MK_ADDR_CONST(0x2844)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE1_IER_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0                 _MK_ADDR_CONST(0x2848)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0                     _MK_ADDR_CONST(0x284c)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0                     _MK_ADDR_CONST(0x2850)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0                   _MK_ADDR_CONST(0x2854)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0                 _MK_ADDR_CONST(0x2858)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0                 _MK_ADDR_CONST(0x285c)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0                     _MK_ADDR_CONST(0x2860)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0                     _MK_ADDR_CONST(0x2864)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0                        _MK_ADDR_CONST(0x2880)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0                        _MK_ADDR_CONST(0x2884)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE2_IER_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0                 _MK_ADDR_CONST(0x2888)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0                     _MK_ADDR_CONST(0x288c)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0                     _MK_ADDR_CONST(0x2890)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0                   _MK_ADDR_CONST(0x2894)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0                 _MK_ADDR_CONST(0x2898)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0                 _MK_ADDR_CONST(0x289c)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0                     _MK_ADDR_CONST(0x28a0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0                     _MK_ADDR_CONST(0x28a4)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0                        _MK_ADDR_CONST(0x28c0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0                        _MK_ADDR_CONST(0x28c4)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE3_IER_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0                 _MK_ADDR_CONST(0x28c8)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0                     _MK_ADDR_CONST(0x28cc)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0                     _MK_ADDR_CONST(0x28d0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0                   _MK_ADDR_CONST(0x28d4)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0                 _MK_ADDR_CONST(0x28d8)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0                 _MK_ADDR_CONST(0x28dc)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0                     _MK_ADDR_CONST(0x28e0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0                     _MK_ADDR_CONST(0x28e4)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0                        _MK_ADDR_CONST(0x2900)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0                        _MK_ADDR_CONST(0x2904)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE4_IER_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0                 _MK_ADDR_CONST(0x2908)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0                     _MK_ADDR_CONST(0x290c)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0                     _MK_ADDR_CONST(0x2910)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0                   _MK_ADDR_CONST(0x2914)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0                 _MK_ADDR_CONST(0x2918)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0                 _MK_ADDR_CONST(0x291c)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0                     _MK_ADDR_CONST(0x2920)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0                     _MK_ADDR_CONST(0x2924)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0                        _MK_ADDR_CONST(0x2940)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0                        _MK_ADDR_CONST(0x2944)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE5_IER_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0                 _MK_ADDR_CONST(0x2948)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0                     _MK_ADDR_CONST(0x294c)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0                     _MK_ADDR_CONST(0x2950)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0                   _MK_ADDR_CONST(0x2954)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0                 _MK_ADDR_CONST(0x2958)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0                 _MK_ADDR_CONST(0x295c)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0                     _MK_ADDR_CONST(0x2960)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0                     _MK_ADDR_CONST(0x2964)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0                        _MK_ADDR_CONST(0x2980)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0                        _MK_ADDR_CONST(0x2984)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE6_IER_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0                 _MK_ADDR_CONST(0x2988)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0                     _MK_ADDR_CONST(0x298c)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0                     _MK_ADDR_CONST(0x2990)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0                   _MK_ADDR_CONST(0x2994)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0                 _MK_ADDR_CONST(0x2998)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0                 _MK_ADDR_CONST(0x299c)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0                     _MK_ADDR_CONST(0x29a0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0                     _MK_ADDR_CONST(0x29a4)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0                        _MK_ADDR_CONST(0x29c0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0                        _MK_ADDR_CONST(0x29c4)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE7_IER_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0                 _MK_ADDR_CONST(0x29c8)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0                     _MK_ADDR_CONST(0x29cc)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0                     _MK_ADDR_CONST(0x29d0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0                   _MK_ADDR_CONST(0x29d4)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0                 _MK_ADDR_CONST(0x29d8)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0                 _MK_ADDR_CONST(0x29dc)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0                     _MK_ADDR_CONST(0x29e0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0                     _MK_ADDR_CONST(0x29e4)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0                        _MK_ADDR_CONST(0x2a00)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0                        _MK_ADDR_CONST(0x2a04)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_FIELD                     _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE8_IER_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0                 _MK_ADDR_CONST(0x2a08)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0                     _MK_ADDR_CONST(0x2a0c)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0                     _MK_ADDR_CONST(0x2a10)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0                   _MK_ADDR_CONST(0x2a14)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0                 _MK_ADDR_CONST(0x2a18)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0                 _MK_ADDR_CONST(0x2a1c)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0                     _MK_ADDR_CONST(0x2a20)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0                     _MK_ADDR_CONST(0x2a24)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0                  _MK_ADDR_CONST(0x2fc0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0                  _MK_ADDR_CONST(0x2fc4)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SHIFT                    _MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SHIFT                    _MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SHIFT                    _MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_FIELD                    _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SHIFT                  _MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_FIELD                  _MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SHIFT                        _MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SHIFT                        _MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SHIFT                        _MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SHIFT                        _MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SHIFT                        _MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SHIFT                        _MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SHIFT                        _MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SHIFT                        _MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SHIFT                        _MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SHIFT                        _MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SHIFT                        _MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SHIFT                        _MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SHIFT                        _MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SHIFT                        _MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SHIFT                        _MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SHIFT                        _MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SHIFT                        _MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SHIFT                        _MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SHIFT                        _MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SHIFT                        _MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SHIFT                        _MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SHIFT                        _MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SHIFT                        _MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SHIFT                        _MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_FIELD                        _MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_DEFAULT                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE0_GISR_0
#define INTR_CTLR_COMMON_SLICE0_GISR_0                  _MK_ADDR_CONST(0xf800)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE0_GISR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE0_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE0_GISR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE0_FIR_0
#define INTR_CTLR_COMMON_SLICE0_FIR_0                   _MK_ADDR_CONST(0xf804)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_0_SCR                       0
#define INTR_CTLR_COMMON_SLICE0_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE0_FIR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE0_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0                       _MK_ADDR_CONST(0xf808)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE0_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0                       _MK_ADDR_CONST(0xf80c)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE0_CIDR_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0                  _MK_ADDR_CONST(0xf810)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE0_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0                      _MK_ADDR_CONST(0xf814)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0                      _MK_ADDR_CONST(0xf818)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE1_GISR_0
#define INTR_CTLR_COMMON_SLICE1_GISR_0                  _MK_ADDR_CONST(0xf840)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE1_GISR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE1_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE1_GISR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE1_FIR_0
#define INTR_CTLR_COMMON_SLICE1_FIR_0                   _MK_ADDR_CONST(0xf844)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_0_SCR                       0
#define INTR_CTLR_COMMON_SLICE1_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE1_FIR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE1_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0                       _MK_ADDR_CONST(0xf848)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE1_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0                       _MK_ADDR_CONST(0xf84c)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE1_CIDR_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0                  _MK_ADDR_CONST(0xf850)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE1_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0                      _MK_ADDR_CONST(0xf854)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0                      _MK_ADDR_CONST(0xf858)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE2_GISR_0
#define INTR_CTLR_COMMON_SLICE2_GISR_0                  _MK_ADDR_CONST(0xf880)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE2_GISR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE2_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE2_GISR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE2_FIR_0
#define INTR_CTLR_COMMON_SLICE2_FIR_0                   _MK_ADDR_CONST(0xf884)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_0_SCR                       0
#define INTR_CTLR_COMMON_SLICE2_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE2_FIR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE2_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0                       _MK_ADDR_CONST(0xf888)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE2_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0                       _MK_ADDR_CONST(0xf88c)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE2_CIDR_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0                  _MK_ADDR_CONST(0xf890)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE2_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0                      _MK_ADDR_CONST(0xf894)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0                      _MK_ADDR_CONST(0xf898)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE3_GISR_0
#define INTR_CTLR_COMMON_SLICE3_GISR_0                  _MK_ADDR_CONST(0xf8c0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE3_GISR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE3_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE3_GISR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE3_FIR_0
#define INTR_CTLR_COMMON_SLICE3_FIR_0                   _MK_ADDR_CONST(0xf8c4)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_0_SCR                       0
#define INTR_CTLR_COMMON_SLICE3_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE3_FIR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE3_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0                       _MK_ADDR_CONST(0xf8c8)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE3_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0                       _MK_ADDR_CONST(0xf8cc)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE3_CIDR_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0                  _MK_ADDR_CONST(0xf8d0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE3_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0                      _MK_ADDR_CONST(0xf8d4)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0                      _MK_ADDR_CONST(0xf8d8)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE4_GISR_0
#define INTR_CTLR_COMMON_SLICE4_GISR_0                  _MK_ADDR_CONST(0xf900)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE4_GISR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE4_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE4_GISR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE4_FIR_0
#define INTR_CTLR_COMMON_SLICE4_FIR_0                   _MK_ADDR_CONST(0xf904)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_0_SCR                       0
#define INTR_CTLR_COMMON_SLICE4_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE4_FIR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE4_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0                       _MK_ADDR_CONST(0xf908)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE4_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0                       _MK_ADDR_CONST(0xf90c)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE4_CIDR_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0                  _MK_ADDR_CONST(0xf910)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE4_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0                      _MK_ADDR_CONST(0xf914)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0                      _MK_ADDR_CONST(0xf918)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE5_GISR_0
#define INTR_CTLR_COMMON_SLICE5_GISR_0                  _MK_ADDR_CONST(0xf940)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE5_GISR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE5_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE5_GISR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE5_FIR_0
#define INTR_CTLR_COMMON_SLICE5_FIR_0                   _MK_ADDR_CONST(0xf944)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_0_SCR                       0
#define INTR_CTLR_COMMON_SLICE5_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE5_FIR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE5_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0                       _MK_ADDR_CONST(0xf948)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE5_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0                       _MK_ADDR_CONST(0xf94c)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE5_CIDR_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0                  _MK_ADDR_CONST(0xf950)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE5_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0                      _MK_ADDR_CONST(0xf954)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0                      _MK_ADDR_CONST(0xf958)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE6_GISR_0
#define INTR_CTLR_COMMON_SLICE6_GISR_0                  _MK_ADDR_CONST(0xf980)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE6_GISR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE6_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE6_GISR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE6_FIR_0
#define INTR_CTLR_COMMON_SLICE6_FIR_0                   _MK_ADDR_CONST(0xf984)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_0_SCR                       0
#define INTR_CTLR_COMMON_SLICE6_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE6_FIR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE6_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0                       _MK_ADDR_CONST(0xf988)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE6_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0                       _MK_ADDR_CONST(0xf98c)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE6_CIDR_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0                  _MK_ADDR_CONST(0xf990)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE6_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0                      _MK_ADDR_CONST(0xf994)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0                      _MK_ADDR_CONST(0xf998)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE7_GISR_0
#define INTR_CTLR_COMMON_SLICE7_GISR_0                  _MK_ADDR_CONST(0xf9c0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE7_GISR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE7_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE7_GISR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE7_FIR_0
#define INTR_CTLR_COMMON_SLICE7_FIR_0                   _MK_ADDR_CONST(0xf9c4)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_0_SCR                       0
#define INTR_CTLR_COMMON_SLICE7_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE7_FIR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE7_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0                       _MK_ADDR_CONST(0xf9c8)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE7_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0                       _MK_ADDR_CONST(0xf9cc)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE7_CIDR_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0                  _MK_ADDR_CONST(0xf9d0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE7_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0                      _MK_ADDR_CONST(0xf9d4)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0                      _MK_ADDR_CONST(0xf9d8)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE8_GISR_0
#define INTR_CTLR_COMMON_SLICE8_GISR_0                  _MK_ADDR_CONST(0xfa00)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE8_GISR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE8_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE8_GISR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE8_FIR_0
#define INTR_CTLR_COMMON_SLICE8_FIR_0                   _MK_ADDR_CONST(0xfa04)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_0_SCR                       0
#define INTR_CTLR_COMMON_SLICE8_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE8_FIR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE8_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0                       _MK_ADDR_CONST(0xfa08)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE8_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0                       _MK_ADDR_CONST(0xfa0c)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SCR                   0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SHIFT                 _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_FIELD                 _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE8_CIDR_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0                  _MK_ADDR_CONST(0xfa10)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SCR                      0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE8_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0                      _MK_ADDR_CONST(0xfa14)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0                      _MK_ADDR_CONST(0xfa18)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SCR                  0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_FIELD                       _MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 64064 [0xfa40]

// Reserved address 64068 [0xfa44]

// Reserved address 64072 [0xfa48]

// Reserved address 64076 [0xfa4c]

// Reserved address 64080 [0xfa50]

// Reserved address 64084 [0xfa54]

// Reserved address 64088 [0xfa58]

// Reserved address 64092 [0xfa5c]

// Reserved address 64096 [0xfa60]

// Reserved address 64100 [0xfa64]

// Reserved address 64104 [0xfa68]

// Reserved address 64108 [0xfa6c]

// Reserved address 64112 [0xfa70]

// Reserved address 64116 [0xfa74]

// Reserved address 64120 [0xfa78]

// Reserved address 64124 [0xfa7c]

// Reserved address 64128 [0xfa80]

// Reserved address 64132 [0xfa84]

// Reserved address 64136 [0xfa88]

// Reserved address 64140 [0xfa8c]

// Reserved address 64144 [0xfa90]

// Reserved address 64148 [0xfa94]

// Reserved address 64152 [0xfa98]

// Reserved address 64156 [0xfa9c]

// Reserved address 64160 [0xfaa0]

// Reserved address 64164 [0xfaa4]

// Reserved address 64168 [0xfaa8]

// Reserved address 64172 [0xfaac]

// Reserved address 64176 [0xfab0]

// Reserved address 64180 [0xfab4]

// Reserved address 64184 [0xfab8]

// Reserved address 64188 [0xfabc]

// Reserved address 64192 [0xfac0]

// Reserved address 64196 [0xfac4]

// Reserved address 64200 [0xfac8]

// Reserved address 64204 [0xfacc]

// Reserved address 64208 [0xfad0]

// Reserved address 64212 [0xfad4]

// Reserved address 64216 [0xfad8]

// Reserved address 64220 [0xfadc]

// Reserved address 64224 [0xfae0]

// Reserved address 64228 [0xfae4]

// Reserved address 64232 [0xfae8]

// Reserved address 64236 [0xfaec]

// Reserved address 64240 [0xfaf0]

// Reserved address 64244 [0xfaf4]

// Reserved address 64248 [0xfaf8]

// Reserved address 64252 [0xfafc]

// Reserved address 64256 [0xfb00]

// Reserved address 64260 [0xfb04]

// Reserved address 64264 [0xfb08]

// Reserved address 64268 [0xfb0c]

// Reserved address 64272 [0xfb10]

// Reserved address 64276 [0xfb14]

// Reserved address 64280 [0xfb18]

// Reserved address 64284 [0xfb1c]

// Reserved address 64288 [0xfb20]

// Reserved address 64292 [0xfb24]

// Reserved address 64296 [0xfb28]

// Reserved address 64300 [0xfb2c]

// Reserved address 64304 [0xfb30]

// Reserved address 64308 [0xfb34]

// Reserved address 64312 [0xfb38]

// Reserved address 64316 [0xfb3c]

// Reserved address 64320 [0xfb40]

// Reserved address 64324 [0xfb44]

// Reserved address 64328 [0xfb48]

// Reserved address 64332 [0xfb4c]

// Reserved address 64336 [0xfb50]

// Reserved address 64340 [0xfb54]

// Reserved address 64344 [0xfb58]

// Reserved address 64348 [0xfb5c]

// Reserved address 64352 [0xfb60]

// Reserved address 64356 [0xfb64]

// Reserved address 64360 [0xfb68]

// Reserved address 64364 [0xfb6c]

// Reserved address 64368 [0xfb70]

// Reserved address 64372 [0xfb74]

// Reserved address 64376 [0xfb78]

// Reserved address 64380 [0xfb7c]

// Reserved address 64384 [0xfb80]

// Reserved address 64388 [0xfb84]

// Reserved address 64392 [0xfb88]

// Reserved address 64396 [0xfb8c]

// Reserved address 64400 [0xfb90]

// Reserved address 64404 [0xfb94]

// Reserved address 64408 [0xfb98]

// Reserved address 64412 [0xfb9c]

// Reserved address 64416 [0xfba0]

// Reserved address 64420 [0xfba4]

// Reserved address 64424 [0xfba8]

// Reserved address 64428 [0xfbac]

// Reserved address 64432 [0xfbb0]

// Reserved address 64436 [0xfbb4]

// Reserved address 64440 [0xfbb8]

// Reserved address 64444 [0xfbbc]

// Reserved address 64448 [0xfbc0]

// Reserved address 64452 [0xfbc4]

// Reserved address 64456 [0xfbc8]

// Reserved address 64460 [0xfbcc]

// Reserved address 64464 [0xfbd0]

// Reserved address 64468 [0xfbd4]

// Reserved address 64472 [0xfbd8]

// Reserved address 64476 [0xfbdc]

// Reserved address 64480 [0xfbe0]

// Reserved address 64484 [0xfbe4]

// Reserved address 64488 [0xfbe8]

// Reserved address 64492 [0xfbec]

// Reserved address 64496 [0xfbf0]

// Reserved address 64500 [0xfbf4]

// Reserved address 64504 [0xfbf8]

// Reserved address 64508 [0xfbfc]

// Reserved address 64512 [0xfc00]

// Reserved address 64516 [0xfc04]

// Reserved address 64520 [0xfc08]

// Reserved address 64524 [0xfc0c]

// Reserved address 64528 [0xfc10]

// Reserved address 64532 [0xfc14]

// Reserved address 64536 [0xfc18]

// Reserved address 64540 [0xfc1c]

// Reserved address 64544 [0xfc20]

// Reserved address 64548 [0xfc24]

// Reserved address 64552 [0xfc28]

// Reserved address 64556 [0xfc2c]

// Reserved address 64560 [0xfc30]

// Reserved address 64564 [0xfc34]

// Reserved address 64568 [0xfc38]

// Reserved address 64572 [0xfc3c]

// Reserved address 64576 [0xfc40]

// Reserved address 64580 [0xfc44]

// Reserved address 64584 [0xfc48]

// Reserved address 64588 [0xfc4c]

// Reserved address 64592 [0xfc50]

// Reserved address 64596 [0xfc54]

// Reserved address 64600 [0xfc58]

// Reserved address 64604 [0xfc5c]

// Reserved address 64608 [0xfc60]

// Reserved address 64612 [0xfc64]

// Reserved address 64616 [0xfc68]

// Reserved address 64620 [0xfc6c]

// Reserved address 64624 [0xfc70]

// Reserved address 64628 [0xfc74]

// Reserved address 64632 [0xfc78]

// Reserved address 64636 [0xfc7c]

// Reserved address 64640 [0xfc80]

// Reserved address 64644 [0xfc84]

// Reserved address 64648 [0xfc88]

// Reserved address 64652 [0xfc8c]

// Reserved address 64656 [0xfc90]

// Reserved address 64660 [0xfc94]

// Reserved address 64664 [0xfc98]

// Reserved address 64668 [0xfc9c]

// Reserved address 64672 [0xfca0]

// Reserved address 64676 [0xfca4]

// Reserved address 64680 [0xfca8]

// Reserved address 64684 [0xfcac]

// Reserved address 64688 [0xfcb0]

// Reserved address 64692 [0xfcb4]

// Reserved address 64696 [0xfcb8]

// Reserved address 64700 [0xfcbc]

// Reserved address 64704 [0xfcc0]

// Reserved address 64708 [0xfcc4]

// Reserved address 64712 [0xfcc8]

// Reserved address 64716 [0xfccc]

// Reserved address 64720 [0xfcd0]

// Reserved address 64724 [0xfcd4]

// Reserved address 64728 [0xfcd8]

// Reserved address 64732 [0xfcdc]

// Reserved address 64736 [0xfce0]

// Reserved address 64740 [0xfce4]

// Reserved address 64744 [0xfce8]

// Reserved address 64748 [0xfcec]

// Reserved address 64752 [0xfcf0]

// Reserved address 64756 [0xfcf4]

// Reserved address 64760 [0xfcf8]

// Reserved address 64764 [0xfcfc]

// Reserved address 64768 [0xfd00]

// Reserved address 64772 [0xfd04]

// Reserved address 64776 [0xfd08]

// Reserved address 64780 [0xfd0c]

// Reserved address 64784 [0xfd10]

// Reserved address 64788 [0xfd14]

// Reserved address 64792 [0xfd18]

// Reserved address 64796 [0xfd1c]

// Reserved address 64800 [0xfd20]

// Reserved address 64804 [0xfd24]

// Reserved address 64808 [0xfd28]

// Reserved address 64812 [0xfd2c]

// Reserved address 64816 [0xfd30]

// Reserved address 64820 [0xfd34]

// Reserved address 64824 [0xfd38]

// Reserved address 64828 [0xfd3c]

// Reserved address 64832 [0xfd40]

// Reserved address 64836 [0xfd44]

// Reserved address 64840 [0xfd48]

// Reserved address 64844 [0xfd4c]

// Reserved address 64848 [0xfd50]

// Reserved address 64852 [0xfd54]

// Reserved address 64856 [0xfd58]

// Reserved address 64860 [0xfd5c]

// Reserved address 64864 [0xfd60]

// Reserved address 64868 [0xfd64]

// Reserved address 64872 [0xfd68]

// Reserved address 64876 [0xfd6c]

// Reserved address 64880 [0xfd70]

// Reserved address 64884 [0xfd74]

// Reserved address 64888 [0xfd78]

// Reserved address 64892 [0xfd7c]

// Reserved address 64896 [0xfd80]

// Reserved address 64900 [0xfd84]

// Reserved address 64904 [0xfd88]

// Reserved address 64908 [0xfd8c]

// Reserved address 64912 [0xfd90]

// Reserved address 64916 [0xfd94]

// Reserved address 64920 [0xfd98]

// Reserved address 64924 [0xfd9c]

// Reserved address 64928 [0xfda0]

// Reserved address 64932 [0xfda4]

// Reserved address 64936 [0xfda8]

// Reserved address 64940 [0xfdac]

// Reserved address 64944 [0xfdb0]

// Reserved address 64948 [0xfdb4]

// Reserved address 64952 [0xfdb8]

// Reserved address 64956 [0xfdbc]

// Reserved address 64960 [0xfdc0]

// Reserved address 64964 [0xfdc4]

// Reserved address 64968 [0xfdc8]

// Reserved address 64972 [0xfdcc]

// Reserved address 64976 [0xfdd0]

// Reserved address 64980 [0xfdd4]

// Reserved address 64984 [0xfdd8]

// Reserved address 64988 [0xfddc]

// Reserved address 64992 [0xfde0]

// Reserved address 64996 [0xfde4]

// Reserved address 65000 [0xfde8]

// Reserved address 65004 [0xfdec]

// Reserved address 65008 [0xfdf0]

// Reserved address 65012 [0xfdf4]

// Reserved address 65016 [0xfdf8]

// Reserved address 65020 [0xfdfc]

// Reserved address 65024 [0xfe00]

// Reserved address 65028 [0xfe04]

// Reserved address 65032 [0xfe08]

// Reserved address 65036 [0xfe0c]

// Reserved address 65040 [0xfe10]

// Reserved address 65044 [0xfe14]

// Reserved address 65048 [0xfe18]

// Reserved address 65052 [0xfe1c]

// Reserved address 65056 [0xfe20]

// Reserved address 65060 [0xfe24]

// Reserved address 65064 [0xfe28]

// Reserved address 65068 [0xfe2c]

// Reserved address 65072 [0xfe30]

// Reserved address 65076 [0xfe34]

// Reserved address 65080 [0xfe38]

// Reserved address 65084 [0xfe3c]

// Reserved address 65088 [0xfe40]

// Reserved address 65092 [0xfe44]

// Reserved address 65096 [0xfe48]

// Reserved address 65100 [0xfe4c]

// Reserved address 65104 [0xfe50]

// Reserved address 65108 [0xfe54]

// Reserved address 65112 [0xfe58]

// Reserved address 65116 [0xfe5c]

// Reserved address 65120 [0xfe60]

// Reserved address 65124 [0xfe64]

// Reserved address 65128 [0xfe68]

// Reserved address 65132 [0xfe6c]

// Reserved address 65136 [0xfe70]

// Reserved address 65140 [0xfe74]

// Reserved address 65144 [0xfe78]

// Reserved address 65148 [0xfe7c]

// Reserved address 65152 [0xfe80]

// Reserved address 65156 [0xfe84]

// Reserved address 65160 [0xfe88]

// Reserved address 65164 [0xfe8c]

// Reserved address 65168 [0xfe90]

// Reserved address 65172 [0xfe94]

// Reserved address 65176 [0xfe98]

// Reserved address 65180 [0xfe9c]

// Reserved address 65184 [0xfea0]

// Reserved address 65188 [0xfea4]

// Reserved address 65192 [0xfea8]

// Reserved address 65196 [0xfeac]

// Reserved address 65200 [0xfeb0]

// Reserved address 65204 [0xfeb4]

// Reserved address 65208 [0xfeb8]

// Reserved address 65212 [0xfebc]

// Reserved address 65216 [0xfec0]

// Reserved address 65220 [0xfec4]

// Reserved address 65224 [0xfec8]

// Reserved address 65228 [0xfecc]

// Reserved address 65232 [0xfed0]

// Reserved address 65236 [0xfed4]

// Reserved address 65240 [0xfed8]

// Reserved address 65244 [0xfedc]

// Reserved address 65248 [0xfee0]

// Reserved address 65252 [0xfee4]

// Reserved address 65256 [0xfee8]

// Reserved address 65260 [0xfeec]

// Reserved address 65264 [0xfef0]

// Reserved address 65268 [0xfef4]

// Reserved address 65272 [0xfef8]

// Reserved address 65276 [0xfefc]

// Reserved address 65280 [0xff00]

// Reserved address 65284 [0xff04]

// Reserved address 65288 [0xff08]

// Reserved address 65292 [0xff0c]

// Reserved address 65296 [0xff10]

// Reserved address 65300 [0xff14]

// Reserved address 65304 [0xff18]

// Reserved address 65308 [0xff1c]

// Reserved address 65312 [0xff20]

// Reserved address 65316 [0xff24]

// Reserved address 65320 [0xff28]

// Reserved address 65324 [0xff2c]

// Reserved address 65328 [0xff30]

// Reserved address 65332 [0xff34]

// Reserved address 65336 [0xff38]

// Reserved address 65340 [0xff3c]

// Reserved address 65344 [0xff40]

// Reserved address 65348 [0xff44]

// Reserved address 65352 [0xff48]

// Reserved address 65356 [0xff4c]

// Reserved address 65360 [0xff50]

// Reserved address 65364 [0xff54]

// Reserved address 65368 [0xff58]

// Reserved address 65372 [0xff5c]

// Reserved address 65376 [0xff60]

// Reserved address 65380 [0xff64]

// Reserved address 65384 [0xff68]

// Reserved address 65388 [0xff6c]

// Reserved address 65392 [0xff70]

// Reserved address 65396 [0xff74]

// Reserved address 65400 [0xff78]

// Reserved address 65404 [0xff7c]

// Reserved address 65408 [0xff80]

// Reserved address 65412 [0xff84]

// Reserved address 65416 [0xff88]

// Reserved address 65420 [0xff8c]

// Reserved address 65424 [0xff90]

// Reserved address 65428 [0xff94]

// Reserved address 65432 [0xff98]

// Reserved address 65436 [0xff9c]

// Reserved address 65440 [0xffa0]

// Reserved address 65444 [0xffa4]

// Reserved address 65448 [0xffa8]

// Reserved address 65452 [0xffac]

// Reserved address 65456 [0xffb0]

// Reserved address 65460 [0xffb4]

// Reserved address 65464 [0xffb8]

// Reserved address 65468 [0xffbc]

// Register INTR_CTLR_COMMON_CTRL_0
#define INTR_CTLR_COMMON_CTRL_0                 _MK_ADDR_CONST(0xffc0)
#define INTR_CTLR_COMMON_CTRL_0_SECURE                  0x0
#define INTR_CTLR_COMMON_CTRL_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_CTRL_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_CTRL_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_CTRL_0_ENABLE_TIMESTAMPING_SHIFT                       _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_CTRL_0_ENABLE_TIMESTAMPING_FIELD                       _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_CTRL_0_ENABLE_TIMESTAMPING_SHIFT)
#define INTR_CTLR_COMMON_CTRL_0_ENABLE_TIMESTAMPING_RANGE                       0:0
#define INTR_CTLR_COMMON_CTRL_0_ENABLE_TIMESTAMPING_WOFFSET                     0x0
#define INTR_CTLR_COMMON_CTRL_0_ENABLE_TIMESTAMPING_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_CTRL_0_ENABLE_TIMESTAMPING_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_CTRL_0_ENABLE_TIMESTAMPING_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_CTRL_0_ENABLE_TIMESTAMPING_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0                       _MK_ADDR_CONST(0xffc4)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SCR                   0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SHIFT                 _MK_SHIFT_CONST(29)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_FIELD                 _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_RANGE                 29:29
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SHIFT                 _MK_SHIFT_CONST(28)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_FIELD                 _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_RANGE                 28:28
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SHIFT                 _MK_SHIFT_CONST(27)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_FIELD                 _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_RANGE                 27:27
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_DEFAULT                       _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SHIFT                       _MK_SHIFT_CONST(24)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_FIELD                       _MK_FIELD_CONST(0x7, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_RANGE                       26:24
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_DEFAULT                     _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SHIFT                     _MK_SHIFT_CONST(23)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_RANGE                     23:23
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SHIFT                     _MK_SHIFT_CONST(22)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_RANGE                     22:22
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SHIFT                     _MK_SHIFT_CONST(21)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_RANGE                     21:21
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SHIFT                     _MK_SHIFT_CONST(20)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_RANGE                     20:20
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SHIFT                     _MK_SHIFT_CONST(19)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_RANGE                     19:19
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SHIFT                     _MK_SHIFT_CONST(18)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_RANGE                     18:18
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SHIFT                     _MK_SHIFT_CONST(17)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_RANGE                     17:17
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SHIFT                     _MK_SHIFT_CONST(16)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_RANGE                     16:16
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SHIFT                     _MK_SHIFT_CONST(15)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_RANGE                     15:15
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SHIFT                     _MK_SHIFT_CONST(14)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_RANGE                     14:14
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SHIFT                     _MK_SHIFT_CONST(13)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_RANGE                     13:13
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SHIFT                     _MK_SHIFT_CONST(12)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_RANGE                     12:12
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SHIFT                     _MK_SHIFT_CONST(11)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_RANGE                     11:11
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SHIFT                     _MK_SHIFT_CONST(10)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_RANGE                     10:10
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SHIFT                     _MK_SHIFT_CONST(9)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_RANGE                     9:9
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SHIFT                     _MK_SHIFT_CONST(8)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_RANGE                     8:8
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SHIFT                     _MK_SHIFT_CONST(7)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_RANGE                     7:7
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SHIFT                     _MK_SHIFT_CONST(6)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_RANGE                     6:6
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SHIFT                     _MK_SHIFT_CONST(5)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_RANGE                     5:5
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SHIFT                     _MK_SHIFT_CONST(4)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_RANGE                     4:4
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SHIFT                     _MK_SHIFT_CONST(3)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_RANGE                     3:3
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SHIFT                     _MK_SHIFT_CONST(2)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_RANGE                     2:2
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SHIFT                     _MK_SHIFT_CONST(1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_RANGE                     1:1
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SHIFT                     _MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_FIELD                     _MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_RANGE                     0:0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_DEFAULT                   _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Packet SLICE0_ICTLR_FIELDS_0
#define SLICE0_ICTLR_FIELDS_0_SIZE 32

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_SHIFT                    _MK_SHIFT_CONST(0)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_FIELD                    _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_SHIFT                    _MK_SHIFT_CONST(1)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_FIELD                    _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_SHIFT                    _MK_SHIFT_CONST(2)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_FIELD                    _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_SHIFT                    _MK_SHIFT_CONST(3)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_FIELD                    _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_RANGE                    _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_SHIFT                    _MK_SHIFT_CONST(4)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_FIELD                    _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_SHIFT                    _MK_SHIFT_CONST(5)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_FIELD                    _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_RANGE                    _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_SHIFT                    _MK_SHIFT_CONST(6)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_FIELD                    _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_SHIFT                    _MK_SHIFT_CONST(7)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_FIELD                    _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_RANGE                    _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_SHIFT                    _MK_SHIFT_CONST(8)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_FIELD                    _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_RANGE                    _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_SHIFT                    _MK_SHIFT_CONST(9)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_FIELD                    _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_RANGE                    _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_RTC_SHIFT                 _MK_SHIFT_CONST(10)
#define SLICE0_ICTLR_FIELDS_0_RTC_FIELD                 _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_RTC_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_RTC_RANGE                 _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
#define SLICE0_ICTLR_FIELDS_0_RTC_ROW                   0

#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_SHIFT                   _MK_SHIFT_CONST(11)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_FIELD                   _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_RANGE                   _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_ROW                     0

#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_SHIFT                   _MK_SHIFT_CONST(12)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_FIELD                   _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_RANGE                   _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_ROW                     0

#define SLICE0_ICTLR_FIELDS_0_AON_GTE_SHIFT                     _MK_SHIFT_CONST(13)
#define SLICE0_ICTLR_FIELDS_0_AON_GTE_FIELD                     _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_AON_GTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_AON_GTE_RANGE                     _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13)
#define SLICE0_ICTLR_FIELDS_0_AON_GTE_ROW                       0

#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_SHIFT                     _MK_SHIFT_CONST(14)
#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_FIELD                     _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_ROW                       0

#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_SHIFT                      _MK_SHIFT_CONST(15)
#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_FIELD                      _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_RANGE                      _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_ROW                        0

#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_SHIFT                      _MK_SHIFT_CONST(16)
#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_FIELD                      _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_RANGE                      _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_ROW                        0

#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_SHIFT                      _MK_SHIFT_CONST(17)
#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_FIELD                      _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_RANGE                      _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_ROW                        0

#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_SHIFT                        _MK_SHIFT_CONST(18)
#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_FIELD                        _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_RANGE                        _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_RESERVED_19_SHIFT                 _MK_SHIFT_CONST(19)
#define SLICE0_ICTLR_FIELDS_0_RESERVED_19_FIELD                 _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_RESERVED_19_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_RESERVED_19_RANGE                 _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
#define SLICE0_ICTLR_FIELDS_0_RESERVED_19_ROW                   0

#define SLICE0_ICTLR_FIELDS_0_DSIA_SHIFT                        _MK_SHIFT_CONST(20)
#define SLICE0_ICTLR_FIELDS_0_DSIA_FIELD                        _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_DSIA_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_DSIA_RANGE                        _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
#define SLICE0_ICTLR_FIELDS_0_DSIA_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_DSIB_SHIFT                        _MK_SHIFT_CONST(21)
#define SLICE0_ICTLR_FIELDS_0_DSIB_FIELD                        _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_DSIB_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_DSIB_RANGE                        _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
#define SLICE0_ICTLR_FIELDS_0_DSIB_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_DSIC_SHIFT                        _MK_SHIFT_CONST(22)
#define SLICE0_ICTLR_FIELDS_0_DSIC_FIELD                        _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_DSIC_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_DSIC_RANGE                        _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
#define SLICE0_ICTLR_FIELDS_0_DSIC_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_DSID_SHIFT                        _MK_SHIFT_CONST(23)
#define SLICE0_ICTLR_FIELDS_0_DSID_FIELD                        _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_DSID_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_DSID_RANGE                        _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
#define SLICE0_ICTLR_FIELDS_0_DSID_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_RESERVED_24_SHIFT                 _MK_SHIFT_CONST(24)
#define SLICE0_ICTLR_FIELDS_0_RESERVED_24_FIELD                 _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_RESERVED_24_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_RESERVED_24_RANGE                 _MK_SHIFT_CONST(24):_MK_SHIFT_CONST(24)
#define SLICE0_ICTLR_FIELDS_0_RESERVED_24_ROW                   0

#define SLICE0_ICTLR_FIELDS_0_I2C_SHIFT                 _MK_SHIFT_CONST(25)
#define SLICE0_ICTLR_FIELDS_0_I2C_FIELD                 _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C_RANGE                 _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(25)
#define SLICE0_ICTLR_FIELDS_0_I2C_ROW                   0

#define SLICE0_ICTLR_FIELDS_0_I2C2_SHIFT                        _MK_SHIFT_CONST(26)
#define SLICE0_ICTLR_FIELDS_0_I2C2_FIELD                        _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C2_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C2_RANGE                        _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
#define SLICE0_ICTLR_FIELDS_0_I2C2_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_I2C3_SHIFT                        _MK_SHIFT_CONST(27)
#define SLICE0_ICTLR_FIELDS_0_I2C3_FIELD                        _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C3_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C3_RANGE                        _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
#define SLICE0_ICTLR_FIELDS_0_I2C3_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_I2C4_SHIFT                        _MK_SHIFT_CONST(28)
#define SLICE0_ICTLR_FIELDS_0_I2C4_FIELD                        _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C4_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C4_RANGE                        _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
#define SLICE0_ICTLR_FIELDS_0_I2C4_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_I2C5_SHIFT                        _MK_SHIFT_CONST(29)
#define SLICE0_ICTLR_FIELDS_0_I2C5_FIELD                        _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C5_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C5_RANGE                        _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
#define SLICE0_ICTLR_FIELDS_0_I2C5_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_I2C6_SHIFT                        _MK_SHIFT_CONST(30)
#define SLICE0_ICTLR_FIELDS_0_I2C6_FIELD                        _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C6_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C6_RANGE                        _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
#define SLICE0_ICTLR_FIELDS_0_I2C6_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_I2C7_SHIFT                        _MK_SHIFT_CONST(31)
#define SLICE0_ICTLR_FIELDS_0_I2C7_FIELD                        _MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C7_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C7_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
#define SLICE0_ICTLR_FIELDS_0_I2C7_ROW                  0


// Packet SLICE1_ICTLR_FIELDS_0
#define SLICE1_ICTLR_FIELDS_0_SIZE 32

#define SLICE1_ICTLR_FIELDS_0_I2C8_SHIFT                        _MK_SHIFT_CONST(0)
#define SLICE1_ICTLR_FIELDS_0_I2C8_FIELD                        _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_I2C8_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_I2C8_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
#define SLICE1_ICTLR_FIELDS_0_I2C8_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_I2C9_SHIFT                        _MK_SHIFT_CONST(1)
#define SLICE1_ICTLR_FIELDS_0_I2C9_FIELD                        _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_I2C9_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_I2C9_RANGE                        _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
#define SLICE1_ICTLR_FIELDS_0_I2C9_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_I2C10_SHIFT                       _MK_SHIFT_CONST(2)
#define SLICE1_ICTLR_FIELDS_0_I2C10_FIELD                       _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_I2C10_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_I2C10_RANGE                       _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
#define SLICE1_ICTLR_FIELDS_0_I2C10_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_QSPI_SHIFT                        _MK_SHIFT_CONST(3)
#define SLICE1_ICTLR_FIELDS_0_QSPI_FIELD                        _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_QSPI_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_QSPI_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
#define SLICE1_ICTLR_FIELDS_0_QSPI_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_SPI1_SHIFT                        _MK_SHIFT_CONST(4)
#define SLICE1_ICTLR_FIELDS_0_SPI1_FIELD                        _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_SPI1_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
#define SLICE1_ICTLR_FIELDS_0_SPI1_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_SPI2_SHIFT                        _MK_SHIFT_CONST(5)
#define SLICE1_ICTLR_FIELDS_0_SPI2_FIELD                        _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI2_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_SPI2_RANGE                        _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
#define SLICE1_ICTLR_FIELDS_0_SPI2_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_SPI3_SHIFT                        _MK_SHIFT_CONST(6)
#define SLICE1_ICTLR_FIELDS_0_SPI3_FIELD                        _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI3_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_SPI3_RANGE                        _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
#define SLICE1_ICTLR_FIELDS_0_SPI3_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_SPI4_SHIFT                        _MK_SHIFT_CONST(7)
#define SLICE1_ICTLR_FIELDS_0_SPI4_FIELD                        _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI4_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_SPI4_RANGE                        _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
#define SLICE1_ICTLR_FIELDS_0_SPI4_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_CAN1_0_SHIFT                      _MK_SHIFT_CONST(8)
#define SLICE1_ICTLR_FIELDS_0_CAN1_0_FIELD                      _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN1_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_CAN1_0_RANGE                      _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
#define SLICE1_ICTLR_FIELDS_0_CAN1_0_ROW                        0

#define SLICE1_ICTLR_FIELDS_0_CAN1_1_SHIFT                      _MK_SHIFT_CONST(9)
#define SLICE1_ICTLR_FIELDS_0_CAN1_1_FIELD                      _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN1_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_CAN1_1_RANGE                      _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
#define SLICE1_ICTLR_FIELDS_0_CAN1_1_ROW                        0

#define SLICE1_ICTLR_FIELDS_0_CAN2_0_SHIFT                      _MK_SHIFT_CONST(10)
#define SLICE1_ICTLR_FIELDS_0_CAN2_0_FIELD                      _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN2_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_CAN2_0_RANGE                      _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
#define SLICE1_ICTLR_FIELDS_0_CAN2_0_ROW                        0

#define SLICE1_ICTLR_FIELDS_0_CAN2_1_SHIFT                      _MK_SHIFT_CONST(11)
#define SLICE1_ICTLR_FIELDS_0_CAN2_1_FIELD                      _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN2_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_CAN2_1_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
#define SLICE1_ICTLR_FIELDS_0_CAN2_1_ROW                        0

#define SLICE1_ICTLR_FIELDS_0_UFSHC_SHIFT                       _MK_SHIFT_CONST(12)
#define SLICE1_ICTLR_FIELDS_0_UFSHC_FIELD                       _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_UFSHC_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_UFSHC_RANGE                       _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12)
#define SLICE1_ICTLR_FIELDS_0_UFSHC_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_GPIO0_0_SHIFT                     _MK_SHIFT_CONST(13)
#define SLICE1_ICTLR_FIELDS_0_GPIO0_0_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO0_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO0_0_RANGE                     _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13)
#define SLICE1_ICTLR_FIELDS_0_GPIO0_0_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO0_1_SHIFT                     _MK_SHIFT_CONST(14)
#define SLICE1_ICTLR_FIELDS_0_GPIO0_1_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO0_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO0_1_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
#define SLICE1_ICTLR_FIELDS_0_GPIO0_1_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO0_2_SHIFT                     _MK_SHIFT_CONST(15)
#define SLICE1_ICTLR_FIELDS_0_GPIO0_2_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO0_2_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO0_2_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
#define SLICE1_ICTLR_FIELDS_0_GPIO0_2_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO1_0_SHIFT                     _MK_SHIFT_CONST(16)
#define SLICE1_ICTLR_FIELDS_0_GPIO1_0_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO1_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO1_0_RANGE                     _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
#define SLICE1_ICTLR_FIELDS_0_GPIO1_0_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO1_1_SHIFT                     _MK_SHIFT_CONST(17)
#define SLICE1_ICTLR_FIELDS_0_GPIO1_1_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO1_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO1_1_RANGE                     _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
#define SLICE1_ICTLR_FIELDS_0_GPIO1_1_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO1_2_SHIFT                     _MK_SHIFT_CONST(18)
#define SLICE1_ICTLR_FIELDS_0_GPIO1_2_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO1_2_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO1_2_RANGE                     _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
#define SLICE1_ICTLR_FIELDS_0_GPIO1_2_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO2_0_SHIFT                     _MK_SHIFT_CONST(19)
#define SLICE1_ICTLR_FIELDS_0_GPIO2_0_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO2_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO2_0_RANGE                     _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
#define SLICE1_ICTLR_FIELDS_0_GPIO2_0_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO2_1_SHIFT                     _MK_SHIFT_CONST(20)
#define SLICE1_ICTLR_FIELDS_0_GPIO2_1_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO2_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO2_1_RANGE                     _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
#define SLICE1_ICTLR_FIELDS_0_GPIO2_1_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO2_2_SHIFT                     _MK_SHIFT_CONST(21)
#define SLICE1_ICTLR_FIELDS_0_GPIO2_2_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO2_2_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO2_2_RANGE                     _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
#define SLICE1_ICTLR_FIELDS_0_GPIO2_2_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO3_0_SHIFT                     _MK_SHIFT_CONST(22)
#define SLICE1_ICTLR_FIELDS_0_GPIO3_0_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO3_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO3_0_RANGE                     _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
#define SLICE1_ICTLR_FIELDS_0_GPIO3_0_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO3_1_SHIFT                     _MK_SHIFT_CONST(23)
#define SLICE1_ICTLR_FIELDS_0_GPIO3_1_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO3_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO3_1_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
#define SLICE1_ICTLR_FIELDS_0_GPIO3_1_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO3_2_SHIFT                     _MK_SHIFT_CONST(24)
#define SLICE1_ICTLR_FIELDS_0_GPIO3_2_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO3_2_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO3_2_RANGE                     _MK_SHIFT_CONST(24):_MK_SHIFT_CONST(24)
#define SLICE1_ICTLR_FIELDS_0_GPIO3_2_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO4_0_SHIFT                     _MK_SHIFT_CONST(25)
#define SLICE1_ICTLR_FIELDS_0_GPIO4_0_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO4_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO4_0_RANGE                     _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(25)
#define SLICE1_ICTLR_FIELDS_0_GPIO4_0_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO4_1_SHIFT                     _MK_SHIFT_CONST(26)
#define SLICE1_ICTLR_FIELDS_0_GPIO4_1_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO4_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO4_1_RANGE                     _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
#define SLICE1_ICTLR_FIELDS_0_GPIO4_1_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_GPIO4_2_SHIFT                     _MK_SHIFT_CONST(27)
#define SLICE1_ICTLR_FIELDS_0_GPIO4_2_FIELD                     _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_GPIO4_2_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_GPIO4_2_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
#define SLICE1_ICTLR_FIELDS_0_GPIO4_2_ROW                       0

#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_SHIFT                  _MK_SHIFT_CONST(28)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_FIELD                  _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_ROW                    0

#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_SHIFT                  _MK_SHIFT_CONST(29)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_FIELD                  _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_RANGE                  _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_ROW                    0

#define SLICE1_ICTLR_FIELDS_0_SDMMC1_SHIFT                      _MK_SHIFT_CONST(30)
#define SLICE1_ICTLR_FIELDS_0_SDMMC1_FIELD                      _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SDMMC1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_SDMMC1_RANGE                      _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
#define SLICE1_ICTLR_FIELDS_0_SDMMC1_ROW                        0

#define SLICE1_ICTLR_FIELDS_0_SDMMC2_SHIFT                      _MK_SHIFT_CONST(31)
#define SLICE1_ICTLR_FIELDS_0_SDMMC2_FIELD                      _MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SDMMC2_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_SDMMC2_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
#define SLICE1_ICTLR_FIELDS_0_SDMMC2_ROW                        0


// Packet SLICE2_ICTLR_FIELDS_0
#define SLICE2_ICTLR_FIELDS_0_SIZE 32

#define SLICE2_ICTLR_FIELDS_0_SDMMC3_SHIFT                      _MK_SHIFT_CONST(0)
#define SLICE2_ICTLR_FIELDS_0_SDMMC3_FIELD                      _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC3_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_SDMMC3_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
#define SLICE2_ICTLR_FIELDS_0_SDMMC3_ROW                        0

#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SHIFT                      _MK_SHIFT_CONST(1)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_FIELD                      _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC4_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_RANGE                      _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_ROW                        0

#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_SHIFT                  _MK_SHIFT_CONST(2)
#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_FIELD                  _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_RANGE                  _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_ROW                    0

#define SLICE2_ICTLR_FIELDS_0_SDMMC2_SYS_SHIFT                  _MK_SHIFT_CONST(3)
#define SLICE2_ICTLR_FIELDS_0_SDMMC2_SYS_FIELD                  _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC2_SYS_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_SDMMC2_SYS_RANGE                  _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
#define SLICE2_ICTLR_FIELDS_0_SDMMC2_SYS_ROW                    0

#define SLICE2_ICTLR_FIELDS_0_SDMMC3_SYS_SHIFT                  _MK_SHIFT_CONST(4)
#define SLICE2_ICTLR_FIELDS_0_SDMMC3_SYS_FIELD                  _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC3_SYS_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_SDMMC3_SYS_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
#define SLICE2_ICTLR_FIELDS_0_SDMMC3_SYS_ROW                    0

#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_SHIFT                  _MK_SHIFT_CONST(5)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_FIELD                  _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_RANGE                  _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_ROW                    0

#define SLICE2_ICTLR_FIELDS_0_GPU_STALL_SHIFT                   _MK_SHIFT_CONST(6)
#define SLICE2_ICTLR_FIELDS_0_GPU_STALL_FIELD                   _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_GPU_STALL_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_GPU_STALL_RANGE                   _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
#define SLICE2_ICTLR_FIELDS_0_GPU_STALL_ROW                     0

#define SLICE2_ICTLR_FIELDS_0_GPU_NONSTALL_SHIFT                        _MK_SHIFT_CONST(7)
#define SLICE2_ICTLR_FIELDS_0_GPU_NONSTALL_FIELD                        _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_GPU_NONSTALL_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_GPU_NONSTALL_RANGE                        _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
#define SLICE2_ICTLR_FIELDS_0_GPU_NONSTALL_ROW                  0

#define SLICE2_ICTLR_FIELDS_0_PCIE_INT_SHIFT                    _MK_SHIFT_CONST(8)
#define SLICE2_ICTLR_FIELDS_0_PCIE_INT_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_PCIE_INT_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_PCIE_INT_RANGE                    _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
#define SLICE2_ICTLR_FIELDS_0_PCIE_INT_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_PCIE_MSI_SHIFT                    _MK_SHIFT_CONST(9)
#define SLICE2_ICTLR_FIELDS_0_PCIE_MSI_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_PCIE_MSI_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_PCIE_MSI_RANGE                    _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
#define SLICE2_ICTLR_FIELDS_0_PCIE_MSI_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_PCIE_WAKE_SHIFT                   _MK_SHIFT_CONST(10)
#define SLICE2_ICTLR_FIELDS_0_PCIE_WAKE_FIELD                   _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_PCIE_WAKE_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_PCIE_WAKE_RANGE                   _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
#define SLICE2_ICTLR_FIELDS_0_PCIE_WAKE_ROW                     0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_SHIFT                     _MK_SHIFT_CONST(11)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_FIELD                     _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_SHIFT                     _MK_SHIFT_CONST(12)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_FIELD                     _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_RANGE                     _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_SHIFT                     _MK_SHIFT_CONST(13)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_FIELD                     _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_RANGE                     _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_SHIFT                     _MK_SHIFT_CONST(14)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_FIELD                     _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_SHIFT                     _MK_SHIFT_CONST(15)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_FIELD                     _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_SHIFT                     _MK_SHIFT_CONST(16)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_FIELD                     _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_RANGE                     _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_SHIFT                     _MK_SHIFT_CONST(17)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_FIELD                     _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_RANGE                     _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_SHIFT                     _MK_SHIFT_CONST(18)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_FIELD                     _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_RANGE                     _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_SHIFT                     _MK_SHIFT_CONST(19)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_FIELD                     _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_RANGE                     _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_SHIFT                     _MK_SHIFT_CONST(20)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_FIELD                     _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_RANGE                     _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_SHIFT                    _MK_SHIFT_CONST(21)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_RANGE                    _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_SHIFT                    _MK_SHIFT_CONST(22)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_RANGE                    _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_SHIFT                    _MK_SHIFT_CONST(23)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_SHIFT                    _MK_SHIFT_CONST(24)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_RANGE                    _MK_SHIFT_CONST(24):_MK_SHIFT_CONST(24)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_SHIFT                    _MK_SHIFT_CONST(25)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_RANGE                    _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(25)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_SHIFT                    _MK_SHIFT_CONST(26)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_RANGE                    _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_SHIFT                    _MK_SHIFT_CONST(27)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_RANGE                    _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_SHIFT                    _MK_SHIFT_CONST(28)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_RANGE                    _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_SHIFT                    _MK_SHIFT_CONST(29)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_SHIFT                    _MK_SHIFT_CONST(30)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_RANGE                    _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_SHIFT                    _MK_SHIFT_CONST(31)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_FIELD                    _MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_ROW                      0


// Packet SLICE3_ICTLR_FIELDS_0
#define SLICE3_ICTLR_FIELDS_0_SIZE 32

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_SHIFT                    _MK_SHIFT_CONST(0)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_FIELD                    _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_SHIFT                    _MK_SHIFT_CONST(1)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_FIELD                    _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_SHIFT                    _MK_SHIFT_CONST(2)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_FIELD                    _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_SHIFT                    _MK_SHIFT_CONST(3)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_FIELD                    _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_RANGE                    _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_SHIFT                    _MK_SHIFT_CONST(4)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_FIELD                    _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_SHIFT                    _MK_SHIFT_CONST(5)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_FIELD                    _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_RANGE                    _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_SHIFT                    _MK_SHIFT_CONST(6)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_FIELD                    _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_SHIFT                    _MK_SHIFT_CONST(7)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_FIELD                    _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_RANGE                    _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_SHIFT                    _MK_SHIFT_CONST(8)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_FIELD                    _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_RANGE                    _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_SHIFT                    _MK_SHIFT_CONST(9)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_FIELD                    _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_RANGE                    _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_SHIFT                    _MK_SHIFT_CONST(10)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_FIELD                    _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_RANGE                    _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_SHIFT                  _MK_SHIFT_CONST(11)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_FIELD                  _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_RANGE                  _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_ROW                    0

#define SLICE3_ICTLR_FIELDS_0_SIMON0_SHIFT                      _MK_SHIFT_CONST(12)
#define SLICE3_ICTLR_FIELDS_0_SIMON0_FIELD                      _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_SIMON0_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_SIMON0_RANGE                      _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12)
#define SLICE3_ICTLR_FIELDS_0_SIMON0_ROW                        0

#define SLICE3_ICTLR_FIELDS_0_SIMON1_SHIFT                      _MK_SHIFT_CONST(13)
#define SLICE3_ICTLR_FIELDS_0_SIMON1_FIELD                      _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_SIMON1_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_SIMON1_RANGE                      _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13)
#define SLICE3_ICTLR_FIELDS_0_SIMON1_ROW                        0

#define SLICE3_ICTLR_FIELDS_0_SIMON2_SHIFT                      _MK_SHIFT_CONST(14)
#define SLICE3_ICTLR_FIELDS_0_SIMON2_FIELD                      _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_SIMON2_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_SIMON2_RANGE                      _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
#define SLICE3_ICTLR_FIELDS_0_SIMON2_ROW                        0

#define SLICE3_ICTLR_FIELDS_0_SIMON3_SHIFT                      _MK_SHIFT_CONST(15)
#define SLICE3_ICTLR_FIELDS_0_SIMON3_FIELD                      _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_SIMON3_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_SIMON3_RANGE                      _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
#define SLICE3_ICTLR_FIELDS_0_SIMON3_ROW                        0

#define SLICE3_ICTLR_FIELDS_0_UARTA_SHIFT                       _MK_SHIFT_CONST(16)
#define SLICE3_ICTLR_FIELDS_0_UARTA_FIELD                       _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTA_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTA_RANGE                       _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
#define SLICE3_ICTLR_FIELDS_0_UARTA_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_UARTB_SHIFT                       _MK_SHIFT_CONST(17)
#define SLICE3_ICTLR_FIELDS_0_UARTB_FIELD                       _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTB_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTB_RANGE                       _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
#define SLICE3_ICTLR_FIELDS_0_UARTB_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_UARTC_SHIFT                       _MK_SHIFT_CONST(18)
#define SLICE3_ICTLR_FIELDS_0_UARTC_FIELD                       _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTC_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTC_RANGE                       _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
#define SLICE3_ICTLR_FIELDS_0_UARTC_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_UARTD_SHIFT                       _MK_SHIFT_CONST(19)
#define SLICE3_ICTLR_FIELDS_0_UARTD_FIELD                       _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTD_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTD_RANGE                       _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
#define SLICE3_ICTLR_FIELDS_0_UARTD_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_UARTE_SHIFT                       _MK_SHIFT_CONST(20)
#define SLICE3_ICTLR_FIELDS_0_UARTE_FIELD                       _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTE_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTE_RANGE                       _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
#define SLICE3_ICTLR_FIELDS_0_UARTE_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_UARTF_SHIFT                       _MK_SHIFT_CONST(21)
#define SLICE3_ICTLR_FIELDS_0_UARTF_FIELD                       _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTF_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTF_RANGE                       _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
#define SLICE3_ICTLR_FIELDS_0_UARTF_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_UARTG_SHIFT                       _MK_SHIFT_CONST(22)
#define SLICE3_ICTLR_FIELDS_0_UARTG_FIELD                       _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTG_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTG_RANGE                       _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
#define SLICE3_ICTLR_FIELDS_0_UARTG_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_NVCSI_SHIFT                       _MK_SHIFT_CONST(23)
#define SLICE3_ICTLR_FIELDS_0_NVCSI_FIELD                       _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_NVCSI_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_NVCSI_RANGE                       _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
#define SLICE3_ICTLR_FIELDS_0_NVCSI_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_SHIFT                   _MK_SHIFT_CONST(24)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_FIELD                   _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_RANGE                   _MK_SHIFT_CONST(24):_MK_SHIFT_CONST(24)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_SHIFT                   _MK_SHIFT_CONST(25)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_FIELD                   _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_RANGE                   _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(25)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_SHIFT                   _MK_SHIFT_CONST(26)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_FIELD                   _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_RANGE                   _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_SHIFT                   _MK_SHIFT_CONST(27)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_FIELD                   _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_RANGE                   _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_SHIFT                   _MK_SHIFT_CONST(28)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_FIELD                   _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_RANGE                   _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_SHIFT                   _MK_SHIFT_CONST(29)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_FIELD                   _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_RANGE                   _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_SHIFT                   _MK_SHIFT_CONST(30)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_FIELD                   _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_RANGE                   _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_SHIFT                   _MK_SHIFT_CONST(31)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_FIELD                   _MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_ROW                     0


// Packet SLICE4_ICTLR_FIELDS_0
#define SLICE4_ICTLR_FIELDS_0_SIZE 32

#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_SHIFT                   _MK_SHIFT_CONST(0)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_FIELD                   _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_RANGE                   _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_SHIFT                   _MK_SHIFT_CONST(1)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_FIELD                   _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_RANGE                   _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_SHIFT                   _MK_SHIFT_CONST(2)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_FIELD                   _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_RANGE                   _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_SHIFT                   _MK_SHIFT_CONST(3)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_FIELD                   _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_RANGE                   _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_SHIFT                   _MK_SHIFT_CONST(4)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_FIELD                   _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_RANGE                   _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_SHIFT                      _MK_SHIFT_CONST(5)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_FIELD                      _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_SHIFT                      _MK_SHIFT_CONST(6)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_FIELD                      _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_RANGE                      _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_SHIFT                      _MK_SHIFT_CONST(7)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_FIELD                      _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_RANGE                      _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_SHIFT                      _MK_SHIFT_CONST(8)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_FIELD                      _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_RANGE                      _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_SHIFT                   _MK_SHIFT_CONST(9)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_FIELD                   _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_RANGE                   _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_SHIFT                   _MK_SHIFT_CONST(10)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_FIELD                   _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_RANGE                   _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_SHIFT                   _MK_SHIFT_CONST(11)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_FIELD                   _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_RANGE                   _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_SHIFT                   _MK_SHIFT_CONST(12)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_FIELD                   _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_RANGE                   _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_SHIFT                      _MK_SHIFT_CONST(13)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_FIELD                      _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_RANGE                      _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_SHIFT                      _MK_SHIFT_CONST(14)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_FIELD                      _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_RANGE                      _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_SHIFT                      _MK_SHIFT_CONST(15)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_FIELD                      _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_RANGE                      _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_SHIFT                      _MK_SHIFT_CONST(16)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_FIELD                      _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_RANGE                      _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_SHIFT                    _MK_SHIFT_CONST(17)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_FIELD                    _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_RANGE                    _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_SHIFT                    _MK_SHIFT_CONST(18)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_FIELD                    _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_RANGE                    _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_SHIFT                    _MK_SHIFT_CONST(19)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_FIELD                    _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_RANGE                    _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_SHIFT                    _MK_SHIFT_CONST(20)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_FIELD                    _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_RANGE                    _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_SHIFT                    _MK_SHIFT_CONST(21)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_FIELD                    _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_RANGE                    _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_SHIFT                    _MK_SHIFT_CONST(22)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_FIELD                    _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_RANGE                    _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_SHIFT                    _MK_SHIFT_CONST(23)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_FIELD                    _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_SHIFT                    _MK_SHIFT_CONST(24)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_FIELD                    _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_RANGE                    _MK_SHIFT_CONST(24):_MK_SHIFT_CONST(24)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD0_SHIFT                       _MK_SHIFT_CONST(25)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD0_FIELD                       _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD0_RANGE                       _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(25)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD0_ROW                 0

#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD1_SHIFT                       _MK_SHIFT_CONST(26)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD1_FIELD                       _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD1_RANGE                       _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD1_ROW                 0

#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD2_SHIFT                       _MK_SHIFT_CONST(27)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD2_FIELD                       _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD2_RANGE                       _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_HEAD2_ROW                 0

#define SLICE4_ICTLR_FIELDS_0_DISPLAY_TZ_SHIFT                  _MK_SHIFT_CONST(28)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_TZ_FIELD                  _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_DISPLAY_TZ_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_TZ_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
#define SLICE4_ICTLR_FIELDS_0_DISPLAY_TZ_ROW                    0

#define SLICE4_ICTLR_FIELDS_0_SOR_SHIFT                 _MK_SHIFT_CONST(29)
#define SLICE4_ICTLR_FIELDS_0_SOR_FIELD                 _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SOR_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_SOR_RANGE                 _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
#define SLICE4_ICTLR_FIELDS_0_SOR_ROW                   0

#define SLICE4_ICTLR_FIELDS_0_SOR1_SHIFT                        _MK_SHIFT_CONST(30)
#define SLICE4_ICTLR_FIELDS_0_SOR1_FIELD                        _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SOR1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_SOR1_RANGE                        _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
#define SLICE4_ICTLR_FIELDS_0_SOR1_ROW                  0

#define SLICE4_ICTLR_FIELDS_0_DPAUX_SHIFT                       _MK_SHIFT_CONST(31)
#define SLICE4_ICTLR_FIELDS_0_DPAUX_FIELD                       _MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_DPAUX_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_DPAUX_RANGE                       _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
#define SLICE4_ICTLR_FIELDS_0_DPAUX_ROW                 0


// Packet SLICE5_ICTLR_FIELDS_0
#define SLICE5_ICTLR_FIELDS_0_SIZE 32

#define SLICE5_ICTLR_FIELDS_0_DPAUX1_SHIFT                      _MK_SHIFT_CONST(0)
#define SLICE5_ICTLR_FIELDS_0_DPAUX1_FIELD                      _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_DPAUX1_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_DPAUX1_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
#define SLICE5_ICTLR_FIELDS_0_DPAUX1_ROW                        0

#define SLICE5_ICTLR_FIELDS_0_HDA_SHIFT                 _MK_SHIFT_CONST(1)
#define SLICE5_ICTLR_FIELDS_0_HDA_FIELD                 _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_HDA_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_HDA_RANGE                 _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
#define SLICE5_ICTLR_FIELDS_0_HDA_ROW                   0

#define SLICE5_ICTLR_FIELDS_0_CEC_SHIFT                 _MK_SHIFT_CONST(2)
#define SLICE5_ICTLR_FIELDS_0_CEC_FIELD                 _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_CEC_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_CEC_RANGE                 _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
#define SLICE5_ICTLR_FIELDS_0_CEC_ROW                   0

#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_SHIFT                       _MK_SHIFT_CONST(3)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_FIELD                       _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_RANGE                       _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_ROW                 0

#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_SHIFT                       _MK_SHIFT_CONST(4)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_FIELD                       _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_ROW                 0

#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_SHIFT                       _MK_SHIFT_CONST(5)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_FIELD                       _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_RANGE                       _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_ROW                 0

#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_SHIFT                        _MK_SHIFT_CONST(6)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_FIELD                        _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_RANGE                        _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_ROW                  0

#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_SHIFT                 _MK_SHIFT_CONST(7)
#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_FIELD                 _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_ROW                   0

#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_SHIFT                        _MK_SHIFT_CONST(8)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_FIELD                        _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_RANGE                        _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_ROW                  0

#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_SHIFT                        _MK_SHIFT_CONST(9)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_FIELD                        _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_ROW                  0

#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_SHIFT                    _MK_SHIFT_CONST(10)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_FIELD                    _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_RANGE                    _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_ROW                      0

#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_SHIFT                     _MK_SHIFT_CONST(11)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_FIELD                     _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_ROW                       0

#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_BRIDGE_SHIFT                   _MK_SHIFT_CONST(12)
#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_BRIDGE_FIELD                   _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SECURE_AON_BRIDGE_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_BRIDGE_RANGE                   _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12)
#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_BRIDGE_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_BRIDGE_SHIFT                   _MK_SHIFT_CONST(13)
#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_BRIDGE_FIELD                   _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SECURE_SCE_BRIDGE_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_BRIDGE_RANGE                   _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13)
#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_BRIDGE_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_BRIDGE_SHIFT                  _MK_SHIFT_CONST(14)
#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_BRIDGE_FIELD                  _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_BRIDGE_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_BRIDGE_RANGE                  _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_BRIDGE_ROW                    0

#define SLICE5_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_SHIFT                    _MK_SHIFT_CONST(15)
#define SLICE5_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_FIELD                    _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
#define SLICE5_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_ROW                      0

#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_SHIFT                  _MK_SHIFT_CONST(16)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_FIELD                  _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_RANGE                  _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_ROW                    0

#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_SHIFT                      _MK_SHIFT_CONST(17)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_FIELD                      _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_RANGE                      _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_ROW                        0

#define SLICE5_ICTLR_FIELDS_0_GPIO5_0_SHIFT                     _MK_SHIFT_CONST(18)
#define SLICE5_ICTLR_FIELDS_0_GPIO5_0_FIELD                     _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_GPIO5_0_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_GPIO5_0_RANGE                     _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
#define SLICE5_ICTLR_FIELDS_0_GPIO5_0_ROW                       0

#define SLICE5_ICTLR_FIELDS_0_GPIO5_1_SHIFT                     _MK_SHIFT_CONST(19)
#define SLICE5_ICTLR_FIELDS_0_GPIO5_1_FIELD                     _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_GPIO5_1_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_GPIO5_1_RANGE                     _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
#define SLICE5_ICTLR_FIELDS_0_GPIO5_1_ROW                       0

#define SLICE5_ICTLR_FIELDS_0_GPIO5_2_SHIFT                     _MK_SHIFT_CONST(20)
#define SLICE5_ICTLR_FIELDS_0_GPIO5_2_FIELD                     _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_GPIO5_2_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_GPIO5_2_RANGE                     _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
#define SLICE5_ICTLR_FIELDS_0_GPIO5_2_ROW                       0

#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_SHIFT                        _MK_SHIFT_CONST(21)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_FIELD                        _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RESERVED_181_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_RANGE                        _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_ROW                  0

#define SLICE5_ICTLR_FIELDS_0_MPCORE_AXIERRIRQ_0_SHIFT                  _MK_SHIFT_CONST(22)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_AXIERRIRQ_0_FIELD                  _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_MPCORE_AXIERRIRQ_0_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_AXIERRIRQ_0_RANGE                  _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_AXIERRIRQ_0_ROW                    0

#define SLICE5_ICTLR_FIELDS_0_MPCORE_AXIERRIRQ_1_SHIFT                  _MK_SHIFT_CONST(23)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_AXIERRIRQ_1_FIELD                  _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_MPCORE_AXIERRIRQ_1_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_AXIERRIRQ_1_RANGE                  _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_AXIERRIRQ_1_ROW                    0

#define SLICE5_ICTLR_FIELDS_0_MPCORE_INTERRIRQ_0_SHIFT                  _MK_SHIFT_CONST(24)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_INTERRIRQ_0_FIELD                  _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_MPCORE_INTERRIRQ_0_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_INTERRIRQ_0_RANGE                  _MK_SHIFT_CONST(24):_MK_SHIFT_CONST(24)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_INTERRIRQ_0_ROW                    0

#define SLICE5_ICTLR_FIELDS_0_MPCORE_INTERRIRQ_1_SHIFT                  _MK_SHIFT_CONST(25)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_INTERRIRQ_1_FIELD                  _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_MPCORE_INTERRIRQ_1_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_INTERRIRQ_1_RANGE                  _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(25)
#define SLICE5_ICTLR_FIELDS_0_MPCORE_INTERRIRQ_1_ROW                    0

#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_0_SHIFT                   _MK_SHIFT_CONST(26)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_0_FIELD                   _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_TX_0_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_0_RANGE                   _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_0_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_1_SHIFT                   _MK_SHIFT_CONST(27)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_1_FIELD                   _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_TX_1_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_1_RANGE                   _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_1_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_2_SHIFT                   _MK_SHIFT_CONST(28)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_2_FIELD                   _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_TX_2_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_2_RANGE                   _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_2_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_3_SHIFT                   _MK_SHIFT_CONST(29)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_3_FIELD                   _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_TX_3_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_3_RANGE                   _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
#define SLICE5_ICTLR_FIELDS_0_EQOS_TX_3_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_EQOS_RX_0_SHIFT                   _MK_SHIFT_CONST(30)
#define SLICE5_ICTLR_FIELDS_0_EQOS_RX_0_FIELD                   _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_RX_0_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_RX_0_RANGE                   _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
#define SLICE5_ICTLR_FIELDS_0_EQOS_RX_0_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_EQOS_RX_1_SHIFT                   _MK_SHIFT_CONST(31)
#define SLICE5_ICTLR_FIELDS_0_EQOS_RX_1_FIELD                   _MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_RX_1_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_RX_1_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
#define SLICE5_ICTLR_FIELDS_0_EQOS_RX_1_ROW                     0


// Packet SLICE6_ICTLR_FIELDS_0
#define SLICE6_ICTLR_FIELDS_0_SIZE 32

#define SLICE6_ICTLR_FIELDS_0_EQOS_RX_2_SHIFT                   _MK_SHIFT_CONST(0)
#define SLICE6_ICTLR_FIELDS_0_EQOS_RX_2_FIELD                   _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_EQOS_RX_2_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_EQOS_RX_2_RANGE                   _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
#define SLICE6_ICTLR_FIELDS_0_EQOS_RX_2_ROW                     0

#define SLICE6_ICTLR_FIELDS_0_EQOS_RX_3_SHIFT                   _MK_SHIFT_CONST(1)
#define SLICE6_ICTLR_FIELDS_0_EQOS_RX_3_FIELD                   _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_EQOS_RX_3_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_EQOS_RX_3_RANGE                   _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
#define SLICE6_ICTLR_FIELDS_0_EQOS_RX_3_ROW                     0

#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_SHIFT                 _MK_SHIFT_CONST(2)
#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_FIELD                 _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_RANGE                 _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_ROW                   0

#define SLICE6_ICTLR_FIELDS_0_EQOS_POWER_SHIFT                  _MK_SHIFT_CONST(3)
#define SLICE6_ICTLR_FIELDS_0_EQOS_POWER_FIELD                  _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_EQOS_POWER_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_EQOS_POWER_RANGE                  _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
#define SLICE6_ICTLR_FIELDS_0_EQOS_POWER_ROW                    0

#define SLICE6_ICTLR_FIELDS_0_SATA_RX_STAT_SHIFT                        _MK_SHIFT_CONST(4)
#define SLICE6_ICTLR_FIELDS_0_SATA_RX_STAT_FIELD                        _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_SATA_RX_STAT_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_SATA_RX_STAT_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
#define SLICE6_ICTLR_FIELDS_0_SATA_RX_STAT_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_SATA_CTL_SHIFT                    _MK_SHIFT_CONST(5)
#define SLICE6_ICTLR_FIELDS_0_SATA_CTL_FIELD                    _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_SATA_CTL_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_SATA_CTL_RANGE                    _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
#define SLICE6_ICTLR_FIELDS_0_SATA_CTL_ROW                      0

#define SLICE6_ICTLR_FIELDS_0_NVJPG_SHIFT                       _MK_SHIFT_CONST(6)
#define SLICE6_ICTLR_FIELDS_0_NVJPG_FIELD                       _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_NVJPG_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_NVJPG_RANGE                       _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
#define SLICE6_ICTLR_FIELDS_0_NVJPG_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_NVDEC_SHIFT                       _MK_SHIFT_CONST(7)
#define SLICE6_ICTLR_FIELDS_0_NVDEC_FIELD                       _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_NVDEC_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_NVDEC_RANGE                       _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
#define SLICE6_ICTLR_FIELDS_0_NVDEC_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_NVENC_SHIFT                       _MK_SHIFT_CONST(8)
#define SLICE6_ICTLR_FIELDS_0_NVENC_FIELD                       _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_NVENC_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_NVENC_RANGE                       _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
#define SLICE6_ICTLR_FIELDS_0_NVENC_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_VI_0_SHIFT                        _MK_SHIFT_CONST(9)
#define SLICE6_ICTLR_FIELDS_0_VI_0_FIELD                        _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_VI_0_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_VI_0_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
#define SLICE6_ICTLR_FIELDS_0_VI_0_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_VI_1_SHIFT                        _MK_SHIFT_CONST(10)
#define SLICE6_ICTLR_FIELDS_0_VI_1_FIELD                        _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_VI_1_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_VI_1_RANGE                        _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
#define SLICE6_ICTLR_FIELDS_0_VI_1_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_VI_2_SHIFT                        _MK_SHIFT_CONST(11)
#define SLICE6_ICTLR_FIELDS_0_VI_2_FIELD                        _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_VI_2_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_VI_2_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
#define SLICE6_ICTLR_FIELDS_0_VI_2_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_RESERVED_204_SHIFT                        _MK_SHIFT_CONST(12)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_204_FIELD                        _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_RESERVED_204_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_204_RANGE                        _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_204_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_ISP_SHIFT                 _MK_SHIFT_CONST(13)
#define SLICE6_ICTLR_FIELDS_0_ISP_FIELD                 _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_ISP_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_ISP_RANGE                 _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13)
#define SLICE6_ICTLR_FIELDS_0_ISP_ROW                   0

#define SLICE6_ICTLR_FIELDS_0_VIC_SHIFT                 _MK_SHIFT_CONST(14)
#define SLICE6_ICTLR_FIELDS_0_VIC_FIELD                 _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_VIC_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_VIC_RANGE                 _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
#define SLICE6_ICTLR_FIELDS_0_VIC_ROW                   0

#define SLICE6_ICTLR_FIELDS_0_DTV_SHIFT                 _MK_SHIFT_CONST(15)
#define SLICE6_ICTLR_FIELDS_0_DTV_FIELD                 _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_DTV_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_DTV_RANGE                 _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
#define SLICE6_ICTLR_FIELDS_0_DTV_ROW                   0

#define SLICE6_ICTLR_FIELDS_0_CVC_SHIFT                 _MK_SHIFT_CONST(16)
#define SLICE6_ICTLR_FIELDS_0_CVC_FIELD                 _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_CVC_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_CVC_RANGE                 _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
#define SLICE6_ICTLR_FIELDS_0_CVC_ROW                   0

#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_SHIFT                    _MK_SHIFT_CONST(17)
#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_FIELD                    _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PMIC_EXT_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_RANGE                    _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_ROW                      0

#define SLICE6_ICTLR_FIELDS_0_ACTMON_SHIFT                      _MK_SHIFT_CONST(18)
#define SLICE6_ICTLR_FIELDS_0_ACTMON_FIELD                      _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_ACTMON_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_ACTMON_RANGE                      _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
#define SLICE6_ICTLR_FIELDS_0_ACTMON_ROW                        0

#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_SHIFT                        _MK_SHIFT_CONST(19)
#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_FIELD                        _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_RANGE                        _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_SHIFT                  _MK_SHIFT_CONST(20)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_FIELD                  _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_RANGE                  _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_ROW                    0

#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_SHIFT                  _MK_SHIFT_CONST(21)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_FIELD                  _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_RANGE                  _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_ROW                    0

#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_SHIFT                  _MK_SHIFT_CONST(22)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_FIELD                  _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_RANGE                  _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_ROW                    0

#define SLICE6_ICTLR_FIELDS_0_AOVC_LIC_INTR_SHIFT                       _MK_SHIFT_CONST(23)
#define SLICE6_ICTLR_FIELDS_0_AOVC_LIC_INTR_FIELD                       _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AOVC_LIC_INTR_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_AOVC_LIC_INTR_RANGE                       _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
#define SLICE6_ICTLR_FIELDS_0_AOVC_LIC_INTR_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_AON_PM_SHIFT                      _MK_SHIFT_CONST(24)
#define SLICE6_ICTLR_FIELDS_0_AON_PM_FIELD                      _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_PM_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_AON_PM_RANGE                      _MK_SHIFT_CONST(24):_MK_SHIFT_CONST(24)
#define SLICE6_ICTLR_FIELDS_0_AON_PM_ROW                        0

#define SLICE6_ICTLR_FIELDS_0_BPMP_PM_SHIFT                     _MK_SHIFT_CONST(25)
#define SLICE6_ICTLR_FIELDS_0_BPMP_PM_FIELD                     _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_BPMP_PM_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_BPMP_PM_RANGE                     _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(25)
#define SLICE6_ICTLR_FIELDS_0_BPMP_PM_ROW                       0

#define SLICE6_ICTLR_FIELDS_0_THERMAL_SHIFT                     _MK_SHIFT_CONST(26)
#define SLICE6_ICTLR_FIELDS_0_THERMAL_FIELD                     _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_THERMAL_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_THERMAL_RANGE                     _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
#define SLICE6_ICTLR_FIELDS_0_THERMAL_ROW                       0

#define SLICE6_ICTLR_FIELDS_0_EDP_SHIFT                 _MK_SHIFT_CONST(27)
#define SLICE6_ICTLR_FIELDS_0_EDP_FIELD                 _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_EDP_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_EDP_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
#define SLICE6_ICTLR_FIELDS_0_EDP_ROW                   0

#define SLICE6_ICTLR_FIELDS_0_RESERVED_220_SHIFT                        _MK_SHIFT_CONST(28)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_220_FIELD                        _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_RESERVED_220_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_220_RANGE                        _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_220_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_RESERVED_221_SHIFT                        _MK_SHIFT_CONST(29)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_221_FIELD                        _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_RESERVED_221_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_221_RANGE                        _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_221_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_RESERVED_222_SHIFT                        _MK_SHIFT_CONST(30)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_222_FIELD                        _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_RESERVED_222_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_222_RANGE                        _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_222_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_MC_SHIFT                  _MK_SHIFT_CONST(31)
#define SLICE6_ICTLR_FIELDS_0_MC_FIELD                  _MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_MC_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_MC_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
#define SLICE6_ICTLR_FIELDS_0_MC_ROW                    0


// Packet SLICE7_ICTLR_FIELDS_0
#define SLICE7_ICTLR_FIELDS_0_SIZE 32

#define SLICE7_ICTLR_FIELDS_0_EMC_SHIFT                 _MK_SHIFT_CONST(0)
#define SLICE7_ICTLR_FIELDS_0_EMC_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_EMC_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_EMC_RANGE                 _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
#define SLICE7_ICTLR_FIELDS_0_EMC_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_CAR_SHIFT                 _MK_SHIFT_CONST(1)
#define SLICE7_ICTLR_FIELDS_0_CAR_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_CAR_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_CAR_RANGE                 _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
#define SLICE7_ICTLR_FIELDS_0_CAR_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_AON_CAR_SHIFT                     _MK_SHIFT_CONST(2)
#define SLICE7_ICTLR_FIELDS_0_AON_CAR_FIELD                     _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_AON_CAR_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_AON_CAR_RANGE                     _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
#define SLICE7_ICTLR_FIELDS_0_AON_CAR_ROW                       0

#define SLICE7_ICTLR_FIELDS_0_RESERVED_227_SHIFT                        _MK_SHIFT_CONST(3)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_227_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_RESERVED_227_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_227_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_227_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TSEC_SHIFT                        _MK_SHIFT_CONST(4)
#define SLICE7_ICTLR_FIELDS_0_TSEC_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TSEC_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TSEC_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
#define SLICE7_ICTLR_FIELDS_0_TSEC_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TSECB_SHIFT                       _MK_SHIFT_CONST(5)
#define SLICE7_ICTLR_FIELDS_0_TSECB_FIELD                       _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TSECB_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TSECB_RANGE                       _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
#define SLICE7_ICTLR_FIELDS_0_TSECB_ROW                 0

#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_1_SHIFT                        _MK_SHIFT_CONST(6)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_1_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_1_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_1_RANGE                        _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_1_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_2_SHIFT                        _MK_SHIFT_CONST(7)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_2_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_2_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_2_RANGE                        _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_2_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_3_SHIFT                        _MK_SHIFT_CONST(8)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_3_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_3_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_3_RANGE                        _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_3_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_4_SHIFT                        _MK_SHIFT_CONST(9)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_4_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_4_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_4_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_4_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_5_SHIFT                        _MK_SHIFT_CONST(10)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_5_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_5_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_5_RANGE                        _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
#define SLICE7_ICTLR_FIELDS_0_TOP_BRIDGE_5_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_0_SHIFT                        _MK_SHIFT_CONST(11)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_0_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_0_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_0_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_0_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_1_SHIFT                        _MK_SHIFT_CONST(12)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_1_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_1_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_1_RANGE                        _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_1_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_2_SHIFT                        _MK_SHIFT_CONST(13)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_2_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_2_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_2_RANGE                        _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_2_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_3_SHIFT                        _MK_SHIFT_CONST(14)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_3_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_3_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_3_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_3_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_4_SHIFT                        _MK_SHIFT_CONST(15)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_4_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_4_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_4_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_4_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_5_SHIFT                        _MK_SHIFT_CONST(16)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_5_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_5_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_5_RANGE                        _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_5_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_6_SHIFT                        _MK_SHIFT_CONST(17)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_6_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_6_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_6_RANGE                        _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_6_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_7_SHIFT                        _MK_SHIFT_CONST(18)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_7_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_7_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_7_RANGE                        _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_7_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_8_SHIFT                        _MK_SHIFT_CONST(19)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_8_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_8_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_8_RANGE                        _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_8_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_9_SHIFT                        _MK_SHIFT_CONST(20)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_9_FIELD                        _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_9_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_9_RANGE                        _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
#define SLICE7_ICTLR_FIELDS_0_TOP_AXIP2P_9_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_1_SHIFT                 _MK_SHIFT_CONST(21)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_1_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_1_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_1_RANGE                 _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_1_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_2_SHIFT                 _MK_SHIFT_CONST(22)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_2_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_2_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_2_RANGE                 _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_2_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_3_SHIFT                 _MK_SHIFT_CONST(23)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_3_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_3_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_3_RANGE                 _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_3_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_4_SHIFT                 _MK_SHIFT_CONST(24)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_4_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_4_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_4_RANGE                 _MK_SHIFT_CONST(24):_MK_SHIFT_CONST(24)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_4_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_5_SHIFT                 _MK_SHIFT_CONST(25)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_5_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_5_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_5_RANGE                 _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(25)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_BRIDGE_5_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_0_SHIFT                 _MK_SHIFT_CONST(26)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_0_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_0_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_0_RANGE                 _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_0_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_1_SHIFT                 _MK_SHIFT_CONST(27)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_1_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_1_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_1_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_1_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_2_SHIFT                 _MK_SHIFT_CONST(28)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_2_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_2_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_2_RANGE                 _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_2_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_3_SHIFT                 _MK_SHIFT_CONST(29)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_3_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_3_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_3_RANGE                 _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_3_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_4_SHIFT                 _MK_SHIFT_CONST(30)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_4_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_4_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_4_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_4_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_5_SHIFT                 _MK_SHIFT_CONST(31)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_5_FIELD                 _MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_5_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_5_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
#define SLICE7_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_5_ROW                   0


// Packet SLICE8_ICTLR_FIELDS_0
#define SLICE8_ICTLR_FIELDS_0_SIZE 32

#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_6_SHIFT                 _MK_SHIFT_CONST(0)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_6_FIELD                 _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_6_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_6_RANGE                 _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_6_ROW                   0

#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_7_SHIFT                 _MK_SHIFT_CONST(1)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_7_FIELD                 _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_7_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_7_RANGE                 _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_7_ROW                   0

#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_8_SHIFT                 _MK_SHIFT_CONST(2)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_8_FIELD                 _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_8_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_8_RANGE                 _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_8_ROW                   0

#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_9_SHIFT                 _MK_SHIFT_CONST(3)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_9_FIELD                 _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_9_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_9_RANGE                 _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
#define SLICE8_ICTLR_FIELDS_0_SECURE_TOP_AXIP2P_9_ROW                   0

#define SLICE8_ICTLR_FIELDS_0_AON_BRIDGE_SHIFT                  _MK_SHIFT_CONST(4)
#define SLICE8_ICTLR_FIELDS_0_AON_BRIDGE_FIELD                  _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_AON_BRIDGE_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_AON_BRIDGE_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
#define SLICE8_ICTLR_FIELDS_0_AON_BRIDGE_ROW                    0

#define SLICE8_ICTLR_FIELDS_0_SCE_BRIDGE_SHIFT                  _MK_SHIFT_CONST(5)
#define SLICE8_ICTLR_FIELDS_0_SCE_BRIDGE_FIELD                  _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SCE_BRIDGE_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SCE_BRIDGE_RANGE                  _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
#define SLICE8_ICTLR_FIELDS_0_SCE_BRIDGE_ROW                    0

#define SLICE8_ICTLR_FIELDS_0_BPMP_BRIDGE_SHIFT                 _MK_SHIFT_CONST(6)
#define SLICE8_ICTLR_FIELDS_0_BPMP_BRIDGE_FIELD                 _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_BPMP_BRIDGE_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_BPMP_BRIDGE_RANGE                 _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
#define SLICE8_ICTLR_FIELDS_0_BPMP_BRIDGE_ROW                   0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_SHIFT                      _MK_SHIFT_CONST(7)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_FIELD                      _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_RANGE                      _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_ROW                        0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_SHIFT                   _MK_SHIFT_CONST(8)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_FIELD                   _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_RANGE                   _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS0_SHIFT                        _MK_SHIFT_CONST(9)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS0_FIELD                        _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS0_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS0_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS0_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS1_SHIFT                        _MK_SHIFT_CONST(10)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS1_FIELD                        _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS1_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS1_RANGE                        _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS1_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS2_SHIFT                        _MK_SHIFT_CONST(11)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS2_FIELD                        _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS2_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS2_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS2_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS3_SHIFT                        _MK_SHIFT_CONST(12)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS3_FIELD                        _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS3_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS3_RANGE                        _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS3_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS4_SHIFT                        _MK_SHIFT_CONST(13)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS4_FIELD                        _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS4_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS4_RANGE                        _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS4_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS5_SHIFT                        _MK_SHIFT_CONST(14)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS5_FIELD                        _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS5_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS5_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS5_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS6_SHIFT                        _MK_SHIFT_CONST(15)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS6_FIELD                        _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS6_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS6_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS6_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS7_SHIFT                        _MK_SHIFT_CONST(16)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS7_FIELD                        _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS7_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS7_RANGE                        _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPUOS7_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_SHIFT                   _MK_SHIFT_CONST(17)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_FIELD                   _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_RANGE                   _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_SHIFT                        _MK_SHIFT_CONST(18)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_FIELD                        _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_RANGE                        _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_SHIFT                     _MK_SHIFT_CONST(19)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_FIELD                     _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_RANGE                     _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_ROW                       0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_SHIFT                  _MK_SHIFT_CONST(20)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_FIELD                  _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_RANGE                  _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_ROW                    0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_SHIFT                  _MK_SHIFT_CONST(21)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_FIELD                  _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_RANGE                  _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_ROW                    0

#define SLICE8_ICTLR_FIELDS_0_GPMU_SHIFT                        _MK_SHIFT_CONST(22)
#define SLICE8_ICTLR_FIELDS_0_GPMU_FIELD                        _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_GPMU_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_GPMU_RANGE                        _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
#define SLICE8_ICTLR_FIELDS_0_GPMU_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_AOTAG_INTR_SHIFT                  _MK_SHIFT_CONST(23)
#define SLICE8_ICTLR_FIELDS_0_AOTAG_INTR_FIELD                  _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_AOTAG_INTR_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_AOTAG_INTR_RANGE                  _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
#define SLICE8_ICTLR_FIELDS_0_AOTAG_INTR_ROW                    0

#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_SHIFT                  _MK_SHIFT_CONST(24)
#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_FIELD                  _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_VFMON_INTR_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_RANGE                  _MK_SHIFT_CONST(24):_MK_SHIFT_CONST(24)
#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_ROW                    0

#define SLICE8_ICTLR_FIELDS_0_SE_APB_SHIFT                      _MK_SHIFT_CONST(25)
#define SLICE8_ICTLR_FIELDS_0_SE_APB_FIELD                      _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SE_APB_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SE_APB_RANGE                      _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(25)
#define SLICE8_ICTLR_FIELDS_0_SE_APB_ROW                        0

#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_SHIFT                   _MK_SHIFT_CONST(26)
#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_FIELD                   _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SE_HOST1X_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_RANGE                   _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_SE_ELPPKA_SHIFT                   _MK_SHIFT_CONST(27)
#define SLICE8_ICTLR_FIELDS_0_SE_ELPPKA_FIELD                   _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SE_ELPPKA_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SE_ELPPKA_RANGE                   _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
#define SLICE8_ICTLR_FIELDS_0_SE_ELPPKA_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_SHIFT                   _MK_SHIFT_CONST(28)
#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_FIELD                   _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_RANGE                   _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_SCE_PM_SHIFT                      _MK_SHIFT_CONST(29)
#define SLICE8_ICTLR_FIELDS_0_SCE_PM_FIELD                      _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SCE_PM_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SCE_PM_RANGE                      _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
#define SLICE8_ICTLR_FIELDS_0_SCE_PM_ROW                        0

#define SLICE8_ICTLR_FIELDS_0_NV_ADDRESS_MAP_LIC_286_INTR_NAME_SHIFT                    _MK_SHIFT_CONST(30)
#define SLICE8_ICTLR_FIELDS_0_NV_ADDRESS_MAP_LIC_286_INTR_NAME_FIELD                    _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_NV_ADDRESS_MAP_LIC_286_INTR_NAME_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_NV_ADDRESS_MAP_LIC_286_INTR_NAME_RANGE                    _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
#define SLICE8_ICTLR_FIELDS_0_NV_ADDRESS_MAP_LIC_286_INTR_NAME_ROW                      0

#define SLICE8_ICTLR_FIELDS_0_NV_ADDRESS_MAP_LIC_287_INTR_NAME_SHIFT                    _MK_SHIFT_CONST(31)
#define SLICE8_ICTLR_FIELDS_0_NV_ADDRESS_MAP_LIC_287_INTR_NAME_FIELD                    _MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_NV_ADDRESS_MAP_LIC_287_INTR_NAME_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_NV_ADDRESS_MAP_LIC_287_INTR_NAME_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
#define SLICE8_ICTLR_FIELDS_0_NV_ADDRESS_MAP_LIC_287_INTR_NAME_ROW                      0


//
// REGISTER LIST
//
#define LIST_ARINTR_CTLR_REGS(_op_) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0) \
_op_(INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0) \
_op_(INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0) \
_op_(INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0) \
_op_(INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0) \
_op_(INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0) \
_op_(INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0) \
_op_(INTR_CTLR_COMMON_SLICE0_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE0_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE0_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE0_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE0_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE0_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE1_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE1_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE1_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE1_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE1_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE1_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE2_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE2_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE2_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE2_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE2_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE2_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE3_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE3_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE3_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE3_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE3_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE3_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE4_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE4_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE4_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE4_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE4_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE4_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE5_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE5_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE5_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE5_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE5_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE5_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE6_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE6_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE6_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE6_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE6_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE6_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE7_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE7_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE7_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE7_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE7_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE7_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE8_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE8_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE8_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE8_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE8_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE8_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_CTRL_0) \
_op_(INTR_CTLR_COMMON_SCR_SCR_COMMON_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_INTR_CTLR  0x00000000
#define BASE_ADDRESS_INTR_CTLR_CHANNEL0 0x00000000
#define BASE_ADDRESS_INTR_CTLR_CHANNEL0_SCR     0x000007c0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL1 0x00000800
#define BASE_ADDRESS_INTR_CTLR_CHANNEL1_SCR     0x00000fc0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL2 0x00001000
#define BASE_ADDRESS_INTR_CTLR_CHANNEL2_SCR     0x000017c0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL3 0x00001800
#define BASE_ADDRESS_INTR_CTLR_CHANNEL3_SCR     0x00001fc0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL4 0x00002000
#define BASE_ADDRESS_INTR_CTLR_CHANNEL4_SCR     0x000027c0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL5 0x00002800
#define BASE_ADDRESS_INTR_CTLR_CHANNEL5_SCR     0x00002fc0
#define BASE_ADDRESS_INTR_CTLR_COMMON   0x0000f800
#define BASE_ADDRESS_INTR_CTLR_COMMON_SCR       0x0000ffc4

//
// ARINTR_CTLR REGISTER BANKS
//

#define INTR_CTLR_CHANNEL00_FIRST_REG 0x0000 // INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL00_LAST_REG 0x0024 // INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL01_FIRST_REG 0x0040 // INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL01_LAST_REG 0x0064 // INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL02_FIRST_REG 0x0080 // INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL02_LAST_REG 0x00a4 // INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL03_FIRST_REG 0x00c0 // INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL03_LAST_REG 0x00e4 // INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL04_FIRST_REG 0x0100 // INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL04_LAST_REG 0x0124 // INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL05_FIRST_REG 0x0140 // INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL05_LAST_REG 0x0164 // INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL06_FIRST_REG 0x0180 // INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL06_LAST_REG 0x01a4 // INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL07_FIRST_REG 0x01c0 // INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL07_LAST_REG 0x01e4 // INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL08_FIRST_REG 0x0200 // INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL08_LAST_REG 0x0224 // INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SCR0_FIRST_REG 0x07c0 // INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SCR0_LAST_REG 0x07c4 // INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL10_FIRST_REG 0x0800 // INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL10_LAST_REG 0x0824 // INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_FIRST_REG 0x0840 // INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL11_LAST_REG 0x0864 // INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL12_FIRST_REG 0x0880 // INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL12_LAST_REG 0x08a4 // INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL13_FIRST_REG 0x08c0 // INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL13_LAST_REG 0x08e4 // INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL14_FIRST_REG 0x0900 // INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL14_LAST_REG 0x0924 // INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL15_FIRST_REG 0x0940 // INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL15_LAST_REG 0x0964 // INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL16_FIRST_REG 0x0980 // INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL16_LAST_REG 0x09a4 // INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL17_FIRST_REG 0x09c0 // INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL17_LAST_REG 0x09e4 // INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL18_FIRST_REG 0x0a00 // INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL18_LAST_REG 0x0a24 // INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SCR0_FIRST_REG 0x0fc0 // INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SCR0_LAST_REG 0x0fc4 // INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL20_FIRST_REG 0x1000 // INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL20_LAST_REG 0x1024 // INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL21_FIRST_REG 0x1040 // INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL21_LAST_REG 0x1064 // INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL22_FIRST_REG 0x1080 // INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL22_LAST_REG 0x10a4 // INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL23_FIRST_REG 0x10c0 // INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL23_LAST_REG 0x10e4 // INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL24_FIRST_REG 0x1100 // INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL24_LAST_REG 0x1124 // INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL25_FIRST_REG 0x1140 // INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL25_LAST_REG 0x1164 // INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL26_FIRST_REG 0x1180 // INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL26_LAST_REG 0x11a4 // INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL27_FIRST_REG 0x11c0 // INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL27_LAST_REG 0x11e4 // INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL28_FIRST_REG 0x1200 // INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL28_LAST_REG 0x1224 // INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SCR0_FIRST_REG 0x17c0 // INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SCR0_LAST_REG 0x17c4 // INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL30_FIRST_REG 0x1800 // INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL30_LAST_REG 0x1824 // INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL31_FIRST_REG 0x1840 // INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL31_LAST_REG 0x1864 // INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL32_FIRST_REG 0x1880 // INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL32_LAST_REG 0x18a4 // INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL33_FIRST_REG 0x18c0 // INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL33_LAST_REG 0x18e4 // INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL34_FIRST_REG 0x1900 // INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL34_LAST_REG 0x1924 // INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL35_FIRST_REG 0x1940 // INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL35_LAST_REG 0x1964 // INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL36_FIRST_REG 0x1980 // INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL36_LAST_REG 0x19a4 // INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL37_FIRST_REG 0x19c0 // INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL37_LAST_REG 0x19e4 // INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL38_FIRST_REG 0x1a00 // INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL38_LAST_REG 0x1a24 // INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SCR0_FIRST_REG 0x1fc0 // INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SCR0_LAST_REG 0x1fc4 // INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL40_FIRST_REG 0x2000 // INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL40_LAST_REG 0x2024 // INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL41_FIRST_REG 0x2040 // INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL41_LAST_REG 0x2064 // INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL42_FIRST_REG 0x2080 // INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL42_LAST_REG 0x20a4 // INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL43_FIRST_REG 0x20c0 // INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL43_LAST_REG 0x20e4 // INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL44_FIRST_REG 0x2100 // INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL44_LAST_REG 0x2124 // INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL45_FIRST_REG 0x2140 // INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL45_LAST_REG 0x2164 // INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL46_FIRST_REG 0x2180 // INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL46_LAST_REG 0x21a4 // INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL47_FIRST_REG 0x21c0 // INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL47_LAST_REG 0x21e4 // INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL48_FIRST_REG 0x2200 // INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL48_LAST_REG 0x2224 // INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SCR0_FIRST_REG 0x27c0 // INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SCR0_LAST_REG 0x27c4 // INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL50_FIRST_REG 0x2800 // INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL50_LAST_REG 0x2824 // INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL51_FIRST_REG 0x2840 // INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL51_LAST_REG 0x2864 // INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL52_FIRST_REG 0x2880 // INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL52_LAST_REG 0x28a4 // INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL53_FIRST_REG 0x28c0 // INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL53_LAST_REG 0x28e4 // INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL54_FIRST_REG 0x2900 // INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL54_LAST_REG 0x2924 // INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL55_FIRST_REG 0x2940 // INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL55_LAST_REG 0x2964 // INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL56_FIRST_REG 0x2980 // INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL56_LAST_REG 0x29a4 // INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL57_FIRST_REG 0x29c0 // INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL57_LAST_REG 0x29e4 // INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL58_FIRST_REG 0x2a00 // INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL58_LAST_REG 0x2a24 // INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SCR0_FIRST_REG 0x2fc0 // INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SCR0_LAST_REG 0x2fc4 // INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_COMMON0_FIRST_REG 0xf800 // INTR_CTLR_COMMON_SLICE0_GISR_0
#define INTR_CTLR_COMMON0_LAST_REG 0xf818 // INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0
#define INTR_CTLR_COMMON1_FIRST_REG 0xf840 // INTR_CTLR_COMMON_SLICE1_GISR_0
#define INTR_CTLR_COMMON1_LAST_REG 0xf858 // INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0
#define INTR_CTLR_COMMON2_FIRST_REG 0xf880 // INTR_CTLR_COMMON_SLICE2_GISR_0
#define INTR_CTLR_COMMON2_LAST_REG 0xf898 // INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0
#define INTR_CTLR_COMMON3_FIRST_REG 0xf8c0 // INTR_CTLR_COMMON_SLICE3_GISR_0
#define INTR_CTLR_COMMON3_LAST_REG 0xf8d8 // INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0
#define INTR_CTLR_COMMON4_FIRST_REG 0xf900 // INTR_CTLR_COMMON_SLICE4_GISR_0
#define INTR_CTLR_COMMON4_LAST_REG 0xf918 // INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0
#define INTR_CTLR_COMMON5_FIRST_REG 0xf940 // INTR_CTLR_COMMON_SLICE5_GISR_0
#define INTR_CTLR_COMMON5_LAST_REG 0xf958 // INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0
#define INTR_CTLR_COMMON6_FIRST_REG 0xf980 // INTR_CTLR_COMMON_SLICE6_GISR_0
#define INTR_CTLR_COMMON6_LAST_REG 0xf998 // INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0
#define INTR_CTLR_COMMON7_FIRST_REG 0xf9c0 // INTR_CTLR_COMMON_SLICE7_GISR_0
#define INTR_CTLR_COMMON7_LAST_REG 0xf9d8 // INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0
#define INTR_CTLR_COMMON8_FIRST_REG 0xfa00 // INTR_CTLR_COMMON_SLICE8_GISR_0
#define INTR_CTLR_COMMON8_LAST_REG 0xfa18 // INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0
#define INTR_CTLR_COMMON9_FIRST_REG 0xffc0 // INTR_CTLR_COMMON_CTRL_0
#define INTR_CTLR_COMMON9_LAST_REG 0xffc0 // INTR_CTLR_COMMON_CTRL_0
#define INTR_CTLR_COMMON_SCR0_FIRST_REG 0xffc4 // INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SCR0_LAST_REG 0xffc4 // INTR_CTLR_COMMON_SCR_SCR_COMMON_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARINTR_CTLR_H_INC_
