//
// Copyright (c) 2015 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//  * Redistributions of source code must retain the above copyright
//    notice, this list of conditions and the following disclaimer.
//  * Redistributions in binary form must reproduce the above copyright
//    notice, this list of conditions and the following disclaimer in the
//    documentation and/or other materials provided with the distribution.
//  * Neither the name of NVIDIA CORPORATION nor the names of its
//    contributors may be used to endorse or promote products derived
//    from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARXUSB_PADCTL_H_INC_
#define ___ARXUSB_PADCTL_H_INC_

// Register XUSB_PADCTL_BOOT_MEDIA_0
#define XUSB_PADCTL_BOOT_MEDIA_0                        _MK_ADDR_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_SECURE                         0x0
#define XUSB_PADCTL_BOOT_MEDIA_0_SCR                    0
#define XUSB_PADCTL_BOOT_MEDIA_0_WORD_COUNT                     0x1
#define XUSB_PADCTL_BOOT_MEDIA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_BOOT_MEDIA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_READ_MASK                      _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_BOOT_MEDIA_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_SHIFT)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_RANGE                        0:0
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_WOFFSET                      0x0
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_SHIFT                        _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_SHIFT)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_RANGE                        4:1
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_WOFFSET                      0x0
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG0                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG1                    _MK_ENUM_CONST(1)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG2                    _MK_ENUM_CONST(2)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG3                    _MK_ENUM_CONST(3)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG4                    _MK_ENUM_CONST(4)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG5                    _MK_ENUM_CONST(5)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG6                    _MK_ENUM_CONST(6)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_HSIC0                        _MK_ENUM_CONST(9)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_HSIC1                        _MK_ENUM_CONST(10)


// Register XUSB_PADCTL_USB2_PAD_MUX_0
#define XUSB_PADCTL_USB2_PAD_MUX_0                      _MK_ADDR_CONST(0x4)
#define XUSB_PADCTL_USB2_PAD_MUX_0_SECURE                       0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_SCR                  0
#define XUSB_PADCTL_USB2_PAD_MUX_0_WORD_COUNT                   0x1
#define XUSB_PADCTL_USB2_PAD_MUX_0_RESET_VAL                    _MK_MASK_CONST(0x55)
#define XUSB_PADCTL_USB2_PAD_MUX_0_RESET_MASK                   _MK_MASK_CONST(0x3000ff)
#define XUSB_PADCTL_USB2_PAD_MUX_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_READ_MASK                    _MK_MASK_CONST(0x3000ff)
#define XUSB_PADCTL_USB2_PAD_MUX_0_WRITE_MASK                   _MK_MASK_CONST(0x3000ff)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_SHIFT)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_RANGE                     1:0
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_XUSB                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_UART                      _MK_ENUM_CONST(2)

#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_SHIFT)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_RANGE                     3:2
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_XUSB                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_UART                      _MK_ENUM_CONST(2)

#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_SHIFT)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_RANGE                     5:4
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_XUSB                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_UART                      _MK_ENUM_CONST(2)

#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_SHIFT)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_RANGE                     7:6
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_XUSB                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_UART                      _MK_ENUM_CONST(2)

#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT0_CONFIG_SHIFT                      _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT0_CONFIG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT0_CONFIG_SHIFT)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT0_CONFIG_RANGE                      20:20
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT0_CONFIG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT0_CONFIG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT0_CONFIG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT0_CONFIG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT0_CONFIG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT0_CONFIG_HSIC                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT0_CONFIG_HSIC_PLUS                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT1_CONFIG_SHIFT                      _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT1_CONFIG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT1_CONFIG_SHIFT)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT1_CONFIG_RANGE                      21:21
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT1_CONFIG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT1_CONFIG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT1_CONFIG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT1_CONFIG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT1_CONFIG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT1_CONFIG_HSIC                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_HSIC_PORT1_CONFIG_HSIC_PLUS                  _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_PORT_CAP_0
#define XUSB_PADCTL_USB2_PORT_CAP_0                     _MK_ADDR_CONST(0x8)
#define XUSB_PADCTL_USB2_PORT_CAP_0_SECURE                      0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_SCR                         0
#define XUSB_PADCTL_USB2_PORT_CAP_0_WORD_COUNT                  0x1
#define XUSB_PADCTL_USB2_PORT_CAP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_PORT_CAP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_PORT_CAP_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_RANGE                     1:0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_DISABLED                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_HOST_ONLY                 _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_DEVICE_ONLY                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_OTG_CAP                   _MK_ENUM_CONST(3)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_SHIFT                        _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_RANGE                        2:2
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_SHIFT                      _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_RANGE                      3:3
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_RANGE                     5:4
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_DISABLED                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_HOST_ONLY                 _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_DEVICE_ONLY                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_OTG_CAP                   _MK_ENUM_CONST(3)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_SHIFT                        _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_RANGE                        6:6
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_SHIFT                      _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_RANGE                      7:7
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_SHIFT                     _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_RANGE                     9:8
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_DISABLED                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_HOST_ONLY                 _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_DEVICE_ONLY                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_OTG_CAP                   _MK_ENUM_CONST(3)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_SHIFT                        _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_RANGE                        10:10
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_RANGE                      11:11
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_SHIFT                     _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_RANGE                     13:12
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_DISABLED                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_HOST_ONLY                 _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_DEVICE_ONLY                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_OTG_CAP                   _MK_ENUM_CONST(3)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_SHIFT                        _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_RANGE                        14:14
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_SHIFT                      _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_RANGE                      15:15
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_YES                        _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_SS_PORT_CAP_0
#define XUSB_PADCTL_SS_PORT_CAP_0                       _MK_ADDR_CONST(0xc)
#define XUSB_PADCTL_SS_PORT_CAP_0_SECURE                        0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_SCR                   0
#define XUSB_PADCTL_SS_PORT_CAP_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_SS_PORT_CAP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_PORT_CAP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_PORT_CAP_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_RANGE                       1:0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_WOFFSET                     0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_DISABLED                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_HOST_ONLY                   _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_DEVICE_ONLY                 _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_OTG_CAP                     _MK_ENUM_CONST(3)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_SHIFT                  _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_RANGE                  2:2
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_WOFFSET                        0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_RANGE                        3:3
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_WOFFSET                      0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_RANGE                       5:4
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_WOFFSET                     0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_DISABLED                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_HOST_ONLY                   _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_DEVICE_ONLY                 _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_OTG_CAP                     _MK_ENUM_CONST(3)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_SHIFT                  _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_RANGE                  6:6
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_WOFFSET                        0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_RANGE                        7:7
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_WOFFSET                      0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_SHIFT                       _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_RANGE                       9:8
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_WOFFSET                     0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_DISABLED                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_HOST_ONLY                   _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_DEVICE_ONLY                 _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_OTG_CAP                     _MK_ENUM_CONST(3)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_SHIFT                  _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_RANGE                  10:10
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_WOFFSET                        0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_SHIFT                        _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_RANGE                        11:11
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_WOFFSET                      0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_SHIFT                       _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_RANGE                       13:12
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_WOFFSET                     0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_DISABLED                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_HOST_ONLY                   _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_DEVICE_ONLY                 _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_OTG_CAP                     _MK_ENUM_CONST(3)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_SHIFT                  _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_RANGE                  14:14
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_WOFFSET                        0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_RANGE                        15:15
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_WOFFSET                      0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_YES                  _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_OC_MAP_0
#define XUSB_PADCTL_USB2_OC_MAP_0                       _MK_ADDR_CONST(0x10)
#define XUSB_PADCTL_USB2_OC_MAP_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OC_MAP_0_SCR                   0
#define XUSB_PADCTL_USB2_OC_MAP_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OC_MAP_0_RESET_VAL                     _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_OC_MAP_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_OC_MAP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_OC_MAP_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_SHIFT)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_RANGE                    3:0
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_DEFAULT                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED0                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED1                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED2                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED3                     _MK_ENUM_CONST(3)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD0                    _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD1                    _MK_ENUM_CONST(5)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD2                    _MK_ENUM_CONST(6)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD3                    _MK_ENUM_CONST(7)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTION_DISABLED                    _MK_ENUM_CONST(15)

#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_SHIFT                    _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_SHIFT)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_RANGE                    7:4
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_DEFAULT                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED0                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED1                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED2                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED3                     _MK_ENUM_CONST(3)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD0                    _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD1                    _MK_ENUM_CONST(5)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD2                    _MK_ENUM_CONST(6)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD3                    _MK_ENUM_CONST(7)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTION_DISABLED                    _MK_ENUM_CONST(15)

#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_SHIFT                    _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_SHIFT)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_RANGE                    11:8
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_DEFAULT                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED0                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED1                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED2                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED3                     _MK_ENUM_CONST(3)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD0                    _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD1                    _MK_ENUM_CONST(5)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD2                    _MK_ENUM_CONST(6)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD3                    _MK_ENUM_CONST(7)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTION_DISABLED                    _MK_ENUM_CONST(15)

#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_SHIFT)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_RANGE                    15:12
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_DEFAULT                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED0                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED1                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED2                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED3                     _MK_ENUM_CONST(3)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD0                    _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD1                    _MK_ENUM_CONST(5)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD2                    _MK_ENUM_CONST(6)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD3                    _MK_ENUM_CONST(7)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTION_DISABLED                    _MK_ENUM_CONST(15)


// Register XUSB_PADCTL_SS_OC_MAP_0
#define XUSB_PADCTL_SS_OC_MAP_0                 _MK_ADDR_CONST(0x14)
#define XUSB_PADCTL_SS_OC_MAP_0_SECURE                  0x0
#define XUSB_PADCTL_SS_OC_MAP_0_SCR                     0
#define XUSB_PADCTL_SS_OC_MAP_0_WORD_COUNT                      0x1
#define XUSB_PADCTL_SS_OC_MAP_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_OC_MAP_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_OC_MAP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_OC_MAP_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_FIELD                      _MK_FIELD_CONST(0xf, XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_SHIFT)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_RANGE                      3:0
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_WOFFSET                    0x0
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_DEFAULT                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED0                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED1                       _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED2                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED3                       _MK_ENUM_CONST(3)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD0                      _MK_ENUM_CONST(4)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD1                      _MK_ENUM_CONST(5)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD2                      _MK_ENUM_CONST(6)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD3                      _MK_ENUM_CONST(7)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTION_DISABLED                      _MK_ENUM_CONST(15)

#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_SHIFT                      _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_FIELD                      _MK_FIELD_CONST(0xf, XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_SHIFT)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_RANGE                      7:4
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_WOFFSET                    0x0
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_DEFAULT                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED0                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED1                       _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED2                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED3                       _MK_ENUM_CONST(3)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD0                      _MK_ENUM_CONST(4)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD1                      _MK_ENUM_CONST(5)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD2                      _MK_ENUM_CONST(6)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD3                      _MK_ENUM_CONST(7)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTION_DISABLED                      _MK_ENUM_CONST(15)

#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_SHIFT                      _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_FIELD                      _MK_FIELD_CONST(0xf, XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_SHIFT)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_RANGE                      11:8
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_WOFFSET                    0x0
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_DEFAULT                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED0                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED1                       _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED2                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED3                       _MK_ENUM_CONST(3)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD0                      _MK_ENUM_CONST(4)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD1                      _MK_ENUM_CONST(5)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD2                      _MK_ENUM_CONST(6)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD3                      _MK_ENUM_CONST(7)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTION_DISABLED                      _MK_ENUM_CONST(15)

#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_SHIFT                      _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_FIELD                      _MK_FIELD_CONST(0xf, XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_SHIFT)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_RANGE                      15:12
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_WOFFSET                    0x0
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_DEFAULT                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED0                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED1                       _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED2                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED3                       _MK_ENUM_CONST(3)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD0                      _MK_ENUM_CONST(4)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD1                      _MK_ENUM_CONST(5)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD2                      _MK_ENUM_CONST(6)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD3                      _MK_ENUM_CONST(7)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTION_DISABLED                      _MK_ENUM_CONST(15)


// Register XUSB_PADCTL_VBUS_OC_MAP_0
#define XUSB_PADCTL_VBUS_OC_MAP_0                       _MK_ADDR_CONST(0x18)
#define XUSB_PADCTL_VBUS_OC_MAP_0_SECURE                        0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_SCR                   0
#define XUSB_PADCTL_VBUS_OC_MAP_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_VBUS_OC_MAP_0_RESET_VAL                     _MK_MASK_CONST(0xf7bde)
#define XUSB_PADCTL_VBUS_OC_MAP_0_RESET_MASK                    _MK_MASK_CONST(0xfffff)
#define XUSB_PADCTL_VBUS_OC_MAP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_READ_MASK                     _MK_MASK_CONST(0xfffff)
#define XUSB_PADCTL_VBUS_OC_MAP_0_WRITE_MASK                    _MK_MASK_CONST(0xfffff)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_RANGE                    0:0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_WOFFSET                  0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_FIELD                     _MK_FIELD_CONST(0xf, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_RANGE                     4:1
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_WOFFSET                   0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_DEFAULT                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED0                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED1                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED2                      _MK_ENUM_CONST(2)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED3                      _MK_ENUM_CONST(3)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED_VBUS_PAD0                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED_VBUS_PAD1                     _MK_ENUM_CONST(5)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED_VBUS_PAD2                     _MK_ENUM_CONST(6)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED_VBUS_PAD3                     _MK_ENUM_CONST(7)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTION_DISABLED                     _MK_ENUM_CONST(15)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_SHIFT                    _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_RANGE                    5:5
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_WOFFSET                  0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_FIELD                     _MK_FIELD_CONST(0xf, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_RANGE                     9:6
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_WOFFSET                   0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_DEFAULT                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED0                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED1                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED2                      _MK_ENUM_CONST(2)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED3                      _MK_ENUM_CONST(3)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED_VBUS_PAD0                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED_VBUS_PAD1                     _MK_ENUM_CONST(5)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED_VBUS_PAD2                     _MK_ENUM_CONST(6)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED_VBUS_PAD3                     _MK_ENUM_CONST(7)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTION_DISABLED                     _MK_ENUM_CONST(15)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_SHIFT                    _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_RANGE                    10:10
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_WOFFSET                  0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_FIELD                     _MK_FIELD_CONST(0xf, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_RANGE                     14:11
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_WOFFSET                   0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_DEFAULT                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED0                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED1                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED2                      _MK_ENUM_CONST(2)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED3                      _MK_ENUM_CONST(3)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED_VBUS_PAD0                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED_VBUS_PAD1                     _MK_ENUM_CONST(5)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED_VBUS_PAD2                     _MK_ENUM_CONST(6)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED_VBUS_PAD3                     _MK_ENUM_CONST(7)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTION_DISABLED                     _MK_ENUM_CONST(15)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_SHIFT                    _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_RANGE                    15:15
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_WOFFSET                  0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_SHIFT                     _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_FIELD                     _MK_FIELD_CONST(0xf, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_RANGE                     19:16
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_WOFFSET                   0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_DEFAULT                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED0                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED1                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED2                      _MK_ENUM_CONST(2)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED3                      _MK_ENUM_CONST(3)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED_VBUS_PAD0                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED_VBUS_PAD1                     _MK_ENUM_CONST(5)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED_VBUS_PAD2                     _MK_ENUM_CONST(6)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED_VBUS_PAD3                     _MK_ENUM_CONST(7)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTION_DISABLED                     _MK_ENUM_CONST(15)


// Register XUSB_PADCTL_OC_DET_0
#define XUSB_PADCTL_OC_DET_0                    _MK_ADDR_CONST(0x1c)
#define XUSB_PADCTL_OC_DET_0_SECURE                     0x0
#define XUSB_PADCTL_OC_DET_0_SCR                        0
#define XUSB_PADCTL_OC_DET_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_OC_DET_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_RESET_MASK                         _MK_MASK_CONST(0xff0ff0f)
#define XUSB_PADCTL_OC_DET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_READ_MASK                  _MK_MASK_CONST(0xff0ff0f)
#define XUSB_PADCTL_OC_DET_0_WRITE_MASK                         _MK_MASK_CONST(0xff0ff0f)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_SHIFT)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_RANGE                     0:0
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_WOFFSET                   0x0
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_SHIFT)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_RANGE                     1:1
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_WOFFSET                   0x0
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_SHIFT)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_RANGE                     2:2
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_WOFFSET                   0x0
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_SHIFT                     _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_SHIFT)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_RANGE                     3:3
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_WOFFSET                   0x0
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_SHIFT                 _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED0_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_RANGE                 8:8
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_WOFFSET                       0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED1_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_RANGE                 9:9
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_WOFFSET                       0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_SHIFT                 _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED2_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_RANGE                 10:10
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_WOFFSET                       0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_SHIFT                 _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED3_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_RANGE                 11:11
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_WOFFSET                       0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_SHIFT                        _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_RANGE                        12:12
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_SHIFT                        _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_RANGE                        13:13
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_SHIFT                        _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_RANGE                        14:14
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_RANGE                        15:15
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_SHIFT                        _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_RANGE                        20:20
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_RANGE                        21:21
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_SHIFT                        _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_RANGE                        22:22
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_SHIFT                        _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_RANGE                        23:23
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_SHIFT                        _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_RANGE                        24:24
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_RANGE                        25:25
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_SHIFT                        _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_RANGE                        26:26
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_SHIFT                        _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_RANGE                        27:27
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_YES                  _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_ELPG_PROGRAM_0_0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0                    _MK_ADDR_CONST(0x20)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SECURE                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SCR                        0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_RESET_MASK                         _MK_MASK_CONST(0xf1e3c78f)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_READ_MASK                  _MK_MASK_CONST(0xf1e3c78f)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_WRITE_MASK                         _MK_MASK_CONST(0xf1e3c78f)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_RANGE                     0:0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_RANGE                     1:1
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_RANGE                     2:2
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_SHIFT                     _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_RANGE                     3:3
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_SHIFT                      _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_RANGE                      7:7
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_WOFFSET                    0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_SHIFT                      _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_RANGE                      8:8
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_WOFFSET                    0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_SHIFT                      _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_RANGE                      9:9
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_WOFFSET                    0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_SHIFT                      _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_RANGE                      10:10
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_WOFFSET                    0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_SHIFT                       _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_RANGE                       14:14
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_WOFFSET                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_SHIFT                       _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_RANGE                       15:15
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_WOFFSET                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_RANGE                       16:16
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_WOFFSET                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_SHIFT                       _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_RANGE                       17:17
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_WOFFSET                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_RANGE                        21:21
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_WOFFSET                      0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_SHIFT                        _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_RANGE                        22:22
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_WOFFSET                      0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_SHIFT                        _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_RANGE                        23:23
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_WOFFSET                      0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_SHIFT                        _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_RANGE                        24:24
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_WOFFSET                      0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE_RANGE                        28:28
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE_WOFFSET                      0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE_SHIFT                        _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE_RANGE                        29:29
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE_WOFFSET                      0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKEUP_EVENT_SHIFT                 _MK_SHIFT_CONST(30)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKEUP_EVENT_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKEUP_EVENT_RANGE                 30:30
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKEUP_EVENT_WOFFSET                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKEUP_EVENT_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKEUP_EVENT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKEUP_EVENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKEUP_EVENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKEUP_EVENT_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT0_WAKEUP_EVENT_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKEUP_EVENT_SHIFT                 _MK_SHIFT_CONST(31)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKEUP_EVENT_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKEUP_EVENT_RANGE                 31:31
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKEUP_EVENT_WOFFSET                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKEUP_EVENT_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKEUP_EVENT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKEUP_EVENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKEUP_EVENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKEUP_EVENT_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_HSIC_PORT1_WAKEUP_EVENT_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_ELPG_PROGRAM_1_0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0                    _MK_ADDR_CONST(0x24)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SECURE                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SCR                        0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_RESET_VAL                  _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_RESET_MASK                         _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_READ_MASK                  _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_WRITE_MASK                         _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_RANGE                   0:0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_WOFFSET                 0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_RANGE                     1:1
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_RANGE                 2:2
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_WOFFSET                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_SHIFT                   _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_RANGE                   3:3
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_WOFFSET                 0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_RANGE                     4:4
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_SHIFT                 _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_RANGE                 5:5
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_WOFFSET                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_SHIFT                   _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_RANGE                   6:6
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_WOFFSET                 0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_SHIFT                     _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_RANGE                     7:7
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_SHIFT                 _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_RANGE                 8:8
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_WOFFSET                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_SHIFT                   _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_RANGE                   9:9
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_WOFFSET                 0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_SHIFT                     _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_RANGE                     10:10
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_SHIFT                 _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_RANGE                 11:11
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_WOFFSET                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_PM_SPARE_0
#define XUSB_PADCTL_PM_SPARE_0                  _MK_ADDR_CONST(0x28)
#define XUSB_PADCTL_PM_SPARE_0_SECURE                   0x0
#define XUSB_PADCTL_PM_SPARE_0_SCR                      0
#define XUSB_PADCTL_PM_SPARE_0_WORD_COUNT                       0x1
#define XUSB_PADCTL_PM_SPARE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_RESET_MASK                       _MK_MASK_CONST(0xf0f)
#define XUSB_PADCTL_PM_SPARE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_READ_MASK                        _MK_MASK_CONST(0xf0f)
#define XUSB_PADCTL_PM_SPARE_0_WRITE_MASK                       _MK_MASK_CONST(0xf0f)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_RANGE                  0:0
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_WOFFSET                        0x0
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_SHIFT                  _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_RANGE                  1:1
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_WOFFSET                        0x0
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_SHIFT                  _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_RANGE                  2:2
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_WOFFSET                        0x0
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_RANGE                  3:3
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_WOFFSET                        0x0
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT0_SHIFT                 _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT0_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT0_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT0_RANGE                 8:8
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT0_WOFFSET                       0x0
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT0_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT1_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT1_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT1_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT1_RANGE                 9:9
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT1_WOFFSET                       0x0
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT1_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT2_SHIFT                 _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT2_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT2_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT2_RANGE                 10:10
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT2_WOFFSET                       0x0
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT2_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT3_SHIFT                 _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT3_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT3_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT3_RANGE                 11:11
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT3_WOFFSET                       0x0
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT3_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_HSIC_PM_SPARE_BIT3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 44 [0x2c]

// Reserved address 48 [0x30]

// Reserved address 52 [0x34]

// Reserved address 56 [0x38]

// Reserved address 60 [0x3c]

// Reserved address 64 [0x40]

// Reserved address 68 [0x44]

// Reserved address 72 [0x48]

// Reserved address 76 [0x4c]

// Reserved address 80 [0x50]

// Reserved address 84 [0x54]

// Reserved address 88 [0x58]

// Reserved address 92 [0x5c]

// Reserved address 96 [0x60]

// Reserved address 100 [0x64]

// Reserved address 104 [0x68]

// Reserved address 108 [0x6c]

// Reserved address 112 [0x70]

// Reserved address 116 [0x74]

// Reserved address 120 [0x78]

// Reserved address 124 [0x7c]

// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0                    _MK_ADDR_CONST(0x80)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_RESET_MASK                         _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_READ_MASK                  _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_WRITE_MASK                         _MK_MASK_CONST(0xffb83fdd)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_RANGE                     1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_RANGE                     2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_RANGE                        3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_SHIFT                     _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_RANGE                     5:5
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_RANGE                     6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_RANGE                        7:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_RANGE                   8:8
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_RANGE                   9:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_RANGE                    10:10
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_RANGE                   11:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_RANGE                    12:12
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_SHIFT                  _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_RANGE                  13:13
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_RANGE                  18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_RANGE                  19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_RANGE                     20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_RANGE                        21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_SHIFT                  _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_RANGE                  22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_RANGE                  23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_RANGE                     24:24
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_RANGE                        25:25
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_SHIFT                 _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_RANGE                 26:26
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_SHIFT                  _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_RANGE                  27:27
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_RANGE                        28:28
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_SHIFT                 _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_RANGE                 29:29
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_SHIFT                  _MK_SHIFT_CONST(30)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_RANGE                  30:30
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_SHIFT                 _MK_SHIFT_CONST(31)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_RANGE                 31:31
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0                    _MK_ADDR_CONST(0x84)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_RESET_MASK                         _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_READ_MASK                  _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_WRITE_MASK                         _MK_MASK_CONST(0xff1fd0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_RANGE                       1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_RANGE                       2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_RANGE                       3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_SHIFT                      _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_RANGE                      6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_SHIFT                     _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_RANGE                     8:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_FIELD                 _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_RANGE                 10:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_RANGE                     12:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_RANGE                       16:16
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_RANGE                   17:17
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_RANGE                       18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_RANGE                   19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_RANGE                       20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_RANGE                   21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_RANGE                       22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_RANGE                   23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0                       _MK_ADDR_CONST(0x88)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_RESET_VAL                     _MK_MASK_CONST(0x248888e0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_RANGE                   5:0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_DEFAULT                 _MK_MASK_CONST(0x20)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_DEFAULT                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_RANGE                        12:9
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_SHIFT                        _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_RANGE                        16:13
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_SHIFT                        _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_RANGE                        20:17
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_RANGE                        24:21
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_RANGE                        25:25
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_SHIFT                      _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_RANGE                      26:26
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_SHIFT                     _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_RANGE                     27:27
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_RANGE                     28:28
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_SHIFT                   _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_RANGE                   29:29
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0                       _MK_ADDR_CONST(0x8c)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RESET_VAL                     _MK_MASK_CONST(0x101044)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RESET_MASK                    _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_READ_MASK                     _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_WRITE_MASK                    _MK_MASK_CONST(0x7dff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_RANGE                    0:0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_SHIFT                    _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_RANGE                    1:1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_SHIFT                   _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_RANGE                   2:2
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_FIELD                  _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_RANGE                  6:3
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_DEFAULT                        _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_SHIFT                   _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_RANGE                   10:7
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_FIELD                      _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_RANGE                      12:11
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_DEFAULT                    _MK_MASK_CONST(0x2)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_RANGE                        15:15
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_RANGE                        16:16
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_SHIFT                 _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_FIELD                 _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_RANGE                 20:17
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT                       _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_RANGE                     21:21
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_RANGE                    22:22
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_SHIFT                 _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_RANGE                 23:23
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_SHIFT                  _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_RANGE                  24:24
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_SHIFT                 _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_RANGE                 25:25
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_SHIFT                        _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_FIELD                        _MK_FIELD_CONST(0x1f, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_RANGE                        30:26
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0                       _MK_ADDR_CONST(0x90)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RESET_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_READ_MASK                     _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_WRITE_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_RANGE                      0:0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_SHIFT                  _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_RANGE                  1:1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_RANGE                       9:4
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_RANGE                       15:10
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_RANGE                  16:16
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_RANGE                  17:17
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_SHIFT                        _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_FIELD                        _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_RANGE                        25:20
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_RANGE                        31:28
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0                       _MK_ADDR_CONST(0x94)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_RESET_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_READ_MASK                     _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_WRITE_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_RANGE                  0:0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_RANGE                 3:1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 152 [0x98]

// Reserved address 156 [0x9c]

// Reserved address 160 [0xa0]

// Reserved address 164 [0xa4]

// Reserved address 168 [0xa8]

// Reserved address 172 [0xac]

// Reserved address 176 [0xb0]

// Reserved address 180 [0xb4]

// Reserved address 184 [0xb8]

// Reserved address 188 [0xbc]

// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0                    _MK_ADDR_CONST(0xc0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_RESET_MASK                         _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_READ_MASK                  _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_WRITE_MASK                         _MK_MASK_CONST(0xffb83fdd)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_RANGE                     1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_RANGE                     2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_RANGE                        3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_SHIFT                     _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_RANGE                     5:5
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_RANGE                     6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_RANGE                        7:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_RANGE                   8:8
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_RANGE                   9:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_RANGE                    10:10
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_RANGE                   11:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_RANGE                    12:12
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_SHIFT                  _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_RANGE                  13:13
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_RANGE                  18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_RANGE                  19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_RANGE                     20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_RANGE                        21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_SHIFT                  _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_RANGE                  22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_RANGE                  23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_RANGE                     24:24
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_RANGE                        25:25
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_SHIFT                 _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_RANGE                 26:26
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_SHIFT                  _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_RANGE                  27:27
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_RANGE                        28:28
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_SHIFT                 _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_RANGE                 29:29
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_SHIFT                  _MK_SHIFT_CONST(30)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_RANGE                  30:30
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_SHIFT                 _MK_SHIFT_CONST(31)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_RANGE                 31:31
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0                    _MK_ADDR_CONST(0xc4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_RESET_MASK                         _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_READ_MASK                  _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_WRITE_MASK                         _MK_MASK_CONST(0xff1fd0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_RANGE                       1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_RANGE                       2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_RANGE                       3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_SHIFT                      _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_RANGE                      6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_SHIFT                     _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_RANGE                     8:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_FIELD                 _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_RANGE                 10:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_RANGE                     12:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_RANGE                       16:16
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_RANGE                   17:17
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_RANGE                       18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_RANGE                   19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_RANGE                       20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_RANGE                   21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_RANGE                       22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_RANGE                   23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0                       _MK_ADDR_CONST(0xc8)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_RESET_VAL                     _MK_MASK_CONST(0x248888e0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_RANGE                   5:0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_DEFAULT                 _MK_MASK_CONST(0x20)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_DEFAULT                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_RANGE                        12:9
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_SHIFT                        _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_RANGE                        16:13
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_SHIFT                        _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_RANGE                        20:17
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_RANGE                        24:21
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_RANGE                        25:25
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_SHIFT                      _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_RANGE                      26:26
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_SHIFT                     _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_RANGE                     27:27
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_RANGE                     28:28
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_SHIFT                   _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_RANGE                   29:29
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0                       _MK_ADDR_CONST(0xcc)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RESET_VAL                     _MK_MASK_CONST(0x101044)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RESET_MASK                    _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_READ_MASK                     _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_WRITE_MASK                    _MK_MASK_CONST(0x7dff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_RANGE                    0:0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_SHIFT                    _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_RANGE                    1:1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_SHIFT                   _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_RANGE                   2:2
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_FIELD                  _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_RANGE                  6:3
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_DEFAULT                        _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_SHIFT                   _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_RANGE                   10:7
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_FIELD                      _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_RANGE                      12:11
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_DEFAULT                    _MK_MASK_CONST(0x2)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_RANGE                        15:15
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_RANGE                        16:16
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_SHIFT                 _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_FIELD                 _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_RANGE                 20:17
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT                       _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_RANGE                     21:21
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_RANGE                    22:22
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_SHIFT                 _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_RANGE                 23:23
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_SHIFT                  _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_RANGE                  24:24
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_SHIFT                 _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_RANGE                 25:25
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_SHIFT                        _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_FIELD                        _MK_FIELD_CONST(0x1f, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_RANGE                        30:26
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0                       _MK_ADDR_CONST(0xd0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RESET_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_READ_MASK                     _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_WRITE_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_RANGE                      0:0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_SHIFT                  _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_RANGE                  1:1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_RANGE                       9:4
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_RANGE                       15:10
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_RANGE                  16:16
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_RANGE                  17:17
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_SHIFT                        _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_FIELD                        _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_RANGE                        25:20
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_RANGE                        31:28
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0                       _MK_ADDR_CONST(0xd4)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_RESET_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_READ_MASK                     _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_WRITE_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_RANGE                  0:0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_RANGE                 3:1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 216 [0xd8]

// Reserved address 220 [0xdc]

// Reserved address 224 [0xe0]

// Reserved address 228 [0xe4]

// Reserved address 232 [0xe8]

// Reserved address 236 [0xec]

// Reserved address 240 [0xf0]

// Reserved address 244 [0xf4]

// Reserved address 248 [0xf8]

// Reserved address 252 [0xfc]

// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0                    _MK_ADDR_CONST(0x100)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_RESET_MASK                         _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_READ_MASK                  _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_WRITE_MASK                         _MK_MASK_CONST(0xffb83fdd)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_RANGE                     1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_RANGE                     2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_RANGE                        3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_SHIFT                     _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_RANGE                     5:5
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_RANGE                     6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_RANGE                        7:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_RANGE                   8:8
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_RANGE                   9:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_RANGE                    10:10
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_RANGE                   11:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_RANGE                    12:12
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_SHIFT                  _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_RANGE                  13:13
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_RANGE                  18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_RANGE                  19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_RANGE                     20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_RANGE                        21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_SHIFT                  _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_RANGE                  22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_RANGE                  23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_RANGE                     24:24
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_RANGE                        25:25
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_SHIFT                 _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_RANGE                 26:26
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_SHIFT                  _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_RANGE                  27:27
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_RANGE                        28:28
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_SHIFT                 _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_RANGE                 29:29
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_SHIFT                  _MK_SHIFT_CONST(30)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_RANGE                  30:30
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_SHIFT                 _MK_SHIFT_CONST(31)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_RANGE                 31:31
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0                    _MK_ADDR_CONST(0x104)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_RESET_MASK                         _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_READ_MASK                  _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_WRITE_MASK                         _MK_MASK_CONST(0xff1fd0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_RANGE                       1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_RANGE                       2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_RANGE                       3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_SHIFT                      _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_RANGE                      6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_SHIFT                     _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_RANGE                     8:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_FIELD                 _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_RANGE                 10:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_RANGE                     12:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_RANGE                       16:16
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_RANGE                   17:17
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_RANGE                       18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_RANGE                   19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_RANGE                       20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_RANGE                   21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_RANGE                       22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_RANGE                   23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0                       _MK_ADDR_CONST(0x108)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_RESET_VAL                     _MK_MASK_CONST(0x248888e0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_RANGE                   5:0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_DEFAULT                 _MK_MASK_CONST(0x20)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_DEFAULT                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_RANGE                        12:9
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_SHIFT                        _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_RANGE                        16:13
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_SHIFT                        _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_RANGE                        20:17
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_RANGE                        24:21
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_RANGE                        25:25
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_SHIFT                      _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_RANGE                      26:26
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_SHIFT                     _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_RANGE                     27:27
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_RANGE                     28:28
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_SHIFT                   _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_RANGE                   29:29
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0                       _MK_ADDR_CONST(0x10c)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RESET_VAL                     _MK_MASK_CONST(0x101044)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RESET_MASK                    _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_READ_MASK                     _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_WRITE_MASK                    _MK_MASK_CONST(0x7dff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_RANGE                    0:0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_SHIFT                    _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_RANGE                    1:1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_SHIFT                   _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_RANGE                   2:2
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_FIELD                  _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_RANGE                  6:3
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_DEFAULT                        _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_SHIFT                   _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_RANGE                   10:7
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_FIELD                      _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_RANGE                      12:11
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_DEFAULT                    _MK_MASK_CONST(0x2)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_RANGE                        15:15
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_RANGE                        16:16
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_SHIFT                 _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_FIELD                 _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_RANGE                 20:17
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT                       _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_RANGE                     21:21
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_RANGE                    22:22
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_SHIFT                 _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_RANGE                 23:23
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_SHIFT                  _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_RANGE                  24:24
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_SHIFT                 _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_RANGE                 25:25
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_SHIFT                        _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_FIELD                        _MK_FIELD_CONST(0x1f, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_RANGE                        30:26
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0                       _MK_ADDR_CONST(0x110)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RESET_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_READ_MASK                     _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_WRITE_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_RANGE                      0:0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_SHIFT                  _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_RANGE                  1:1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_RANGE                       9:4
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_RANGE                       15:10
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_RANGE                  16:16
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_RANGE                  17:17
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_SHIFT                        _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_FIELD                        _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_RANGE                        25:20
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_RANGE                        31:28
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0                       _MK_ADDR_CONST(0x114)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_RESET_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_READ_MASK                     _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_WRITE_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_RANGE                  0:0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_RANGE                 3:1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 280 [0x118]

// Reserved address 284 [0x11c]

// Reserved address 288 [0x120]

// Reserved address 292 [0x124]

// Reserved address 296 [0x128]

// Reserved address 300 [0x12c]

// Reserved address 304 [0x130]

// Reserved address 308 [0x134]

// Reserved address 312 [0x138]

// Reserved address 316 [0x13c]

// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0                    _MK_ADDR_CONST(0x140)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_RESET_MASK                         _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_READ_MASK                  _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_WRITE_MASK                         _MK_MASK_CONST(0xffb83fdd)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_RANGE                     1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_RANGE                     2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_RANGE                        3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_SHIFT                     _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_RANGE                     5:5
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_RANGE                     6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_RANGE                        7:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_RANGE                   8:8
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_RANGE                   9:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_RANGE                    10:10
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_RANGE                   11:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_RANGE                    12:12
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_SHIFT                  _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_RANGE                  13:13
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_RANGE                  18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_RANGE                  19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_RANGE                     20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_RANGE                        21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_SHIFT                  _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_RANGE                  22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_RANGE                  23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_RANGE                     24:24
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_RANGE                        25:25
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_SHIFT                 _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_RANGE                 26:26
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_SHIFT                  _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_RANGE                  27:27
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_RANGE                        28:28
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_SHIFT                 _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_RANGE                 29:29
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_SHIFT                  _MK_SHIFT_CONST(30)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_RANGE                  30:30
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_SHIFT                 _MK_SHIFT_CONST(31)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_RANGE                 31:31
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0                    _MK_ADDR_CONST(0x144)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_RESET_MASK                         _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_READ_MASK                  _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_WRITE_MASK                         _MK_MASK_CONST(0xff1fd0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_RANGE                       1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_RANGE                       2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_RANGE                       3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_SHIFT                      _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_RANGE                      6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_SHIFT                     _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_RANGE                     8:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_FIELD                 _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_RANGE                 10:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_RANGE                     12:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_RANGE                       16:16
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_RANGE                   17:17
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_RANGE                       18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_RANGE                   19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_RANGE                       20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_RANGE                   21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_RANGE                       22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_RANGE                   23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0                       _MK_ADDR_CONST(0x148)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_RESET_VAL                     _MK_MASK_CONST(0x248888e0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_RANGE                   5:0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_DEFAULT                 _MK_MASK_CONST(0x20)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_DEFAULT                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_RANGE                        12:9
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_SHIFT                        _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_RANGE                        16:13
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_SHIFT                        _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_RANGE                        20:17
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_RANGE                        24:21
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_RANGE                        25:25
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_SHIFT                      _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_RANGE                      26:26
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_SHIFT                     _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_RANGE                     27:27
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_RANGE                     28:28
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_SHIFT                   _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_RANGE                   29:29
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0                       _MK_ADDR_CONST(0x14c)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RESET_VAL                     _MK_MASK_CONST(0x101044)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RESET_MASK                    _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_READ_MASK                     _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_WRITE_MASK                    _MK_MASK_CONST(0x7dff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_RANGE                    0:0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_SHIFT                    _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_RANGE                    1:1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_SHIFT                   _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_RANGE                   2:2
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_FIELD                  _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_RANGE                  6:3
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_DEFAULT                        _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_SHIFT                   _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_RANGE                   10:7
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_FIELD                      _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_RANGE                      12:11
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_DEFAULT                    _MK_MASK_CONST(0x2)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_RANGE                        15:15
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_RANGE                        16:16
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_SHIFT                 _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_FIELD                 _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_RANGE                 20:17
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT                       _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_RANGE                     21:21
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_RANGE                    22:22
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_SHIFT                 _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_RANGE                 23:23
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_SHIFT                  _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_RANGE                  24:24
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_SHIFT                 _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_RANGE                 25:25
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_SHIFT                        _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_FIELD                        _MK_FIELD_CONST(0x1f, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_RANGE                        30:26
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0                       _MK_ADDR_CONST(0x150)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RESET_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_READ_MASK                     _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_WRITE_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_RANGE                      0:0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_SHIFT                  _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_RANGE                  1:1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_RANGE                       9:4
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_RANGE                       15:10
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_RANGE                  16:16
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_RANGE                  17:17
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_SHIFT                        _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_FIELD                        _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_RANGE                        25:20
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_RANGE                        31:28
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0                       _MK_ADDR_CONST(0x154)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_RESET_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_READ_MASK                     _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_WRITE_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_RANGE                  0:0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_RANGE                 3:1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 344 [0x158]

// Reserved address 348 [0x15c]

// Reserved address 352 [0x160]

// Reserved address 356 [0x164]

// Reserved address 360 [0x168]

// Reserved address 364 [0x16c]

// Reserved address 368 [0x170]

// Reserved address 372 [0x174]

// Reserved address 376 [0x178]

// Reserved address 380 [0x17c]

// Reserved address 384 [0x180]

// Reserved address 388 [0x184]

// Reserved address 392 [0x188]

// Reserved address 396 [0x18c]

// Reserved address 400 [0x190]

// Reserved address 404 [0x194]

// Reserved address 408 [0x198]

// Reserved address 412 [0x19c]

// Reserved address 416 [0x1a0]

// Reserved address 420 [0x1a4]

// Reserved address 424 [0x1a8]

// Reserved address 428 [0x1ac]

// Reserved address 432 [0x1b0]

// Reserved address 436 [0x1b4]

// Reserved address 440 [0x1b8]

// Reserved address 444 [0x1bc]

// Reserved address 448 [0x1c0]

// Reserved address 452 [0x1c4]

// Reserved address 456 [0x1c8]

// Reserved address 460 [0x1cc]

// Reserved address 464 [0x1d0]

// Reserved address 468 [0x1d4]

// Reserved address 472 [0x1d8]

// Reserved address 476 [0x1dc]

// Reserved address 480 [0x1e0]

// Reserved address 484 [0x1e4]

// Reserved address 488 [0x1e8]

// Reserved address 492 [0x1ec]

// Reserved address 496 [0x1f0]

// Reserved address 500 [0x1f4]

// Reserved address 504 [0x1f8]

// Reserved address 508 [0x1fc]

// Reserved address 512 [0x200]

// Reserved address 516 [0x204]

// Reserved address 520 [0x208]

// Reserved address 524 [0x20c]

// Reserved address 528 [0x210]

// Reserved address 532 [0x214]

// Reserved address 536 [0x218]

// Reserved address 540 [0x21c]

// Reserved address 544 [0x220]

// Reserved address 548 [0x224]

// Reserved address 552 [0x228]

// Reserved address 556 [0x22c]

// Reserved address 560 [0x230]

// Reserved address 564 [0x234]

// Reserved address 568 [0x238]

// Reserved address 572 [0x23c]

// Reserved address 576 [0x240]

// Reserved address 580 [0x244]

// Reserved address 584 [0x248]

// Reserved address 588 [0x24c]

// Reserved address 592 [0x250]

// Reserved address 596 [0x254]

// Reserved address 600 [0x258]

// Reserved address 604 [0x25c]

// Reserved address 608 [0x260]

// Reserved address 612 [0x264]

// Reserved address 616 [0x268]

// Reserved address 620 [0x26c]

// Reserved address 624 [0x270]

// Reserved address 628 [0x274]

// Reserved address 632 [0x278]

// Reserved address 636 [0x27c]

// Register XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0                 _MK_ADDR_CONST(0x280)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_SECURE                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_SCR                     0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_WORD_COUNT                      0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_RESET_VAL                       _MK_MASK_CONST(0x5000)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_RESET_MASK                      _MK_MASK_CONST(0x1ffff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_READ_MASK                       _MK_MASK_CONST(0x1ffff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_WRITE_MASK                      _MK_MASK_CONST(0x1ffff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_SHIFT                 _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_FIELD                 _MK_FIELD_CONST(0x7ff, XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_RANGE                 10:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_DEFAULT_MASK                  _MK_MASK_CONST(0x7ff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_SHIFT                        _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_FIELD                        _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_RANGE                        16:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_DEFAULT                      _MK_MASK_CONST(0xa)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0                       _MK_ADDR_CONST(0x284)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SCR                   0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_RESET_VAL                     _MK_MASK_CONST(0x60e0b10)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_RESET_MASK                    _MK_MASK_CONST(0x1fff8fff)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_READ_MASK                     _MK_MASK_CONST(0x1fff8fff)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff8fff)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_FIELD                        _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_RANGE                        2:0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_SHIFT                 _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_RANGE                 5:3
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_DEFAULT                       _MK_MASK_CONST(0x2)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_SHIFT                  _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_FIELD                  _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_RANGE                  7:6
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_SHIFT                     _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_FIELD                     _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_RANGE                     10:8
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_DEFAULT                   _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_RANGE                      11:11
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_SHIFT                       _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_FIELD                       _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_RANGE                       17:15
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_DEFAULT                     _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_SHIFT                       _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_FIELD                       _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_RANGE                       20:18
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_DEFAULT                     _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_SHIFT                 _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_FIELD                 _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_RANGE                 24:21
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_SHIFT                   _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_RANGE                   28:25
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0                       _MK_ADDR_CONST(0x288)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_SCR                   0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_RESET_VAL                     _MK_MASK_CONST(0x4820000)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_RESET_MASK                    _MK_MASK_CONST(0x7fffffff)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_READ_MASK                     _MK_MASK_CONST(0x7fffffff)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_WRITE_MASK                    _MK_MASK_CONST(0x6ffff000)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_RANGE                   5:0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_SHIFT                   _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_RANGE                   11:6
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_SHIFT                 _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_FIELD                 _MK_FIELD_CONST(0x7f, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_RANGE                 18:12
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_DEFAULT                       _MK_MASK_CONST(0x20)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_SHIFT                    _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_FIELD                    _MK_FIELD_CONST(0x7f, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_RANGE                    25:19
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_DEFAULT                  _MK_MASK_CONST(0x10)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_SHIFT                  _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_RANGE                  26:26
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_DEFAULT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_SHIFT                       _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_RANGE                       27:27
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RANGE                        28:28
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_SHIFT                     _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_RANGE                     29:29
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_SHIFT                        _MK_SHIFT_CONST(30)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_RANGE                        30:30
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 652 [0x28c]

// Reserved address 656 [0x290]

// Reserved address 660 [0x294]

// Reserved address 664 [0x298]

// Reserved address 668 [0x29c]

// Reserved address 672 [0x2a0]

// Reserved address 676 [0x2a4]

// Reserved address 680 [0x2a8]

// Reserved address 684 [0x2ac]

// Reserved address 688 [0x2b0]

// Reserved address 692 [0x2b4]

// Reserved address 696 [0x2b8]

// Reserved address 700 [0x2bc]

// Reserved address 704 [0x2c0]

// Reserved address 708 [0x2c4]

// Reserved address 712 [0x2c8]

// Reserved address 716 [0x2cc]

// Reserved address 720 [0x2d0]

// Reserved address 724 [0x2d4]

// Reserved address 728 [0x2d8]

// Reserved address 732 [0x2dc]

// Reserved address 736 [0x2e0]

// Reserved address 740 [0x2e4]

// Reserved address 744 [0x2e8]

// Reserved address 748 [0x2ec]

// Reserved address 752 [0x2f0]

// Reserved address 756 [0x2f4]

// Reserved address 760 [0x2f8]

// Reserved address 764 [0x2fc]

// Register XUSB_PADCTL_HSIC_PAD0_CTL_0_0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0                   _MK_ADDR_CONST(0x300)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_SECURE                    0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_SCR                       0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_WORD_COUNT                        0x1
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RESET_VAL                         _MK_MASK_CONST(0xe3fe)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RESET_MASK                        _MK_MASK_CONST(0x7ffff)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_READ_MASK                         _MK_MASK_CONST(0x7ffff)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_WRITE_MASK                        _MK_MASK_CONST(0x7ffff)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_IDDQ_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_IDDQ_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_IDDQ_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_IDDQ_RANGE                        0:0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_IDDQ_WOFFSET                      0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_IDDQ_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_IDDQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_IDDQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_IDDQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA0_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA0_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA0_RANGE                 1:1
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA0_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA0_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA1_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA1_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA1_RANGE                 2:2
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA1_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA1_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_DATA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_STROBE_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_STROBE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_STROBE_RANGE                        3:3
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_STROBE_WOFFSET                      0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_STROBE_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_STROBE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_STROBE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_TX_STROBE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA0_SHIFT                 _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA0_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA0_RANGE                 4:4
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA0_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA0_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA1_SHIFT                 _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA1_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA1_RANGE                 5:5
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA1_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA1_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_DATA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_STROBE_SHIFT                        _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_STROBE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_STROBE_RANGE                        6:6
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_STROBE_WOFFSET                      0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_STROBE_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_STROBE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_STROBE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_RX_STROBE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA0_SHIFT                 _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA0_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA0_RANGE                 7:7
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA0_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA0_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA1_SHIFT                 _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA1_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA1_RANGE                 8:8
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA1_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA1_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_DATA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_STROBE_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_STROBE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_STROBE_RANGE                        9:9
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_STROBE_WOFFSET                      0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_STROBE_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_STROBE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_STROBE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_PD_ZI_STROBE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA0_SHIFT                  _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA0_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA0_RANGE                  10:10
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA0_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA0_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA1_SHIFT                  _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA1_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA1_RANGE                  11:11
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA1_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA1_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_DATA1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_STROBE_SHIFT                 _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_STROBE_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_STROBE_RANGE                 12:12
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_STROBE_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_STROBE_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_STROBE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_STROBE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_LPBK_STROBE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA0_SHIFT                   _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA0_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA0_RANGE                   13:13
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA0_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA0_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA1_SHIFT                   _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA1_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA1_RANGE                   14:14
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA1_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA1_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_DATA1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_STROBE_SHIFT                  _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_STROBE_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_STROBE_RANGE                  15:15
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_STROBE_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_STROBE_DEFAULT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_STROBE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_STROBE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPD_STROBE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA0_SHIFT                   _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA0_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA0_RANGE                   16:16
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA0_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA0_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA1_SHIFT                   _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA1_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA1_RANGE                   17:17
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA1_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA1_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_DATA1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_STROBE_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_STROBE_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_STROBE_RANGE                  18:18
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_STROBE_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_STROBE_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_STROBE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_STROBE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_0_0_RPU_STROBE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_HSIC_PAD0_CTL_1_0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0                   _MK_ADDR_CONST(0x304)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_SECURE                    0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_SCR                       0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_WORD_COUNT                        0x1
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RESET_VAL                         _MK_MASK_CONST(0x10008)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RESET_MASK                        _MK_MASK_CONST(0x6b7ffff)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_READ_MASK                         _MK_MASK_CONST(0x6b7ffff)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_WRITE_MASK                        _MK_MASK_CONST(0x6b7ffff)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_RTUNEP_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_RTUNEP_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_RTUNEP_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_RTUNEP_RANGE                   3:0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_RTUNEP_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_RTUNEP_DEFAULT                 _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_RTUNEP_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_RTUNEP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_RTUNEP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_SLEW_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_SLEW_FIELD                     _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_SLEW_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_SLEW_RANGE                     7:4
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_SLEW_WOFFSET                   0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_SLEW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_SLEW_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_SLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TX_SLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_OPT_SHIFT                    _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_OPT_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_OPT_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_OPT_RANGE                    11:8
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_OPT_WOFFSET                  0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_OPT_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_OPT_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_OPT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_OPT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RTERM_SHIFT                       _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RTERM_FIELD                       _MK_FIELD_CONST(0x1f, XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RTERM_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RTERM_RANGE                       16:12
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RTERM_WOFFSET                     0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RTERM_DEFAULT                     _MK_MASK_CONST(0x10)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RTERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RTERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RTERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_BUS_KEEPER_RES_SEL_SHIFT                  _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_BUS_KEEPER_RES_SEL_FIELD                  _MK_FIELD_CONST(0x3, XUSB_PADCTL_HSIC_PAD0_CTL_1_0_BUS_KEEPER_RES_SEL_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_BUS_KEEPER_RES_SEL_RANGE                  18:17
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_BUS_KEEPER_RES_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_BUS_KEEPER_RES_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_BUS_KEEPER_RES_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_BUS_KEEPER_RES_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_BUS_KEEPER_RES_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TRACK_RES_SEL_SHIFT                       _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TRACK_RES_SEL_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TRACK_RES_SEL_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TRACK_RES_SEL_RANGE                       21:20
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TRACK_RES_SEL_WOFFSET                     0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TRACK_RES_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TRACK_RES_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TRACK_RES_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_TRACK_RES_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RX_REC_SEL_SHIFT                  _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RX_REC_SEL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RX_REC_SEL_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RX_REC_SEL_RANGE                  23:23
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RX_REC_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RX_REC_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RX_REC_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RX_REC_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_RX_REC_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_AO_OPT_SHIFT                 _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_AO_OPT_FIELD                 _MK_FIELD_CONST(0x3, XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_AO_OPT_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_AO_OPT_RANGE                 26:25
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_AO_OPT_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_AO_OPT_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_AO_OPT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_AO_OPT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_1_0_HSIC_AO_OPT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_HSIC_PAD0_CTL_2_0
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0                   _MK_ADDR_CONST(0x308)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_SECURE                    0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_SCR                       0
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_WORD_COUNT                        0x1
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RESET_VAL                         _MK_MASK_CONST(0x111)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RESET_MASK                        _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_READ_MASK                         _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_WRITE_MASK                        _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA0_TRIM_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA0_TRIM_FIELD                       _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA0_TRIM_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA0_TRIM_RANGE                       3:0
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA0_TRIM_WOFFSET                     0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA0_TRIM_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA0_TRIM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA0_TRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA0_TRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA1_TRIM_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA1_TRIM_FIELD                       _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA1_TRIM_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA1_TRIM_RANGE                       7:4
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA1_TRIM_WOFFSET                     0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA1_TRIM_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA1_TRIM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA1_TRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_DATA1_TRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_STROBE_TRIM_SHIFT                      _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_STROBE_TRIM_FIELD                      _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_STROBE_TRIM_SHIFT)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_STROBE_TRIM_RANGE                      11:8
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_STROBE_TRIM_WOFFSET                    0x0
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_STROBE_TRIM_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_STROBE_TRIM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_STROBE_TRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD0_CTL_2_0_RX_STROBE_TRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 780 [0x30c]

// Reserved address 784 [0x310]

// Reserved address 788 [0x314]

// Reserved address 792 [0x318]

// Reserved address 796 [0x31c]

// Register XUSB_PADCTL_HSIC_PAD1_CTL_0_0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0                   _MK_ADDR_CONST(0x320)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_SECURE                    0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_SCR                       0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_WORD_COUNT                        0x1
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RESET_VAL                         _MK_MASK_CONST(0xe3fe)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RESET_MASK                        _MK_MASK_CONST(0x7ffff)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_READ_MASK                         _MK_MASK_CONST(0x7ffff)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_WRITE_MASK                        _MK_MASK_CONST(0x7ffff)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_IDDQ_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_IDDQ_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_IDDQ_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_IDDQ_RANGE                        0:0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_IDDQ_WOFFSET                      0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_IDDQ_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_IDDQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_IDDQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_IDDQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA0_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA0_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA0_RANGE                 1:1
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA0_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA0_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA1_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA1_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA1_RANGE                 2:2
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA1_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA1_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_DATA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_STROBE_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_STROBE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_STROBE_RANGE                        3:3
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_STROBE_WOFFSET                      0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_STROBE_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_STROBE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_STROBE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_TX_STROBE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA0_SHIFT                 _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA0_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA0_RANGE                 4:4
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA0_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA0_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA1_SHIFT                 _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA1_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA1_RANGE                 5:5
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA1_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA1_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_DATA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_STROBE_SHIFT                        _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_STROBE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_STROBE_RANGE                        6:6
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_STROBE_WOFFSET                      0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_STROBE_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_STROBE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_STROBE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_RX_STROBE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA0_SHIFT                 _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA0_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA0_RANGE                 7:7
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA0_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA0_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA1_SHIFT                 _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA1_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA1_RANGE                 8:8
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA1_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA1_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_DATA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_STROBE_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_STROBE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_STROBE_RANGE                        9:9
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_STROBE_WOFFSET                      0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_STROBE_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_STROBE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_STROBE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_PD_ZI_STROBE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA0_SHIFT                  _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA0_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA0_RANGE                  10:10
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA0_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA0_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA1_SHIFT                  _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA1_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA1_RANGE                  11:11
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA1_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA1_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_DATA1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_STROBE_SHIFT                 _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_STROBE_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_STROBE_RANGE                 12:12
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_STROBE_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_STROBE_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_STROBE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_STROBE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_LPBK_STROBE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA0_SHIFT                   _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA0_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA0_RANGE                   13:13
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA0_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA0_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA1_SHIFT                   _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA1_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA1_RANGE                   14:14
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA1_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA1_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_DATA1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_STROBE_SHIFT                  _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_STROBE_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_STROBE_RANGE                  15:15
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_STROBE_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_STROBE_DEFAULT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_STROBE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_STROBE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPD_STROBE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA0_SHIFT                   _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA0_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA0_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA0_RANGE                   16:16
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA0_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA0_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA1_SHIFT                   _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA1_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA1_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA1_RANGE                   17:17
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA1_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA1_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_DATA1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_STROBE_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_STROBE_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_STROBE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_STROBE_RANGE                  18:18
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_STROBE_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_STROBE_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_STROBE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_STROBE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_0_0_RPU_STROBE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_HSIC_PAD1_CTL_1_0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0                   _MK_ADDR_CONST(0x324)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_SECURE                    0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_SCR                       0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_WORD_COUNT                        0x1
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RESET_VAL                         _MK_MASK_CONST(0x10008)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RESET_MASK                        _MK_MASK_CONST(0x6b7ffff)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_READ_MASK                         _MK_MASK_CONST(0x6b7ffff)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_WRITE_MASK                        _MK_MASK_CONST(0x6b7ffff)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_RTUNEP_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_RTUNEP_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_RTUNEP_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_RTUNEP_RANGE                   3:0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_RTUNEP_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_RTUNEP_DEFAULT                 _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_RTUNEP_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_RTUNEP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_RTUNEP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_SLEW_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_SLEW_FIELD                     _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_SLEW_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_SLEW_RANGE                     7:4
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_SLEW_WOFFSET                   0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_SLEW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_SLEW_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_SLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TX_SLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_OPT_SHIFT                    _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_OPT_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_OPT_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_OPT_RANGE                    11:8
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_OPT_WOFFSET                  0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_OPT_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_OPT_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_OPT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_OPT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RTERM_SHIFT                       _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RTERM_FIELD                       _MK_FIELD_CONST(0x1f, XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RTERM_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RTERM_RANGE                       16:12
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RTERM_WOFFSET                     0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RTERM_DEFAULT                     _MK_MASK_CONST(0x10)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RTERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RTERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RTERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_BUS_KEEPER_RES_SEL_SHIFT                  _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_BUS_KEEPER_RES_SEL_FIELD                  _MK_FIELD_CONST(0x3, XUSB_PADCTL_HSIC_PAD1_CTL_1_0_BUS_KEEPER_RES_SEL_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_BUS_KEEPER_RES_SEL_RANGE                  18:17
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_BUS_KEEPER_RES_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_BUS_KEEPER_RES_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_BUS_KEEPER_RES_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_BUS_KEEPER_RES_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_BUS_KEEPER_RES_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TRACK_RES_SEL_SHIFT                       _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TRACK_RES_SEL_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TRACK_RES_SEL_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TRACK_RES_SEL_RANGE                       21:20
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TRACK_RES_SEL_WOFFSET                     0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TRACK_RES_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TRACK_RES_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TRACK_RES_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_TRACK_RES_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RX_REC_SEL_SHIFT                  _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RX_REC_SEL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RX_REC_SEL_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RX_REC_SEL_RANGE                  23:23
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RX_REC_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RX_REC_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RX_REC_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RX_REC_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_RX_REC_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_AO_OPT_SHIFT                 _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_AO_OPT_FIELD                 _MK_FIELD_CONST(0x3, XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_AO_OPT_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_AO_OPT_RANGE                 26:25
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_AO_OPT_WOFFSET                       0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_AO_OPT_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_AO_OPT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_AO_OPT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_1_0_HSIC_AO_OPT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_HSIC_PAD1_CTL_2_0
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0                   _MK_ADDR_CONST(0x328)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_SECURE                    0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_SCR                       0
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_WORD_COUNT                        0x1
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RESET_VAL                         _MK_MASK_CONST(0x111)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RESET_MASK                        _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_READ_MASK                         _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_WRITE_MASK                        _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA0_TRIM_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA0_TRIM_FIELD                       _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA0_TRIM_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA0_TRIM_RANGE                       3:0
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA0_TRIM_WOFFSET                     0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA0_TRIM_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA0_TRIM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA0_TRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA0_TRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA1_TRIM_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA1_TRIM_FIELD                       _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA1_TRIM_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA1_TRIM_RANGE                       7:4
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA1_TRIM_WOFFSET                     0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA1_TRIM_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA1_TRIM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA1_TRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_DATA1_TRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_STROBE_TRIM_SHIFT                      _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_STROBE_TRIM_FIELD                      _MK_FIELD_CONST(0xf, XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_STROBE_TRIM_SHIFT)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_STROBE_TRIM_RANGE                      11:8
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_STROBE_TRIM_WOFFSET                    0x0
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_STROBE_TRIM_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_STROBE_TRIM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_STROBE_TRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD1_CTL_2_0_RX_STROBE_TRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 812 [0x32c]

// Reserved address 816 [0x330]

// Reserved address 820 [0x334]

// Reserved address 824 [0x338]

// Reserved address 828 [0x33c]

// Register XUSB_PADCTL_HSIC_PAD_TRK_CTL_0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0                  _MK_ADDR_CONST(0x340)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_SECURE                   0x0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_SCR                      0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_WORD_COUNT                       0x1
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_RESET_VAL                        _MK_MASK_CONST(0x1090400)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_RESET_MASK                       _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_READ_MASK                        _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_WRITE_MASK                       _MK_MASK_CONST(0x1dfffe0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_RTERM_OUT_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_RTERM_OUT_FIELD                  _MK_FIELD_CONST(0x1f, XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_RTERM_OUT_SHIFT)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_RTERM_OUT_RANGE                  4:0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_RTERM_OUT_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_RTERM_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_RTERM_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_RTERM_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_RTERM_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_TIMER_SHIFT                    _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_TIMER_FIELD                    _MK_FIELD_CONST(0x7f, XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_TIMER_SHIFT)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_TIMER_RANGE                    11:5
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_TIMER_WOFFSET                  0x0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_TIMER_DEFAULT                  _MK_MASK_CONST(0x20)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_TIMER_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_TIMER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_TIMER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_RESET_TIMER_SHIFT                       _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_RESET_TIMER_FIELD                       _MK_FIELD_CONST(0x7f, XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_RESET_TIMER_SHIFT)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_RESET_TIMER_RANGE                       18:12
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_RESET_TIMER_WOFFSET                     0x0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_RESET_TIMER_DEFAULT                     _MK_MASK_CONST(0x10)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_RESET_TIMER_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_RESET_TIMER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_RESET_TIMER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_PD_TRK_SHIFT                     _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_PD_TRK_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_PD_TRK_SHIFT)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_PD_TRK_RANGE                     19:19
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_PD_TRK_WOFFSET                   0x0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_PD_TRK_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_PD_TRK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_PD_TRK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_PD_TRK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_SHIFT                  _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_SHIFT)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_RANGE                  20:20
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_WOFFSET                        0x0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_SHIFT                   _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_SHIFT)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_RANGE                   21:21
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_DONE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_SW_OVRD_SHIFT                        _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_SW_OVRD_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_SW_OVRD_SHIFT)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_SW_OVRD_RANGE                        22:22
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_SW_OVRD_WOFFSET                      0x0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_SW_OVRD_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_SW_OVRD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_SW_OVRD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_TRK_SW_OVRD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_FORCE_TRK_CLK_EN_SHIFT                   _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_FORCE_TRK_CLK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_FORCE_TRK_CLK_EN_SHIFT)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_FORCE_TRK_CLK_EN_RANGE                   23:23
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_FORCE_TRK_CLK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_FORCE_TRK_CLK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_FORCE_TRK_CLK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_FORCE_TRK_CLK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_FORCE_TRK_CLK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_AUTO_RTERM_EN_SHIFT                      _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_AUTO_RTERM_EN_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_AUTO_RTERM_EN_SHIFT)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_AUTO_RTERM_EN_RANGE                      24:24
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_AUTO_RTERM_EN_WOFFSET                    0x0
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_AUTO_RTERM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_AUTO_RTERM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_AUTO_RTERM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_0_AUTO_RTERM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0                    _MK_ADDR_CONST(0x344)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_SECURE                     0x0
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_SCR                        0
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x7f)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_STRB_TRIM_VAL_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_STRB_TRIM_VAL_FIELD                        _MK_FIELD_CONST(0x7f, XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_STRB_TRIM_VAL_SHIFT)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_STRB_TRIM_VAL_RANGE                        6:0
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_STRB_TRIM_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_STRB_TRIM_VAL_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_STRB_TRIM_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_STRB_TRIM_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0_STRB_TRIM_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 840 [0x348]

// Reserved address 844 [0x34c]

// Reserved address 848 [0x350]

// Reserved address 852 [0x354]

// Reserved address 856 [0x358]

// Reserved address 860 [0x35c]

// Register XUSB_PADCTL_USB2_VBUS_ID_0
#define XUSB_PADCTL_USB2_VBUS_ID_0                      _MK_ADDR_CONST(0x360)
#define XUSB_PADCTL_USB2_VBUS_ID_0_SECURE                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_SCR                  0
#define XUSB_PADCTL_USB2_VBUS_ID_0_WORD_COUNT                   0x1
#define XUSB_PADCTL_USB2_VBUS_ID_0_RESET_VAL                    _MK_MASK_CONST(0x211000)
#define XUSB_PADCTL_USB2_VBUS_ID_0_RESET_MASK                   _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_READ_MASK                    _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_0_WRITE_MASK                   _MK_MASK_CONST(0x1bffc36)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_RANGE                      0:0
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT                      _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_RANGE                      1:1
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_RANGE                 2:2
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_SHIFT                     _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_RANGE                     3:3
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_RANGE                     4:4
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_RANGE                        5:5
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_SHIFT                  _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_RANGE                  6:6
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_RANGE                        7:7
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_SHIFT                        _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_RANGE                        8:8
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_RANGE                        9:9
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_RANGE                  10:10
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_RANGE                     11:11
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_SHIFT                     _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_RANGE                     13:12
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_VGPIO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_VBUS_OVERRIDE                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_RANGE                  14:14
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_RANGE                   15:15
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_RANGE                       17:16
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_VGPIO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_ID_OVERRIDE                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_RANGE                    21:18
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_RANGE                    22:22
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_SHIFT                    _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_RANGE                    23:23
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT                       _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_RANGE                       24:24
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_YES                 _MK_ENUM_CONST(1)


// Reserved address 868 [0x364]

// Reserved address 872 [0x368]

// Reserved address 876 [0x36c]

// Reserved address 880 [0x370]

// Reserved address 884 [0x374]

// Reserved address 888 [0x378]

// Reserved address 892 [0x37c]

// Reserved address 896 [0x380]

// Reserved address 900 [0x384]

// Reserved address 904 [0x388]

// Reserved address 908 [0x38c]

// Reserved address 912 [0x390]

// Reserved address 916 [0x394]

// Reserved address 920 [0x398]

// Reserved address 924 [0x39c]

// Reserved address 928 [0x3a0]

// Reserved address 932 [0x3a4]

// Reserved address 936 [0x3a8]

// Reserved address 940 [0x3ac]

// Reserved address 944 [0x3b0]

// Reserved address 948 [0x3b4]

// Reserved address 952 [0x3b8]

// Reserved address 956 [0x3bc]

// Reserved address 960 [0x3c0]

// Reserved address 964 [0x3c4]

// Reserved address 968 [0x3c8]

// Reserved address 972 [0x3cc]

// Reserved address 976 [0x3d0]

// Reserved address 980 [0x3d4]

// Reserved address 984 [0x3d8]

// Reserved address 988 [0x3dc]

// Reserved address 992 [0x3e0]

// Reserved address 996 [0x3e4]

// Reserved address 1000 [0x3e8]

// Reserved address 1004 [0x3ec]

// Reserved address 1008 [0x3f0]

// Reserved address 1012 [0x3f4]

// Reserved address 1016 [0x3f8]

// Reserved address 1020 [0x3fc]

// Reserved address 1024 [0x400]

// Reserved address 1028 [0x404]

// Reserved address 1032 [0x408]

// Reserved address 1036 [0x40c]

// Reserved address 1040 [0x410]

// Reserved address 1044 [0x414]

// Reserved address 1048 [0x418]

// Reserved address 1052 [0x41c]

// Reserved address 1056 [0x420]

// Reserved address 1060 [0x424]

// Reserved address 1064 [0x428]

// Reserved address 1068 [0x42c]

// Reserved address 1072 [0x430]

// Reserved address 1076 [0x434]

// Reserved address 1080 [0x438]

// Reserved address 1084 [0x43c]

// Reserved address 1088 [0x440]

// Reserved address 1092 [0x444]

// Reserved address 1096 [0x448]

// Reserved address 1100 [0x44c]

// Reserved address 1104 [0x450]

// Reserved address 1108 [0x454]

// Reserved address 1112 [0x458]

// Reserved address 1116 [0x45c]

// Reserved address 1120 [0x460]

// Reserved address 1124 [0x464]

// Reserved address 1128 [0x468]

// Reserved address 1132 [0x46c]

// Reserved address 1136 [0x470]

// Reserved address 1140 [0x474]

// Reserved address 1144 [0x478]

// Reserved address 1148 [0x47c]

// Reserved address 1152 [0x480]

// Reserved address 1156 [0x484]

// Reserved address 1160 [0x488]

// Reserved address 1164 [0x48c]

// Reserved address 1168 [0x490]

// Reserved address 1172 [0x494]

// Reserved address 1176 [0x498]

// Reserved address 1180 [0x49c]

// Reserved address 1184 [0x4a0]

// Reserved address 1188 [0x4a4]

// Reserved address 1192 [0x4a8]

// Reserved address 1196 [0x4ac]

// Reserved address 1200 [0x4b0]

// Reserved address 1204 [0x4b4]

// Reserved address 1208 [0x4b8]

// Reserved address 1212 [0x4bc]

// Reserved address 1216 [0x4c0]

// Reserved address 1220 [0x4c4]

// Reserved address 1224 [0x4c8]

// Reserved address 1228 [0x4cc]

// Reserved address 1232 [0x4d0]

// Reserved address 1236 [0x4d4]

// Reserved address 1240 [0x4d8]

// Reserved address 1244 [0x4dc]

// Reserved address 1248 [0x4e0]

// Reserved address 1252 [0x4e4]

// Reserved address 1256 [0x4e8]

// Reserved address 1260 [0x4ec]

// Reserved address 1264 [0x4f0]

// Reserved address 1268 [0x4f4]

// Reserved address 1272 [0x4f8]

// Reserved address 1276 [0x4fc]

// Reserved address 1280 [0x500]

// Reserved address 1284 [0x504]

// Reserved address 1288 [0x508]

// Reserved address 1292 [0x50c]

// Reserved address 1296 [0x510]

// Reserved address 1300 [0x514]

// Reserved address 1304 [0x518]

// Reserved address 1308 [0x51c]

// Reserved address 1312 [0x520]

// Reserved address 1316 [0x524]

// Reserved address 1320 [0x528]

// Reserved address 1324 [0x52c]

// Reserved address 1328 [0x530]

// Reserved address 1332 [0x534]

// Reserved address 1336 [0x538]

// Reserved address 1340 [0x53c]

// Reserved address 1344 [0x540]

// Reserved address 1348 [0x544]

// Reserved address 1352 [0x548]

// Reserved address 1356 [0x54c]

// Reserved address 1360 [0x550]

// Reserved address 1364 [0x554]

// Reserved address 1368 [0x558]

// Reserved address 1372 [0x55c]

// Reserved address 1376 [0x560]

// Reserved address 1380 [0x564]

// Reserved address 1384 [0x568]

// Reserved address 1388 [0x56c]

// Reserved address 1392 [0x570]

// Reserved address 1396 [0x574]

// Reserved address 1400 [0x578]

// Reserved address 1404 [0x57c]

// Reserved address 1408 [0x580]

// Reserved address 1412 [0x584]

// Reserved address 1416 [0x588]

// Reserved address 1420 [0x58c]

// Reserved address 1424 [0x590]

// Reserved address 1428 [0x594]

// Reserved address 1432 [0x598]

// Reserved address 1436 [0x59c]

// Reserved address 1440 [0x5a0]

// Reserved address 1444 [0x5a4]

// Reserved address 1448 [0x5a8]

// Reserved address 1452 [0x5ac]

// Reserved address 1456 [0x5b0]

// Reserved address 1460 [0x5b4]

// Reserved address 1464 [0x5b8]

// Reserved address 1468 [0x5bc]

// Reserved address 1472 [0x5c0]

// Reserved address 1476 [0x5c4]

// Reserved address 1480 [0x5c8]

// Reserved address 1484 [0x5cc]

// Reserved address 1488 [0x5d0]

// Reserved address 1492 [0x5d4]

// Reserved address 1496 [0x5d8]

// Reserved address 1500 [0x5dc]

// Reserved address 1504 [0x5e0]

// Reserved address 1508 [0x5e4]

// Reserved address 1512 [0x5e8]

// Reserved address 1516 [0x5ec]

// Reserved address 1520 [0x5f0]

// Reserved address 1524 [0x5f4]

// Reserved address 1528 [0x5f8]

// Reserved address 1532 [0x5fc]

// Reserved address 1536 [0x600]

// Reserved address 1540 [0x604]

// Reserved address 1544 [0x608]

// Reserved address 1548 [0x60c]

// Reserved address 1552 [0x610]

// Reserved address 1556 [0x614]

// Reserved address 1560 [0x618]

// Reserved address 1564 [0x61c]

// Reserved address 1568 [0x620]

// Reserved address 1572 [0x624]

// Reserved address 1576 [0x628]

// Reserved address 1580 [0x62c]

// Reserved address 1584 [0x630]

// Reserved address 1588 [0x634]

// Reserved address 1592 [0x638]

// Reserved address 1596 [0x63c]

// Reserved address 1600 [0x640]

// Reserved address 1604 [0x644]

// Reserved address 1608 [0x648]

// Reserved address 1612 [0x64c]

// Reserved address 1616 [0x650]

// Reserved address 1620 [0x654]

// Reserved address 1624 [0x658]

// Reserved address 1628 [0x65c]

// Reserved address 1632 [0x660]

// Reserved address 1636 [0x664]

// Reserved address 1640 [0x668]

// Reserved address 1644 [0x66c]

// Reserved address 1648 [0x670]

// Reserved address 1652 [0x674]

// Reserved address 1656 [0x678]

// Reserved address 1660 [0x67c]

// Reserved address 1664 [0x680]

// Reserved address 1668 [0x684]

// Reserved address 1672 [0x688]

// Reserved address 1676 [0x68c]

// Reserved address 1680 [0x690]

// Reserved address 1684 [0x694]

// Reserved address 1688 [0x698]

// Reserved address 1692 [0x69c]

// Reserved address 1696 [0x6a0]

// Reserved address 1700 [0x6a4]

// Reserved address 1704 [0x6a8]

// Reserved address 1708 [0x6ac]

// Reserved address 1712 [0x6b0]

// Reserved address 1716 [0x6b4]

// Reserved address 1720 [0x6b8]

// Reserved address 1724 [0x6bc]

// Reserved address 1728 [0x6c0]

// Reserved address 1732 [0x6c4]

// Reserved address 1736 [0x6c8]

// Reserved address 1740 [0x6cc]

// Reserved address 1744 [0x6d0]

// Reserved address 1748 [0x6d4]

// Reserved address 1752 [0x6d8]

// Reserved address 1756 [0x6dc]

// Reserved address 1760 [0x6e0]

// Reserved address 1764 [0x6e4]

// Reserved address 1768 [0x6e8]

// Reserved address 1772 [0x6ec]

// Reserved address 1776 [0x6f0]

// Reserved address 1780 [0x6f4]

// Reserved address 1784 [0x6f8]

// Reserved address 1788 [0x6fc]

// Reserved address 1792 [0x700]

// Reserved address 1796 [0x704]

// Reserved address 1800 [0x708]

// Reserved address 1804 [0x70c]

// Reserved address 1808 [0x710]

// Reserved address 1812 [0x714]

// Reserved address 1816 [0x718]

// Reserved address 1820 [0x71c]

// Reserved address 1824 [0x720]

// Reserved address 1828 [0x724]

// Reserved address 1832 [0x728]

// Reserved address 1836 [0x72c]

// Reserved address 1840 [0x730]

// Reserved address 1844 [0x734]

// Reserved address 1848 [0x738]

// Reserved address 1852 [0x73c]

// Reserved address 1856 [0x740]

// Reserved address 1860 [0x744]

// Reserved address 1864 [0x748]

// Reserved address 1868 [0x74c]

// Reserved address 1872 [0x750]

// Reserved address 1876 [0x754]

// Reserved address 1880 [0x758]

// Reserved address 1884 [0x75c]

// Reserved address 1888 [0x760]

// Reserved address 1892 [0x764]

// Reserved address 1896 [0x768]

// Reserved address 1900 [0x76c]

// Reserved address 1904 [0x770]

// Reserved address 1908 [0x774]

// Reserved address 1912 [0x778]

// Reserved address 1916 [0x77c]

// Reserved address 1920 [0x780]

// Reserved address 1924 [0x784]

// Reserved address 1928 [0x788]

// Reserved address 1932 [0x78c]

// Reserved address 1936 [0x790]

// Reserved address 1940 [0x794]

// Reserved address 1944 [0x798]

// Reserved address 1948 [0x79c]

// Reserved address 1952 [0x7a0]

// Reserved address 1956 [0x7a4]

// Reserved address 1960 [0x7a8]

// Reserved address 1964 [0x7ac]

// Reserved address 1968 [0x7b0]

// Reserved address 1972 [0x7b4]

// Reserved address 1976 [0x7b8]

// Reserved address 1980 [0x7bc]

// Reserved address 1984 [0x7c0]

// Reserved address 1988 [0x7c4]

// Reserved address 1992 [0x7c8]

// Reserved address 1996 [0x7cc]

// Reserved address 2000 [0x7d0]

// Reserved address 2004 [0x7d4]

// Reserved address 2008 [0x7d8]

// Reserved address 2012 [0x7dc]

// Reserved address 2016 [0x7e0]

// Reserved address 2020 [0x7e4]

// Reserved address 2024 [0x7e8]

// Reserved address 2028 [0x7ec]

// Reserved address 2032 [0x7f0]

// Reserved address 2036 [0x7f4]

// Reserved address 2040 [0x7f8]

// Reserved address 2044 [0x7fc]

// Reserved address 2048 [0x800]

// Reserved address 2052 [0x804]

// Reserved address 2056 [0x808]

// Reserved address 2060 [0x80c]

// Reserved address 2064 [0x810]

// Reserved address 2068 [0x814]

// Reserved address 2072 [0x818]

// Reserved address 2076 [0x81c]

// Reserved address 2080 [0x820]

// Reserved address 2084 [0x824]

// Reserved address 2088 [0x828]

// Reserved address 2092 [0x82c]

// Reserved address 2096 [0x830]

// Reserved address 2100 [0x834]

// Reserved address 2104 [0x838]

// Reserved address 2108 [0x83c]

// Reserved address 2112 [0x840]

// Reserved address 2116 [0x844]

// Reserved address 2120 [0x848]

// Reserved address 2124 [0x84c]

// Reserved address 2128 [0x850]

// Reserved address 2132 [0x854]

// Reserved address 2136 [0x858]

// Reserved address 2140 [0x85c]

// Reserved address 2144 [0x860]

// Reserved address 2148 [0x864]

// Reserved address 2152 [0x868]

// Reserved address 2156 [0x86c]

// Reserved address 2160 [0x870]

// Reserved address 2164 [0x874]

// Reserved address 2168 [0x878]

// Reserved address 2172 [0x87c]

// Reserved address 2176 [0x880]

// Reserved address 2180 [0x884]

// Reserved address 2184 [0x888]

// Reserved address 2188 [0x88c]

// Reserved address 2192 [0x890]

// Reserved address 2196 [0x894]

// Reserved address 2200 [0x898]

// Reserved address 2204 [0x89c]

// Reserved address 2208 [0x8a0]

// Reserved address 2212 [0x8a4]

// Reserved address 2216 [0x8a8]

// Reserved address 2220 [0x8ac]

// Reserved address 2224 [0x8b0]

// Reserved address 2228 [0x8b4]

// Reserved address 2232 [0x8b8]

// Reserved address 2236 [0x8bc]

// Reserved address 2240 [0x8c0]

// Reserved address 2244 [0x8c4]

// Reserved address 2248 [0x8c8]

// Reserved address 2252 [0x8cc]

// Reserved address 2256 [0x8d0]

// Reserved address 2260 [0x8d4]

// Reserved address 2264 [0x8d8]

// Reserved address 2268 [0x8dc]

// Reserved address 2272 [0x8e0]

// Reserved address 2276 [0x8e4]

// Reserved address 2280 [0x8e8]

// Reserved address 2284 [0x8ec]

// Reserved address 2288 [0x8f0]

// Reserved address 2292 [0x8f4]

// Reserved address 2296 [0x8f8]

// Reserved address 2300 [0x8fc]

// Reserved address 2304 [0x900]

// Reserved address 2308 [0x904]

// Reserved address 2312 [0x908]

// Reserved address 2316 [0x90c]

// Reserved address 2320 [0x910]

// Reserved address 2324 [0x914]

// Reserved address 2328 [0x918]

// Reserved address 2332 [0x91c]

// Reserved address 2336 [0x920]

// Reserved address 2340 [0x924]

// Reserved address 2344 [0x928]

// Reserved address 2348 [0x92c]

// Reserved address 2352 [0x930]

// Reserved address 2356 [0x934]

// Reserved address 2360 [0x938]

// Reserved address 2364 [0x93c]

// Reserved address 2368 [0x940]

// Reserved address 2372 [0x944]

// Reserved address 2376 [0x948]

// Reserved address 2380 [0x94c]

// Reserved address 2384 [0x950]

// Reserved address 2388 [0x954]

// Reserved address 2392 [0x958]

// Reserved address 2396 [0x95c]

// Reserved address 2400 [0x960]

// Reserved address 2404 [0x964]

// Reserved address 2408 [0x968]

// Reserved address 2412 [0x96c]

// Reserved address 2416 [0x970]

// Reserved address 2420 [0x974]

// Reserved address 2424 [0x978]

// Reserved address 2428 [0x97c]

// Reserved address 2432 [0x980]

// Reserved address 2436 [0x984]

// Reserved address 2440 [0x988]

// Reserved address 2444 [0x98c]

// Reserved address 2448 [0x990]

// Reserved address 2452 [0x994]

// Reserved address 2456 [0x998]

// Reserved address 2460 [0x99c]

// Reserved address 2464 [0x9a0]

// Reserved address 2468 [0x9a4]

// Reserved address 2472 [0x9a8]

// Reserved address 2476 [0x9ac]

// Reserved address 2480 [0x9b0]

// Reserved address 2484 [0x9b4]

// Reserved address 2488 [0x9b8]

// Reserved address 2492 [0x9bc]

// Reserved address 2496 [0x9c0]

// Reserved address 2500 [0x9c4]

// Reserved address 2504 [0x9c8]

// Reserved address 2508 [0x9cc]

// Reserved address 2512 [0x9d0]

// Reserved address 2516 [0x9d4]

// Reserved address 2520 [0x9d8]

// Reserved address 2524 [0x9dc]

// Reserved address 2528 [0x9e0]

// Reserved address 2532 [0x9e4]

// Reserved address 2536 [0x9e8]

// Reserved address 2540 [0x9ec]

// Reserved address 2544 [0x9f0]

// Reserved address 2548 [0x9f4]

// Reserved address 2552 [0x9f8]

// Reserved address 2556 [0x9fc]

// Reserved address 2560 [0xa00]

// Reserved address 2564 [0xa04]

// Reserved address 2568 [0xa08]

// Reserved address 2572 [0xa0c]

// Reserved address 2576 [0xa10]

// Reserved address 2580 [0xa14]

// Reserved address 2584 [0xa18]

// Reserved address 2588 [0xa1c]

// Reserved address 2592 [0xa20]

// Reserved address 2596 [0xa24]

// Reserved address 2600 [0xa28]

// Reserved address 2604 [0xa2c]

// Reserved address 2608 [0xa30]

// Reserved address 2612 [0xa34]

// Reserved address 2616 [0xa38]

// Reserved address 2620 [0xa3c]

// Reserved address 2624 [0xa40]

// Reserved address 2628 [0xa44]

// Reserved address 2632 [0xa48]

// Reserved address 2636 [0xa4c]

// Reserved address 2640 [0xa50]

// Reserved address 2644 [0xa54]

// Reserved address 2648 [0xa58]

// Reserved address 2652 [0xa5c]

// Reserved address 2656 [0xa60]

// Reserved address 2660 [0xa64]

// Reserved address 2664 [0xa68]

// Reserved address 2668 [0xa6c]

// Reserved address 2672 [0xa70]

// Reserved address 2676 [0xa74]

// Reserved address 2680 [0xa78]

// Reserved address 2684 [0xa7c]

// Reserved address 2688 [0xa80]

// Reserved address 2692 [0xa84]

// Reserved address 2696 [0xa88]

// Reserved address 2700 [0xa8c]

// Reserved address 2704 [0xa90]

// Reserved address 2708 [0xa94]

// Reserved address 2712 [0xa98]

// Reserved address 2716 [0xa9c]

// Reserved address 2720 [0xaa0]

// Reserved address 2724 [0xaa4]

// Reserved address 2728 [0xaa8]

// Reserved address 2732 [0xaac]

// Reserved address 2736 [0xab0]

// Reserved address 2740 [0xab4]

// Reserved address 2744 [0xab8]

// Reserved address 2748 [0xabc]

// Reserved address 2752 [0xac0]

// Reserved address 2756 [0xac4]

// Reserved address 2760 [0xac8]

// Reserved address 2764 [0xacc]

// Reserved address 2768 [0xad0]

// Reserved address 2772 [0xad4]

// Reserved address 2776 [0xad8]

// Reserved address 2780 [0xadc]

// Reserved address 2784 [0xae0]

// Reserved address 2788 [0xae4]

// Reserved address 2792 [0xae8]

// Reserved address 2796 [0xaec]

// Reserved address 2800 [0xaf0]

// Reserved address 2804 [0xaf4]

// Reserved address 2808 [0xaf8]

// Reserved address 2812 [0xafc]

// Reserved address 2816 [0xb00]

// Reserved address 2820 [0xb04]

// Reserved address 2824 [0xb08]

// Reserved address 2828 [0xb0c]

// Reserved address 2832 [0xb10]

// Reserved address 2836 [0xb14]

// Reserved address 2840 [0xb18]

// Reserved address 2844 [0xb1c]

// Reserved address 2848 [0xb20]

// Reserved address 2852 [0xb24]

// Reserved address 2856 [0xb28]

// Reserved address 2860 [0xb2c]

// Reserved address 2864 [0xb30]

// Reserved address 2868 [0xb34]

// Reserved address 2872 [0xb38]

// Reserved address 2876 [0xb3c]

// Reserved address 2880 [0xb40]

// Reserved address 2884 [0xb44]

// Reserved address 2888 [0xb48]

// Reserved address 2892 [0xb4c]

// Reserved address 2896 [0xb50]

// Reserved address 2900 [0xb54]

// Reserved address 2904 [0xb58]

// Reserved address 2908 [0xb5c]

// Reserved address 2912 [0xb60]

// Reserved address 2916 [0xb64]

// Reserved address 2920 [0xb68]

// Reserved address 2924 [0xb6c]

// Reserved address 2928 [0xb70]

// Reserved address 2932 [0xb74]

// Reserved address 2936 [0xb78]

// Reserved address 2940 [0xb7c]

// Reserved address 2944 [0xb80]

// Reserved address 2948 [0xb84]

// Reserved address 2952 [0xb88]

// Reserved address 2956 [0xb8c]

// Reserved address 2960 [0xb90]

// Reserved address 2964 [0xb94]

// Reserved address 2968 [0xb98]

// Reserved address 2972 [0xb9c]

// Reserved address 2976 [0xba0]

// Reserved address 2980 [0xba4]

// Reserved address 2984 [0xba8]

// Reserved address 2988 [0xbac]

// Reserved address 2992 [0xbb0]

// Reserved address 2996 [0xbb4]

// Reserved address 3000 [0xbb8]

// Reserved address 3004 [0xbbc]

// Reserved address 3008 [0xbc0]

// Reserved address 3012 [0xbc4]

// Reserved address 3016 [0xbc8]

// Reserved address 3020 [0xbcc]

// Reserved address 3024 [0xbd0]

// Reserved address 3028 [0xbd4]

// Reserved address 3032 [0xbd8]

// Reserved address 3036 [0xbdc]

// Reserved address 3040 [0xbe0]

// Reserved address 3044 [0xbe4]

// Reserved address 3048 [0xbe8]

// Reserved address 3052 [0xbec]

// Reserved address 3056 [0xbf0]

// Reserved address 3060 [0xbf4]

// Reserved address 3064 [0xbf8]

// Reserved address 3068 [0xbfc]

// Reserved address 3072 [0xc00]

// Reserved address 3076 [0xc04]

// Reserved address 3080 [0xc08]

// Reserved address 3084 [0xc0c]

// Reserved address 3088 [0xc10]

// Reserved address 3092 [0xc14]

// Reserved address 3096 [0xc18]

// Reserved address 3100 [0xc1c]

// Reserved address 3104 [0xc20]

// Reserved address 3108 [0xc24]

// Reserved address 3112 [0xc28]

// Reserved address 3116 [0xc2c]

// Reserved address 3120 [0xc30]

// Reserved address 3124 [0xc34]

// Reserved address 3128 [0xc38]

// Reserved address 3132 [0xc3c]

// Reserved address 3136 [0xc40]

// Reserved address 3140 [0xc44]

// Reserved address 3144 [0xc48]

// Reserved address 3148 [0xc4c]

// Reserved address 3152 [0xc50]

// Reserved address 3156 [0xc54]

// Reserved address 3160 [0xc58]

// Reserved address 3164 [0xc5c]

// Reserved address 3168 [0xc60]

// Reserved address 3172 [0xc64]

// Reserved address 3176 [0xc68]

// Reserved address 3180 [0xc6c]

// Reserved address 3184 [0xc70]

// Reserved address 3188 [0xc74]

// Reserved address 3192 [0xc78]

// Reserved address 3196 [0xc7c]

// Reserved address 3200 [0xc80]

// Reserved address 3204 [0xc84]

// Reserved address 3208 [0xc88]

// Reserved address 3212 [0xc8c]

// Reserved address 3216 [0xc90]

// Reserved address 3220 [0xc94]

// Reserved address 3224 [0xc98]

// Reserved address 3228 [0xc9c]

// Reserved address 3232 [0xca0]

// Reserved address 3236 [0xca4]

// Reserved address 3240 [0xca8]

// Reserved address 3244 [0xcac]

// Reserved address 3248 [0xcb0]

// Reserved address 3252 [0xcb4]

// Reserved address 3256 [0xcb8]

// Reserved address 3260 [0xcbc]

// Reserved address 3264 [0xcc0]

// Reserved address 3268 [0xcc4]

// Reserved address 3272 [0xcc8]

// Reserved address 3276 [0xccc]

// Reserved address 3280 [0xcd0]

// Reserved address 3284 [0xcd4]

// Reserved address 3288 [0xcd8]

// Reserved address 3292 [0xcdc]

// Reserved address 3296 [0xce0]

// Reserved address 3300 [0xce4]

// Reserved address 3304 [0xce8]

// Reserved address 3308 [0xcec]

// Reserved address 3312 [0xcf0]

// Reserved address 3316 [0xcf4]

// Reserved address 3320 [0xcf8]

// Reserved address 3324 [0xcfc]

// Reserved address 3328 [0xd00]

// Reserved address 3332 [0xd04]

// Reserved address 3336 [0xd08]

// Reserved address 3340 [0xd0c]

// Reserved address 3344 [0xd10]

// Reserved address 3348 [0xd14]

// Reserved address 3352 [0xd18]

// Reserved address 3356 [0xd1c]

// Reserved address 3360 [0xd20]

// Reserved address 3364 [0xd24]

// Reserved address 3368 [0xd28]

// Reserved address 3372 [0xd2c]

// Reserved address 3376 [0xd30]

// Reserved address 3380 [0xd34]

// Reserved address 3384 [0xd38]

// Reserved address 3388 [0xd3c]

// Reserved address 3392 [0xd40]

// Reserved address 3396 [0xd44]

// Reserved address 3400 [0xd48]

// Reserved address 3404 [0xd4c]

// Reserved address 3408 [0xd50]

// Reserved address 3412 [0xd54]

// Reserved address 3416 [0xd58]

// Reserved address 3420 [0xd5c]

// Reserved address 3424 [0xd60]

// Reserved address 3428 [0xd64]

// Reserved address 3432 [0xd68]

// Reserved address 3436 [0xd6c]

// Reserved address 3440 [0xd70]

// Reserved address 3444 [0xd74]

// Reserved address 3448 [0xd78]

// Reserved address 3452 [0xd7c]

// Reserved address 3456 [0xd80]

// Reserved address 3460 [0xd84]

// Reserved address 3464 [0xd88]

// Reserved address 3468 [0xd8c]

// Reserved address 3472 [0xd90]

// Reserved address 3476 [0xd94]

// Reserved address 3480 [0xd98]

// Reserved address 3484 [0xd9c]

// Reserved address 3488 [0xda0]

// Reserved address 3492 [0xda4]

// Reserved address 3496 [0xda8]

// Reserved address 3500 [0xdac]

// Reserved address 3504 [0xdb0]

// Reserved address 3508 [0xdb4]

// Reserved address 3512 [0xdb8]

// Reserved address 3516 [0xdbc]

// Reserved address 3520 [0xdc0]

// Reserved address 3524 [0xdc4]

// Reserved address 3528 [0xdc8]

// Reserved address 3532 [0xdcc]

// Reserved address 3536 [0xdd0]

// Reserved address 3540 [0xdd4]

// Reserved address 3544 [0xdd8]

// Reserved address 3548 [0xddc]

// Reserved address 3552 [0xde0]

// Reserved address 3556 [0xde4]

// Reserved address 3560 [0xde8]

// Reserved address 3564 [0xdec]

// Reserved address 3568 [0xdf0]

// Reserved address 3572 [0xdf4]

// Reserved address 3576 [0xdf8]

// Reserved address 3580 [0xdfc]

// Reserved address 3584 [0xe00]

// Reserved address 3588 [0xe04]

// Reserved address 3592 [0xe08]

// Reserved address 3596 [0xe0c]

// Reserved address 3600 [0xe10]

// Reserved address 3604 [0xe14]

// Reserved address 3608 [0xe18]

// Reserved address 3612 [0xe1c]

// Reserved address 3616 [0xe20]

// Reserved address 3620 [0xe24]

// Reserved address 3624 [0xe28]

// Reserved address 3628 [0xe2c]

// Reserved address 3632 [0xe30]

// Reserved address 3636 [0xe34]

// Reserved address 3640 [0xe38]

// Reserved address 3644 [0xe3c]

// Reserved address 3648 [0xe40]

// Reserved address 3652 [0xe44]

// Reserved address 3656 [0xe48]

// Reserved address 3660 [0xe4c]

// Reserved address 3664 [0xe50]

// Reserved address 3668 [0xe54]

// Reserved address 3672 [0xe58]

// Reserved address 3676 [0xe5c]

// Reserved address 3680 [0xe60]

// Reserved address 3684 [0xe64]

// Reserved address 3688 [0xe68]

// Reserved address 3692 [0xe6c]

// Reserved address 3696 [0xe70]

// Reserved address 3700 [0xe74]

// Reserved address 3704 [0xe78]

// Reserved address 3708 [0xe7c]

// Reserved address 3712 [0xe80]

// Reserved address 3716 [0xe84]

// Reserved address 3720 [0xe88]

// Reserved address 3724 [0xe8c]

// Reserved address 3728 [0xe90]

// Reserved address 3732 [0xe94]

// Reserved address 3736 [0xe98]

// Reserved address 3740 [0xe9c]

// Reserved address 3744 [0xea0]

// Reserved address 3748 [0xea4]

// Reserved address 3752 [0xea8]

// Reserved address 3756 [0xeac]

// Reserved address 3760 [0xeb0]

// Reserved address 3764 [0xeb4]

// Reserved address 3768 [0xeb8]

// Reserved address 3772 [0xebc]

// Reserved address 3776 [0xec0]

// Reserved address 3780 [0xec4]

// Reserved address 3784 [0xec8]

// Reserved address 3788 [0xecc]

// Reserved address 3792 [0xed0]

// Reserved address 3796 [0xed4]

// Reserved address 3800 [0xed8]

// Reserved address 3804 [0xedc]

// Reserved address 3808 [0xee0]

// Reserved address 3812 [0xee4]

// Reserved address 3816 [0xee8]

// Reserved address 3820 [0xeec]

// Reserved address 3824 [0xef0]

// Reserved address 3828 [0xef4]

// Reserved address 3832 [0xef8]

// Reserved address 3836 [0xefc]

// Reserved address 3840 [0xf00]

// Reserved address 3844 [0xf04]

// Reserved address 3848 [0xf08]

// Reserved address 3852 [0xf0c]

// Reserved address 3856 [0xf10]

// Reserved address 3860 [0xf14]

// Reserved address 3864 [0xf18]

// Reserved address 3868 [0xf1c]

// Reserved address 3872 [0xf20]

// Reserved address 3876 [0xf24]

// Reserved address 3880 [0xf28]

// Reserved address 3884 [0xf2c]

// Reserved address 3888 [0xf30]

// Reserved address 3892 [0xf34]

// Reserved address 3896 [0xf38]

// Reserved address 3900 [0xf3c]

// Reserved address 3904 [0xf40]

// Reserved address 3908 [0xf44]

// Reserved address 3912 [0xf48]

// Reserved address 3916 [0xf4c]

// Reserved address 3920 [0xf50]

// Reserved address 3924 [0xf54]

// Reserved address 3928 [0xf58]

// Reserved address 3932 [0xf5c]

// Reserved address 3936 [0xf60]

// Reserved address 3940 [0xf64]

// Reserved address 3944 [0xf68]

// Reserved address 3948 [0xf6c]

// Reserved address 3952 [0xf70]

// Reserved address 3956 [0xf74]

// Reserved address 3960 [0xf78]

// Reserved address 3964 [0xf7c]

// Reserved address 3968 [0xf80]

// Reserved address 3972 [0xf84]

// Reserved address 3976 [0xf88]

// Reserved address 3980 [0xf8c]

// Reserved address 3984 [0xf90]

// Reserved address 3988 [0xf94]

// Reserved address 3992 [0xf98]

// Reserved address 3996 [0xf9c]

// Reserved address 4000 [0xfa0]

// Reserved address 4004 [0xfa4]

// Reserved address 4008 [0xfa8]

// Reserved address 4012 [0xfac]

// Reserved address 4016 [0xfb0]

// Reserved address 4020 [0xfb4]

// Reserved address 4024 [0xfb8]

// Reserved address 4028 [0xfbc]

// Reserved address 4032 [0xfc0]

// Reserved address 4036 [0xfc4]

// Reserved address 4040 [0xfc8]

// Reserved address 4044 [0xfcc]

// Reserved address 4048 [0xfd0]

// Reserved address 4052 [0xfd4]

// Reserved address 4056 [0xfd8]

// Reserved address 4060 [0xfdc]

// Reserved address 4064 [0xfe0]

// Reserved address 4068 [0xfe4]

// Reserved address 4072 [0xfe8]

// Reserved address 4076 [0xfec]

// Reserved address 4080 [0xff0]

// Reserved address 4084 [0xff4]

// Reserved address 4088 [0xff8]

// Reserved address 4092 [0xffc]

// Reserved address 4096 [0x1000]

// Reserved address 4100 [0x1004]

// Reserved address 4104 [0x1008]

// Reserved address 4108 [0x100c]

// Reserved address 4112 [0x1010]

// Reserved address 4116 [0x1014]

// Reserved address 4120 [0x1018]

// Reserved address 4124 [0x101c]

// Reserved address 4128 [0x1020]

// Reserved address 4132 [0x1024]

// Reserved address 4136 [0x1028]

// Reserved address 4140 [0x102c]

// Reserved address 4144 [0x1030]

// Reserved address 4148 [0x1034]

// Reserved address 4152 [0x1038]

// Reserved address 4156 [0x103c]

// Reserved address 4160 [0x1040]

// Reserved address 4164 [0x1044]

// Reserved address 4168 [0x1048]

// Reserved address 4172 [0x104c]

// Reserved address 4176 [0x1050]

// Reserved address 4180 [0x1054]

// Reserved address 4184 [0x1058]

// Reserved address 4188 [0x105c]

// Reserved address 4192 [0x1060]

// Reserved address 4196 [0x1064]

// Reserved address 4200 [0x1068]

// Reserved address 4204 [0x106c]

// Reserved address 4208 [0x1070]

// Reserved address 4212 [0x1074]

// Reserved address 4216 [0x1078]

// Reserved address 4220 [0x107c]

// Reserved address 4224 [0x1080]

// Reserved address 4228 [0x1084]

// Reserved address 4232 [0x1088]

// Reserved address 4236 [0x108c]

// Reserved address 4240 [0x1090]

// Reserved address 4244 [0x1094]

// Reserved address 4248 [0x1098]

// Reserved address 4252 [0x109c]

// Reserved address 4256 [0x10a0]

// Reserved address 4260 [0x10a4]

// Reserved address 4264 [0x10a8]

// Reserved address 4268 [0x10ac]

// Reserved address 4272 [0x10b0]

// Reserved address 4276 [0x10b4]

// Reserved address 4280 [0x10b8]

// Reserved address 4284 [0x10bc]

// Reserved address 4288 [0x10c0]

// Reserved address 4292 [0x10c4]

// Reserved address 4296 [0x10c8]

// Reserved address 4300 [0x10cc]

// Reserved address 4304 [0x10d0]

// Reserved address 4308 [0x10d4]

// Reserved address 4312 [0x10d8]

// Reserved address 4316 [0x10dc]

// Reserved address 4320 [0x10e0]

// Reserved address 4324 [0x10e4]

// Reserved address 4328 [0x10e8]

// Reserved address 4332 [0x10ec]

// Reserved address 4336 [0x10f0]

// Reserved address 4340 [0x10f4]

// Reserved address 4344 [0x10f8]

// Reserved address 4348 [0x10fc]

// Reserved address 4352 [0x1100]

// Reserved address 4356 [0x1104]

// Reserved address 4360 [0x1108]

// Reserved address 4364 [0x110c]

// Reserved address 4368 [0x1110]

// Reserved address 4372 [0x1114]

// Reserved address 4376 [0x1118]

// Reserved address 4380 [0x111c]

// Reserved address 4384 [0x1120]

// Reserved address 4388 [0x1124]

// Reserved address 4392 [0x1128]

// Reserved address 4396 [0x112c]

// Reserved address 4400 [0x1130]

// Reserved address 4404 [0x1134]

// Reserved address 4408 [0x1138]

// Reserved address 4412 [0x113c]

// Reserved address 4416 [0x1140]

// Reserved address 4420 [0x1144]

// Reserved address 4424 [0x1148]

// Reserved address 4428 [0x114c]

// Reserved address 4432 [0x1150]

// Reserved address 4436 [0x1154]

// Reserved address 4440 [0x1158]

// Reserved address 4444 [0x115c]

// Reserved address 4448 [0x1160]

// Reserved address 4452 [0x1164]

// Reserved address 4456 [0x1168]

// Reserved address 4460 [0x116c]

// Reserved address 4464 [0x1170]

// Reserved address 4468 [0x1174]

// Reserved address 4472 [0x1178]

// Reserved address 4476 [0x117c]

// Reserved address 4480 [0x1180]

// Reserved address 4484 [0x1184]

// Reserved address 4488 [0x1188]

// Reserved address 4492 [0x118c]

// Reserved address 4496 [0x1190]

// Reserved address 4500 [0x1194]

// Reserved address 4504 [0x1198]

// Reserved address 4508 [0x119c]

// Reserved address 4512 [0x11a0]

// Reserved address 4516 [0x11a4]

// Reserved address 4520 [0x11a8]

// Reserved address 4524 [0x11ac]

// Reserved address 4528 [0x11b0]

// Reserved address 4532 [0x11b4]

// Reserved address 4536 [0x11b8]

// Reserved address 4540 [0x11bc]

// Reserved address 4544 [0x11c0]

// Reserved address 4548 [0x11c4]

// Reserved address 4552 [0x11c8]

// Reserved address 4556 [0x11cc]

// Reserved address 4560 [0x11d0]

// Reserved address 4564 [0x11d4]

// Reserved address 4568 [0x11d8]

// Reserved address 4572 [0x11dc]

// Reserved address 4576 [0x11e0]

// Reserved address 4580 [0x11e4]

// Reserved address 4584 [0x11e8]

// Reserved address 4588 [0x11ec]

// Reserved address 4592 [0x11f0]

// Reserved address 4596 [0x11f4]

// Reserved address 4600 [0x11f8]

// Reserved address 4604 [0x11fc]

// Reserved address 4608 [0x1200]

// Reserved address 4612 [0x1204]

// Reserved address 4616 [0x1208]

// Reserved address 4620 [0x120c]

// Reserved address 4624 [0x1210]

// Reserved address 4628 [0x1214]

// Reserved address 4632 [0x1218]

// Reserved address 4636 [0x121c]

// Reserved address 4640 [0x1220]

// Reserved address 4644 [0x1224]

// Reserved address 4648 [0x1228]

// Reserved address 4652 [0x122c]

// Reserved address 4656 [0x1230]

// Reserved address 4660 [0x1234]

// Reserved address 4664 [0x1238]

// Reserved address 4668 [0x123c]

// Reserved address 4672 [0x1240]

// Reserved address 4676 [0x1244]

// Reserved address 4680 [0x1248]

// Reserved address 4684 [0x124c]

// Reserved address 4688 [0x1250]

// Reserved address 4692 [0x1254]

// Reserved address 4696 [0x1258]

// Reserved address 4700 [0x125c]

// Reserved address 4704 [0x1260]

// Reserved address 4708 [0x1264]

// Reserved address 4712 [0x1268]

// Reserved address 4716 [0x126c]

// Reserved address 4720 [0x1270]

// Reserved address 4724 [0x1274]

// Reserved address 4728 [0x1278]

// Reserved address 4732 [0x127c]

// Reserved address 4736 [0x1280]

// Reserved address 4740 [0x1284]

// Reserved address 4744 [0x1288]

// Reserved address 4748 [0x128c]

// Reserved address 4752 [0x1290]

// Reserved address 4756 [0x1294]

// Reserved address 4760 [0x1298]

// Reserved address 4764 [0x129c]

// Reserved address 4768 [0x12a0]

// Reserved address 4772 [0x12a4]

// Reserved address 4776 [0x12a8]

// Reserved address 4780 [0x12ac]

// Reserved address 4784 [0x12b0]

// Reserved address 4788 [0x12b4]

// Reserved address 4792 [0x12b8]

// Reserved address 4796 [0x12bc]

// Reserved address 4800 [0x12c0]

// Reserved address 4804 [0x12c4]

// Reserved address 4808 [0x12c8]

// Reserved address 4812 [0x12cc]

// Reserved address 4816 [0x12d0]

// Reserved address 4820 [0x12d4]

// Reserved address 4824 [0x12d8]

// Reserved address 4828 [0x12dc]

// Reserved address 4832 [0x12e0]

// Reserved address 4836 [0x12e4]

// Reserved address 4840 [0x12e8]

// Reserved address 4844 [0x12ec]

// Reserved address 4848 [0x12f0]

// Reserved address 4852 [0x12f4]

// Reserved address 4856 [0x12f8]

// Reserved address 4860 [0x12fc]

// Reserved address 4864 [0x1300]

// Reserved address 4868 [0x1304]

// Reserved address 4872 [0x1308]

// Reserved address 4876 [0x130c]

// Reserved address 4880 [0x1310]

// Reserved address 4884 [0x1314]

// Reserved address 4888 [0x1318]

// Reserved address 4892 [0x131c]

// Reserved address 4896 [0x1320]

// Reserved address 4900 [0x1324]

// Reserved address 4904 [0x1328]

// Reserved address 4908 [0x132c]

// Reserved address 4912 [0x1330]

// Reserved address 4916 [0x1334]

// Reserved address 4920 [0x1338]

// Reserved address 4924 [0x133c]

// Reserved address 4928 [0x1340]

// Reserved address 4932 [0x1344]

// Reserved address 4936 [0x1348]

// Reserved address 4940 [0x134c]

// Reserved address 4944 [0x1350]

// Reserved address 4948 [0x1354]

// Reserved address 4952 [0x1358]

// Reserved address 4956 [0x135c]

// Reserved address 4960 [0x1360]

// Register XUSB_PADCTL_HOST_AXI_SEC0_0
#define XUSB_PADCTL_HOST_AXI_SEC0_0                     _MK_ADDR_CONST(0x1364)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_SECURE                      0x1
#define XUSB_PADCTL_HOST_AXI_SEC0_0_SCR                         0
#define XUSB_PADCTL_HOST_AXI_SEC0_0_WORD_COUNT                  0x1
#define XUSB_PADCTL_HOST_AXI_SEC0_0_RESET_VAL                   _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_RESET_MASK                  _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_READ_MASK                   _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_WRITE_MASK                  _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_RANGE                       0:0
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_WOFFSET                     0x0
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_RANGE                       4:4
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_WOFFSET                     0x0
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_HOST_AXI_SEC2_0
#define XUSB_PADCTL_HOST_AXI_SEC2_0                     _MK_ADDR_CONST(0x1368)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_SECURE                      0x0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_SCR                         0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_WORD_COUNT                  0x1
#define XUSB_PADCTL_HOST_AXI_SEC2_0_RESET_VAL                   _MK_MASK_CONST(0x1013)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_RESET_MASK                  _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_READ_MASK                   _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_WRITE_MASK                  _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_FIELD                       _MK_FIELD_CONST(0xf, XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_RANGE                       3:0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_WOFFSET                     0x0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_DEFAULT                     _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_SHIFT                  _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_RANGE                  4:4
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_DEFAULT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_SHIFT                       _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_FIELD                       _MK_FIELD_CONST(0xf, XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_RANGE                       11:8
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_WOFFSET                     0x0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_SHIFT                  _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_RANGE                  12:12
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_DEFAULT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 4972 [0x136c]

// Reserved address 4976 [0x1370]

// Reserved address 4980 [0x1374]

// Reserved address 4984 [0x1378]

// Register XUSB_PADCTL_DEV_AXI_SEC0_0
#define XUSB_PADCTL_DEV_AXI_SEC0_0                      _MK_ADDR_CONST(0x137c)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_SECURE                       0x1
#define XUSB_PADCTL_DEV_AXI_SEC0_0_SCR                  0
#define XUSB_PADCTL_DEV_AXI_SEC0_0_WORD_COUNT                   0x1
#define XUSB_PADCTL_DEV_AXI_SEC0_0_RESET_VAL                    _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_RESET_MASK                   _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_READ_MASK                    _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_WRITE_MASK                   _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_RANGE                        0:0
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_WOFFSET                      0x0
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_SHIFT                        _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_RANGE                        4:4
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_WOFFSET                      0x0
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register XUSB_PADCTL_DEV_AXI_SEC2_0
#define XUSB_PADCTL_DEV_AXI_SEC2_0                      _MK_ADDR_CONST(0x1380)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_SECURE                       0x0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_SCR                  0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_WORD_COUNT                   0x1
#define XUSB_PADCTL_DEV_AXI_SEC2_0_RESET_VAL                    _MK_MASK_CONST(0x1013)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_RESET_MASK                   _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_READ_MASK                    _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_WRITE_MASK                   _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_RANGE                        3:0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_WOFFSET                      0x0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_DEFAULT                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_RANGE                   4:4
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_WOFFSET                 0x0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_SHIFT                        _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_RANGE                        11:8
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_WOFFSET                      0x0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_SHIFT                   _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_RANGE                   12:12
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_WOFFSET                 0x0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Reserved address 4996 [0x1384]

// Reserved address 5000 [0x1388]

// Reserved address 5004 [0x138c]

// Reserved address 5008 [0x1390]

//
// REGISTER LIST
//
#define LIST_ARXUSB_PADCTL_REGS(_op_) \
_op_(XUSB_PADCTL_BOOT_MEDIA_0) \
_op_(XUSB_PADCTL_USB2_PAD_MUX_0) \
_op_(XUSB_PADCTL_USB2_PORT_CAP_0) \
_op_(XUSB_PADCTL_SS_PORT_CAP_0) \
_op_(XUSB_PADCTL_USB2_OC_MAP_0) \
_op_(XUSB_PADCTL_SS_OC_MAP_0) \
_op_(XUSB_PADCTL_VBUS_OC_MAP_0) \
_op_(XUSB_PADCTL_OC_DET_0) \
_op_(XUSB_PADCTL_ELPG_PROGRAM_0_0) \
_op_(XUSB_PADCTL_ELPG_PROGRAM_1_0) \
_op_(XUSB_PADCTL_PM_SPARE_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0) \
_op_(XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0) \
_op_(XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0) \
_op_(XUSB_PADCTL_HSIC_PAD0_CTL_0_0) \
_op_(XUSB_PADCTL_HSIC_PAD0_CTL_1_0) \
_op_(XUSB_PADCTL_HSIC_PAD0_CTL_2_0) \
_op_(XUSB_PADCTL_HSIC_PAD1_CTL_0_0) \
_op_(XUSB_PADCTL_HSIC_PAD1_CTL_1_0) \
_op_(XUSB_PADCTL_HSIC_PAD1_CTL_2_0) \
_op_(XUSB_PADCTL_HSIC_PAD_TRK_CTL_0) \
_op_(XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0) \
_op_(XUSB_PADCTL_USB2_VBUS_ID_0) \
_op_(XUSB_PADCTL_HOST_AXI_SEC0_0) \
_op_(XUSB_PADCTL_HOST_AXI_SEC2_0) \
_op_(XUSB_PADCTL_DEV_AXI_SEC0_0) \
_op_(XUSB_PADCTL_DEV_AXI_SEC2_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_XUSB_PADCTL        0x00000000

//
// ARXUSB_PADCTL REGISTER BANKS
//

#define XUSB_PADCTL0_FIRST_REG 0x0000 // XUSB_PADCTL_BOOT_MEDIA_0
#define XUSB_PADCTL0_LAST_REG 0x0028 // XUSB_PADCTL_PM_SPARE_0
#define XUSB_PADCTL1_FIRST_REG 0x0080 // XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0
#define XUSB_PADCTL1_LAST_REG 0x0094 // XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0
#define XUSB_PADCTL2_FIRST_REG 0x00c0 // XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0
#define XUSB_PADCTL2_LAST_REG 0x00d4 // XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0
#define XUSB_PADCTL3_FIRST_REG 0x0100 // XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0
#define XUSB_PADCTL3_LAST_REG 0x0114 // XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0
#define XUSB_PADCTL4_FIRST_REG 0x0140 // XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0
#define XUSB_PADCTL4_LAST_REG 0x0154 // XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0
#define XUSB_PADCTL5_FIRST_REG 0x0280 // XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0
#define XUSB_PADCTL5_LAST_REG 0x0288 // XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
#define XUSB_PADCTL6_FIRST_REG 0x0300 // XUSB_PADCTL_HSIC_PAD0_CTL_0_0
#define XUSB_PADCTL6_LAST_REG 0x0308 // XUSB_PADCTL_HSIC_PAD0_CTL_2_0
#define XUSB_PADCTL7_FIRST_REG 0x0320 // XUSB_PADCTL_HSIC_PAD1_CTL_0_0
#define XUSB_PADCTL7_LAST_REG 0x0328 // XUSB_PADCTL_HSIC_PAD1_CTL_2_0
#define XUSB_PADCTL8_FIRST_REG 0x0340 // XUSB_PADCTL_HSIC_PAD_TRK_CTL_0
#define XUSB_PADCTL8_LAST_REG 0x0344 // XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
#define XUSB_PADCTL9_FIRST_REG 0x0360 // XUSB_PADCTL_USB2_VBUS_ID_0
#define XUSB_PADCTL9_LAST_REG 0x0360 // XUSB_PADCTL_USB2_VBUS_ID_0
#define XUSB_PADCTL10_FIRST_REG 0x1364 // XUSB_PADCTL_HOST_AXI_SEC0_0
#define XUSB_PADCTL10_LAST_REG 0x1368 // XUSB_PADCTL_HOST_AXI_SEC2_0
#define XUSB_PADCTL11_FIRST_REG 0x137c // XUSB_PADCTL_DEV_AXI_SEC0_0
#define XUSB_PADCTL11_LAST_REG 0x1380 // XUSB_PADCTL_DEV_AXI_SEC2_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARXUSB_PADCTL_H_INC_
