#ifndef ARDEV_T_FPCI_XUSB_DEV_0_H_
#define ARDEV_T_FPCI_XUSB_DEV_0_H_

// generated by manual_ref_to_h.py from dev_t_fpci_xusb_dev_0.ref - do not edit

//
// Copyright (c) 2011 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
// 
// 
// 
// 
// 
// 
// 
// 
// 
//                       MCP XUSB PCI Config Reference Manual
// 
//                         Karthik Mani (kmani@nvidia.com)
// 
//                                Nvidia Corporation
// 
//                            2701 San Tomas Expressway
// 
//                              Santa Clara, CA 95050
// 
// 
// 
//                                       $Id: //dev/stdif/xusb/1.2/manuals/dev_t_fpci_xusb_dev.ref#5 $
//                                      $Date: 2014/08/13 $
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// .ADDR_SPACE DEV_CFG
// 
// 
// 


#define XUSB_DEV_CFG_0_0                                   _MK_ADDR_CONST(0x00000000)
#define XUSB_DEV_CFG_0_0_SECURE                            0
#define XUSB_DEV_CFG_0_0_WORD_COUNT                        1
#define XUSB_DEV_CFG_0_0_RESET_VAL                         _MK_MASK_CONST(0x10ff10de)
#define XUSB_DEV_CFG_0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x10ff10de)
#define XUSB_DEV_CFG_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_0_0_CLEAR_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_0_0_TGL_MASK                          _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_0_0_VENDOR_ID_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_0_0_VENDOR_ID_FIELD                   (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_CFG_0_0_VENDOR_ID_SHIFT)
#define XUSB_DEV_CFG_0_0_VENDOR_ID_RANGE                   15:0
#define XUSB_DEV_CFG_0_0_VENDOR_ID_WOFFSET                 0
#define XUSB_DEV_CFG_0_0_VENDOR_ID_DEFAULT                 (_MK_MASK_CONST(0x000010DE)
#define XUSB_DEV_CFG_0_0_VENDOR_ID_DEFAULT_MASK            (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_0_0_VENDOR_ID_SW_DEFAULT              (_MK_MASK_CONST(0x000010DE)
#define XUSB_DEV_CFG_0_0_VENDOR_ID_SW_DEFAULT_MASK         (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_0_0_VENDOR_ID_NVIDIA                  _MK_ENUM_CONST(0x000010DE)
#define XUSB_DEV_CFG_0_0_DEVICE_ID_UNIT_SHIFT               _MK_SHIFT_CONST(16)
#define XUSB_DEV_CFG_0_0_DEVICE_ID_UNIT_FIELD              (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_CFG_0_0_DEVICE_ID_UNIT_SHIFT)
#define XUSB_DEV_CFG_0_0_DEVICE_ID_UNIT_RANGE              31:16
#define XUSB_DEV_CFG_0_0_DEVICE_ID_UNIT_WOFFSET            0
#define XUSB_DEV_CFG_0_0_DEVICE_ID_UNIT_DEFAULT            (_MK_MASK_CONST(0x000010FF)
#define XUSB_DEV_CFG_0_0_DEVICE_ID_UNIT_DEFAULT_MASK       (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_0_0_DEVICE_ID_UNIT_SW_DEFAULT         (_MK_MASK_CONST(0x000010FF)
#define XUSB_DEV_CFG_0_0_DEVICE_ID_UNIT_SW_DEFAULT_MASK    (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_0_0_DEVICE_ID_UNIT_XUSB_DEV           _MK_ENUM_CONST(0x000010FF)


// 
// // Else tlit2
// // Else tlit3
// // Tlit4 / T186
// 
// 
// 
// .TITLE PCI Device Control Register 04h
//      The Device Control Command register provides coarse control over a
// device's ability to generate and respond to PCI cycles.
// .FIELD IO_SPACE
//      The IO_SPACE bit indicates that the device will respond to I/O space
// accesses.  A value of 0 disables the device response.  A value of 1 allows the
// device to respond to I/O space accesses.  IO_SPACE is writable.
// .FIELD MEMORY_SPACE
//      The MEMORY_SPACE bit indicates that the device will respond to memory
// space accesses.  A value of 0 disables the device response.  A value of 1
// allows the device to respond to Memory space accesses.  MEMORY_SPACE is
// writable.
// .FIELD BUS_MASTER
//      The BUS_MASTER bit indicates that the device can act as a master on the
// PCI bus.  A value of 0 disables the device from generating PCI accesses.  A
// value of 1 allows the device to behave as a bus master.  BUS_MASTER is
// writable.
// .FIELD WRITE_AND_INVAL
//      The WRITE_AND_INVAL bit indicates that the device can use the Memory
// Write and Invalidate command when the transfer is aligned and 16 bytes and the
// contents of the Cache Line Size Register is 4 DWORDS.  When this bit is 1,
// masters may generate the command.  When it is 0, Memory Write must be used
// instead.  State after RST# is 0.  This bit must be implemented by master
// devices that can generate the Memory Write and Invalidate command.
// .FIELD PALETTE_SNOOP
//      The PALETTE_SNOOP bit indicates that VGA compatible devices should snoop
// their palette registers.  When this bit is set, special palette snooping
// behavior is enabled (ie, device must not respond).  When the bit is reset, the
// device should treat palette accesses like all other accesses.  VGA compatible
// devices should implement this bit.  PALETTE_SNOOP is writable.
// .FIELD INTR_DISABLE
//      The INTR_DISABLE bit indicates that it could disable the device/function
// from asserting INTx#. A value of 0 enables the assertion of INTx#, and a value
// of 1 disables the assertion of INTx# signal.
// 
//      The Device Status register is used to record status information for PCI
// bus related events.
// .FIELD INTR_STATUS
//      The INTR_STATUS bit is read-only and reflects the state of the interrupt
// in the device/function. Only when the INTR_DISABLE bit in the command register
// is a 0 and this INTR_STATUS bit is a 1, will the device's/function's INTx#
// signal be asserted. Setting the INTR_DISABLE bit to 1 has no effect on the
// state of this bit.
// .FIELD CAPLIST
//      The CAPLIST bit indicates that the device configuration space includes a
// capabilities list starting at the offset indicated by T_XUSB_DEV_CFG_13.
// .FIELD 66MHZ
//      The 66MHZ bit indicates that the device is capable of 66 MHz PCI Bus
// operation.  This value is initialized by a strapping bit.
// .FIELD FAST_BACK2BACK
//      The FAST_BACK2BACK bit indicates that the device is capable of handling
// back-to-back transfers when the transactions are not to the same agent.  This
// bit can be set to 1 if the device can accept these transactions, and must be
// set to 0 otherwise.
// .FIELD DEVSEL_TIMING
//      The DEVSEL_TIMING bits contain the timing of DEVSEL#.  There are three
// allowable timings for assertion of DEVSEL#.  These are encoded as 00b for
// fast, 01b for medium, and 10b for slow (11b is reserved).  These bits are read
// only and must indicate the slowest time that a device asserts DEVSEL# for any
// bus command except Configuration Read and Configuration Write.  FPCI positive
// decode device are required to respond with fast DEVSEL# (0-cycle). Only the
// subtractive FPCI function will respond with medium DEVSEL# to accept the
// cycle for the subtractive bus.
// .FIELD SIGNALED_TARGET
//      The SIGNALED_TARGET bit indicates that the device has terminated a
// transaction with target-abort.  Devices that will never signal target-abort
// do not need to implement this bit.  When this bit is set, an interrupt is
// signaled in the PBUS_INTR_0 register.
// .FIELD RECEIVED_TARGET
//      The RECEIVED_TARGET bit indicates that a master device's transaction was
// terminated with a target-abort.  All master devices must implement this bit.
// When this bit is set, an interrupt is signaled in the PBUS_INTR_0 register.
// .FIELD RECEIVED_MASTER
//      The RECEIVED_MASTER bit indicates that a master device's transaction
// (except for Special Cycle) was terminated with a master-abort.  This means
// that no device on the PCI bus responded to the address of the mastered
// transaction.  All master devices must implement this bit.  When this bit is
// set, an interrupt is signaled in the PBUS_INTR_0 register.
// /*         Regarding the SIGNALED_TARGET, RECEIVED_TARGET, and RECEIVED_MASTER bits,
// unfortunately, there is no way of knowing what the offending address of the bus
// error was, except by using a logic analyzer.*/
// .LABEL PCI_CONFIG
// .FIELD SIGNALED_SERR
//      The SIGNALED_SERR bit indicates that the device has asserted SERR#.
// .FIELD DETECTED_PERR
//      The DETECTED_PERR bit indicates that the device has detected a parity
// error, even if parity error handing is disabled. (Bit 6 -
// T_CONFIG_FPCI_PERR_DISABLED)
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0|0|0|0|0|0 0|0|1|0|1|1|0 0 0 0|0 0 0 0 0 0 0|0|0 0 0|0|0| | |0| CFG_1
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 


#define XUSB_DEV_CFG_1_0                                   _MK_ADDR_CONST(0x00000004)
#define XUSB_DEV_CFG_1_0_SECURE                            0
#define XUSB_DEV_CFG_1_0_WORD_COUNT                        1
#define XUSB_DEV_CFG_1_0_RESET_VAL                         _MK_MASK_CONST(0xb00000)
#define XUSB_DEV_CFG_1_0_RESET_MASK                        _MK_MASK_CONST(0xffb007ff)
#define XUSB_DEV_CFG_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0xb00000)
#define XUSB_DEV_CFG_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffb007ff)
#define XUSB_DEV_CFG_1_0_READ_MASK                         _MK_MASK_CONST(0xffb807ff)
#define XUSB_DEV_CFG_1_0_WRITE_MASK                        _MK_MASK_CONST(0x407)
#define XUSB_DEV_CFG_1_0_CLEAR_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_1_0_TGL_MASK                          _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_1_0_IO_SPACE_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_1_0_IO_SPACE_FIELD                    (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_IO_SPACE_SHIFT)
#define XUSB_DEV_CFG_1_0_IO_SPACE_RANGE                    0:0
#define XUSB_DEV_CFG_1_0_IO_SPACE_WOFFSET                  0
#define XUSB_DEV_CFG_1_0_IO_SPACE_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_IO_SPACE_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_IO_SPACE_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_IO_SPACE_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_IO_SPACE__WRNPRDCHK               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_IO_SPACE_DISABLED                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_IO_SPACE_ENABLED                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_MEMORY_SPACE_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_DEV_CFG_1_0_MEMORY_SPACE_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_MEMORY_SPACE_SHIFT)
#define XUSB_DEV_CFG_1_0_MEMORY_SPACE_RANGE                1:1
#define XUSB_DEV_CFG_1_0_MEMORY_SPACE_WOFFSET              0
#define XUSB_DEV_CFG_1_0_MEMORY_SPACE_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_MEMORY_SPACE_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_MEMORY_SPACE_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_MEMORY_SPACE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_MEMORY_SPACE__WRNPRDCHK           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_MEMORY_SPACE_DISABLED             _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_MEMORY_SPACE_ENABLED              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_BUS_MASTER_SHIFT                   _MK_SHIFT_CONST(2)
#define XUSB_DEV_CFG_1_0_BUS_MASTER_FIELD                  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_BUS_MASTER_SHIFT)
#define XUSB_DEV_CFG_1_0_BUS_MASTER_RANGE                  2:2
#define XUSB_DEV_CFG_1_0_BUS_MASTER_WOFFSET                0
#define XUSB_DEV_CFG_1_0_BUS_MASTER_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_BUS_MASTER_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_BUS_MASTER_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_BUS_MASTER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_BUS_MASTER__WRNPRDCHK             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_BUS_MASTER_DISABLED               _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_BUS_MASTER_ENABLED                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_SPECIAL_CYCLE_SHIFT                _MK_SHIFT_CONST(3)
#define XUSB_DEV_CFG_1_0_SPECIAL_CYCLE_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_SPECIAL_CYCLE_SHIFT)
#define XUSB_DEV_CFG_1_0_SPECIAL_CYCLE_RANGE               3:3
#define XUSB_DEV_CFG_1_0_SPECIAL_CYCLE_WOFFSET             0
#define XUSB_DEV_CFG_1_0_SPECIAL_CYCLE_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SPECIAL_CYCLE_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_SPECIAL_CYCLE_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SPECIAL_CYCLE_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_SPECIAL_CYCLE_DISABLED            _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SPECIAL_CYCLE_ENABLED             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_WRITE_AND_INVAL_SHIFT              _MK_SHIFT_CONST(4)
#define XUSB_DEV_CFG_1_0_WRITE_AND_INVAL_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_WRITE_AND_INVAL_SHIFT)
#define XUSB_DEV_CFG_1_0_WRITE_AND_INVAL_RANGE             4:4
#define XUSB_DEV_CFG_1_0_WRITE_AND_INVAL_WOFFSET           0
#define XUSB_DEV_CFG_1_0_WRITE_AND_INVAL_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_WRITE_AND_INVAL_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_WRITE_AND_INVAL_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_WRITE_AND_INVAL_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_WRITE_AND_INVAL_DISABLED          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_WRITE_AND_INVAL_ENABLED           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_PALETTE_SNOOP_SHIFT                _MK_SHIFT_CONST(5)
#define XUSB_DEV_CFG_1_0_PALETTE_SNOOP_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_PALETTE_SNOOP_SHIFT)
#define XUSB_DEV_CFG_1_0_PALETTE_SNOOP_RANGE               5:5
#define XUSB_DEV_CFG_1_0_PALETTE_SNOOP_WOFFSET             0
#define XUSB_DEV_CFG_1_0_PALETTE_SNOOP_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_PALETTE_SNOOP_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_PALETTE_SNOOP_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_PALETTE_SNOOP_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_PALETTE_SNOOP_DISABLED            _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_PALETTE_SNOOP_ENABLED             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_PERR_SHIFT                         _MK_SHIFT_CONST(6)
#define XUSB_DEV_CFG_1_0_PERR_FIELD                        (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_PERR_SHIFT)
#define XUSB_DEV_CFG_1_0_PERR_RANGE                        6:6
#define XUSB_DEV_CFG_1_0_PERR_WOFFSET                      0
#define XUSB_DEV_CFG_1_0_PERR_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_PERR_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_PERR_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_PERR_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_PERR_DISABLED                     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_PERR_ENABLED                      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_STEP_SHIFT                         _MK_SHIFT_CONST(7)
#define XUSB_DEV_CFG_1_0_STEP_FIELD                        (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_STEP_SHIFT)
#define XUSB_DEV_CFG_1_0_STEP_RANGE                        7:7
#define XUSB_DEV_CFG_1_0_STEP_WOFFSET                      0
#define XUSB_DEV_CFG_1_0_STEP_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_STEP_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_STEP_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_STEP_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_STEP_DISABLED                     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_STEP_ENABLED                      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_SERR_SHIFT                         _MK_SHIFT_CONST(8)
#define XUSB_DEV_CFG_1_0_SERR_FIELD                        (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_SERR_SHIFT)
#define XUSB_DEV_CFG_1_0_SERR_RANGE                        8:8
#define XUSB_DEV_CFG_1_0_SERR_WOFFSET                      0
#define XUSB_DEV_CFG_1_0_SERR_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SERR_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_SERR_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SERR_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_SERR_DISABLED                     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SERR_ENABLED                      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_BACK2BACK_SHIFT                    _MK_SHIFT_CONST(9)
#define XUSB_DEV_CFG_1_0_BACK2BACK_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_BACK2BACK_SHIFT)
#define XUSB_DEV_CFG_1_0_BACK2BACK_RANGE                   9:9
#define XUSB_DEV_CFG_1_0_BACK2BACK_WOFFSET                 0
#define XUSB_DEV_CFG_1_0_BACK2BACK_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_BACK2BACK_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_BACK2BACK_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_BACK2BACK_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_BACK2BACK_DISABLED                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_BACK2BACK_ENABLED                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_INTR_DISABLE_SHIFT                 _MK_SHIFT_CONST(10)
#define XUSB_DEV_CFG_1_0_INTR_DISABLE_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_INTR_DISABLE_SHIFT)
#define XUSB_DEV_CFG_1_0_INTR_DISABLE_RANGE                10:10
#define XUSB_DEV_CFG_1_0_INTR_DISABLE_WOFFSET              0
#define XUSB_DEV_CFG_1_0_INTR_DISABLE_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_INTR_DISABLE_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_INTR_DISABLE_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_INTR_DISABLE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_INTR_DISABLE_ON                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_INTR_DISABLE_OFF                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_INTR_STATUS_SHIFT                  _MK_SHIFT_CONST(19)
#define XUSB_DEV_CFG_1_0_INTR_STATUS_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_INTR_STATUS_SHIFT)
#define XUSB_DEV_CFG_1_0_INTR_STATUS_RANGE                 19:19
#define XUSB_DEV_CFG_1_0_INTR_STATUS_WOFFSET               0
#define XUSB_DEV_CFG_1_0_INTR_STATUS_0                     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_INTR_STATUS_1                     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_CAPLIST_SHIFT                      _MK_SHIFT_CONST(20)
#define XUSB_DEV_CFG_1_0_CAPLIST_FIELD                     (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_CAPLIST_SHIFT)
#define XUSB_DEV_CFG_1_0_CAPLIST_RANGE                     20:20
#define XUSB_DEV_CFG_1_0_CAPLIST_WOFFSET                   0
#define XUSB_DEV_CFG_1_0_CAPLIST_DEFAULT                   (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_CAPLIST_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_CAPLIST_SW_DEFAULT                (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_CAPLIST_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_CAPLIST_NOT_PRESENT               _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_CAPLIST_PRESENT                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_66MHZ_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_DEV_CFG_1_0_66MHZ_FIELD                       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_66MHZ_SHIFT)
#define XUSB_DEV_CFG_1_0_66MHZ_RANGE                       21:21
#define XUSB_DEV_CFG_1_0_66MHZ_WOFFSET                     0
#define XUSB_DEV_CFG_1_0_66MHZ_DEFAULT                     (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_66MHZ_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_66MHZ_SW_DEFAULT                  (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_66MHZ_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_66MHZ_INCAPABLE                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_66MHZ_CAPABLE                     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_FAST_BACK2BACK_SHIFT               _MK_SHIFT_CONST(23)
#define XUSB_DEV_CFG_1_0_FAST_BACK2BACK_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_FAST_BACK2BACK_SHIFT)
#define XUSB_DEV_CFG_1_0_FAST_BACK2BACK_RANGE              23:23
#define XUSB_DEV_CFG_1_0_FAST_BACK2BACK_WOFFSET            0
#define XUSB_DEV_CFG_1_0_FAST_BACK2BACK_DEFAULT            (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_FAST_BACK2BACK_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_FAST_BACK2BACK_SW_DEFAULT         (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_FAST_BACK2BACK_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_FAST_BACK2BACK_INCAPABLE          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_FAST_BACK2BACK_CAPABLE            _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_SHIFT             _MK_SHIFT_CONST(24)
#define XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_FIELD            (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_SHIFT)
#define XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_RANGE            24:24
#define XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_WOFFSET          0
#define XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_SW_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_SW_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_NOT_ACTIVE       _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_ACTIVE           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_MASTER_DATA_PERR_CLEAR            _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_DEVSEL_TIMING_SHIFT                _MK_SHIFT_CONST(25)
#define XUSB_DEV_CFG_1_0_DEVSEL_TIMING_FIELD               (_MK_SHIFT_CONST(0x3) << XUSB_DEV_CFG_1_0_DEVSEL_TIMING_SHIFT)
#define XUSB_DEV_CFG_1_0_DEVSEL_TIMING_RANGE               26:25
#define XUSB_DEV_CFG_1_0_DEVSEL_TIMING_WOFFSET             0
#define XUSB_DEV_CFG_1_0_DEVSEL_TIMING_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_DEVSEL_TIMING_DEFAULT_MASK        (_MK_MASK_CONST(0x3)
#define XUSB_DEV_CFG_1_0_DEVSEL_TIMING_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_DEVSEL_TIMING_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x3)
#define XUSB_DEV_CFG_1_0_DEVSEL_TIMING_FAST                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_DEVSEL_TIMING_MEDIUM              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_DEVSEL_TIMING_SLOW                _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_CFG_1_0_SIGNALED_TARGET_SHIFT              _MK_SHIFT_CONST(27)
#define XUSB_DEV_CFG_1_0_SIGNALED_TARGET_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_SIGNALED_TARGET_SHIFT)
#define XUSB_DEV_CFG_1_0_SIGNALED_TARGET_RANGE             27:27
#define XUSB_DEV_CFG_1_0_SIGNALED_TARGET_WOFFSET           0
#define XUSB_DEV_CFG_1_0_SIGNALED_TARGET_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SIGNALED_TARGET_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_SIGNALED_TARGET_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SIGNALED_TARGET_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_SIGNALED_TARGET_NO_ABORT          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SIGNALED_TARGET_ABORT             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_SIGNALED_TARGET_CLEAR             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_RECEIVED_TARGET_SHIFT              _MK_SHIFT_CONST(28)
#define XUSB_DEV_CFG_1_0_RECEIVED_TARGET_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_RECEIVED_TARGET_SHIFT)
#define XUSB_DEV_CFG_1_0_RECEIVED_TARGET_RANGE             28:28
#define XUSB_DEV_CFG_1_0_RECEIVED_TARGET_WOFFSET           0
#define XUSB_DEV_CFG_1_0_RECEIVED_TARGET_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_RECEIVED_TARGET_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_RECEIVED_TARGET_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_RECEIVED_TARGET_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_RECEIVED_TARGET_NO_ABORT          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_RECEIVED_TARGET_ABORT             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_RECEIVED_TARGET_CLEAR             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_RECEIVED_MASTER_SHIFT              _MK_SHIFT_CONST(29)
#define XUSB_DEV_CFG_1_0_RECEIVED_MASTER_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_RECEIVED_MASTER_SHIFT)
#define XUSB_DEV_CFG_1_0_RECEIVED_MASTER_RANGE             29:29
#define XUSB_DEV_CFG_1_0_RECEIVED_MASTER_WOFFSET           0
#define XUSB_DEV_CFG_1_0_RECEIVED_MASTER_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_RECEIVED_MASTER_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_RECEIVED_MASTER_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_RECEIVED_MASTER_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_RECEIVED_MASTER_NO_ABORT          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_RECEIVED_MASTER_ABORT             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_RECEIVED_MASTER_CLEAR             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_SIGNALED_SERR_SHIFT                _MK_SHIFT_CONST(30)
#define XUSB_DEV_CFG_1_0_SIGNALED_SERR_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_SIGNALED_SERR_SHIFT)
#define XUSB_DEV_CFG_1_0_SIGNALED_SERR_RANGE               30:30
#define XUSB_DEV_CFG_1_0_SIGNALED_SERR_WOFFSET             0
#define XUSB_DEV_CFG_1_0_SIGNALED_SERR_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SIGNALED_SERR_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_SIGNALED_SERR_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SIGNALED_SERR_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_SIGNALED_SERR_NOT_ACTIVE          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_SIGNALED_SERR_ACTIVE              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_SIGNALED_SERR_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_DETECTED_PERR_SHIFT                _MK_SHIFT_CONST(31)
#define XUSB_DEV_CFG_1_0_DETECTED_PERR_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_1_0_DETECTED_PERR_SHIFT)
#define XUSB_DEV_CFG_1_0_DETECTED_PERR_RANGE               31:31
#define XUSB_DEV_CFG_1_0_DETECTED_PERR_WOFFSET             0
#define XUSB_DEV_CFG_1_0_DETECTED_PERR_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_DETECTED_PERR_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_DETECTED_PERR_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_DETECTED_PERR_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_1_0_DETECTED_PERR_NOT_ACTIVE          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_1_0_DETECTED_PERR_ACTIVE              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_1_0_DETECTED_PERR_CLEAR               _MK_ENUM_CONST(0x00000001)


// 
// 
//                 Figure 10-2  FPCI Configuration Register 04h
// 
// // Constraints for Advanced ref manual flow.
// constraint cfg_1_mem_space {T_XUSB_DEV_CFG_1_MEMORY_SPACE == 1'b1;}
// constraint cfg_1_bus_master {T_XUSB_DEV_CFG_1_BUS_MASTER == 1'b1;}
// 
// 
// .TITLE PCI Revision ID and Class Code Register 08h
// 
// .FIELD REVISION_ID
//      The REVISION_ID bits specify a device specific revision identifier.  The
// value is chosen by the vendor.  Zero is an acceptable value.  This field
// should be viewed as a vendor defined extension to the DEVICE_ID.
// .FIELD PROG_IF
// .FIELD SUB_CLASS
// .FIELD BASE_CLASS
//      The CLASS_CODE bits identify the generic function of the device and
// (in some cases) a specific register-level programming interface.  The register
// is broken into three byte-size fields.  The upper byte (at offset 0BH) is a
// base class code which broadly classifies the type of function the device
// performs.  The middle-byte (at offset 0BH)is a sub-class code which identifies
// more specifically the function of the device.  The lower byte (at offset 09H)
// identifies a specific register-level programming interface (if any) so that
// device independent software can interact with the device.
// 
//         The Class Code and Revision ID are defined by parameters per block.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 1 1 0 0|0 0 0 0 0 0 1 1|0 0 0 1 0 0 0 0|0 0 0 0 0 0 0 0| CFG_2
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 


#define XUSB_DEV_CFG_2_0                                   _MK_ADDR_CONST(0x00000008)
#define XUSB_DEV_CFG_2_0_SECURE                            0
#define XUSB_DEV_CFG_2_0_WORD_COUNT                        1
#define XUSB_DEV_CFG_2_0_RESET_VAL                         _MK_MASK_CONST(0xc03fea1)
#define XUSB_DEV_CFG_2_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0xc03fea1)
#define XUSB_DEV_CFG_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_2_0_CLEAR_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_2_0_TGL_MASK                          _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_2_0_REVISION_ID_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_2_0_REVISION_ID_FIELD                 (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_2_0_REVISION_ID_SHIFT)
#define XUSB_DEV_CFG_2_0_REVISION_ID_RANGE                 7:0
#define XUSB_DEV_CFG_2_0_REVISION_ID_WOFFSET               0
#define XUSB_DEV_CFG_2_0_REVISION_ID_DEFAULT               (_MK_MASK_CONST(0x000000A1)
#define XUSB_DEV_CFG_2_0_REVISION_ID_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_2_0_REVISION_ID_SW_DEFAULT            (_MK_MASK_CONST(0x000000A1)
#define XUSB_DEV_CFG_2_0_REVISION_ID_SW_DEFAULT_MASK       (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_2_0_REVISION_ID_VAL                   _MK_ENUM_CONST(0x000000A1)
#define XUSB_DEV_CFG_2_0_REVISION_ID_A01                   _MK_ENUM_CONST(0x000000A1)
#define XUSB_DEV_CFG_2_0_PROG_IF_SHIFT                      _MK_SHIFT_CONST(8)
#define XUSB_DEV_CFG_2_0_PROG_IF_FIELD                     (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_2_0_PROG_IF_SHIFT)
#define XUSB_DEV_CFG_2_0_PROG_IF_RANGE                     15:8
#define XUSB_DEV_CFG_2_0_PROG_IF_WOFFSET                   0
#define XUSB_DEV_CFG_2_0_PROG_IF_DEFAULT                   (_MK_MASK_CONST(0x000000FE)
#define XUSB_DEV_CFG_2_0_PROG_IF_DEFAULT_MASK              (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_2_0_PROG_IF_SW_DEFAULT                (_MK_MASK_CONST(0x000000FE)
#define XUSB_DEV_CFG_2_0_PROG_IF_SW_DEFAULT_MASK           (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_2_0_PROG_IF_CUSTOM                    _MK_ENUM_CONST(0x000000FE)
#define XUSB_DEV_CFG_2_0_SUB_CLASS_SHIFT                    _MK_SHIFT_CONST(16)
#define XUSB_DEV_CFG_2_0_SUB_CLASS_FIELD                   (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_2_0_SUB_CLASS_SHIFT)
#define XUSB_DEV_CFG_2_0_SUB_CLASS_RANGE                   23:16
#define XUSB_DEV_CFG_2_0_SUB_CLASS_WOFFSET                 0
#define XUSB_DEV_CFG_2_0_SUB_CLASS_DEFAULT                 (_MK_MASK_CONST(0x00000003)
#define XUSB_DEV_CFG_2_0_SUB_CLASS_DEFAULT_MASK            (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_2_0_SUB_CLASS_SW_DEFAULT              (_MK_MASK_CONST(0x00000003)
#define XUSB_DEV_CFG_2_0_SUB_CLASS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_2_0_SUB_CLASS_XUSB                    _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_CFG_2_0_BASE_CLASS_SHIFT                   _MK_SHIFT_CONST(24)
#define XUSB_DEV_CFG_2_0_BASE_CLASS_FIELD                  (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_2_0_BASE_CLASS_SHIFT)
#define XUSB_DEV_CFG_2_0_BASE_CLASS_RANGE                  31:24
#define XUSB_DEV_CFG_2_0_BASE_CLASS_WOFFSET                0
#define XUSB_DEV_CFG_2_0_BASE_CLASS_DEFAULT                (_MK_MASK_CONST(0x0000000C)
#define XUSB_DEV_CFG_2_0_BASE_CLASS_DEFAULT_MASK           (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_2_0_BASE_CLASS_SW_DEFAULT             (_MK_MASK_CONST(0x0000000C)
#define XUSB_DEV_CFG_2_0_BASE_CLASS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_2_0_BASE_CLASS_SBC                    _MK_ENUM_CONST(0x0000000C)


// 
// 
// 
// 
// 
//                 Figure 10-3  FPCI Configuration Register 08h
// 
// 
// 
// .TITLE PCI Configuration Register 0Ch
// 
// .FIELD LATENCY_TIMER
//      The LATENCY_TIMER bits contain, in units of PCI bus clocks, the value of
// the Latency Timer for this PCI bus master.  This register must be implemented
// as writable by any master that can burst more than two data phases.  This
// register may be implemented as read-only for devices that burst two or fewer
// data phases, but the hardwired value must be limited to 16 or less.  A typical
// implementation would be to build the five high-order bits (leaving the bottom
// three as read-only), resulting in a timer granularity of eight clocks.  At
// reset, the register should be set to 0 (if programmable).  LATENCY_TIMER bits
// are writable.
// .FIELD HEADER_TYPE_DEVICE
//      The HEADER_TYPE bits identify the layout of the bytes 10h through 3FH in
// configuration space and also whether or not the device contains multiple
// functions.  Bit 7 in this register is used to identify a multi-function
// device.  If the bit is 0, then the device is single function.  If the bit is
// 1, then the device has multiple functions.  Bits 6 through 0 specify the
// layout of bytes 10h through 3Fh.
// 
//      The LATENCY_TIMER and HEADER_TYPE are defined by parameters per block.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0|0|0 0 0 0 0 0 0|0 0 0 0 0|0 0 0|0 0 0 0 0 0 0 0| CFG_3
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 


#define XUSB_DEV_CFG_3_0                                   _MK_ADDR_CONST(0x0000000C)
#define XUSB_DEV_CFG_3_0_SECURE                            0
#define XUSB_DEV_CFG_3_0_WORD_COUNT                        1
#define XUSB_DEV_CFG_3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_3_0_RESET_MASK                        _MK_MASK_CONST(0xfff8ff)
#define XUSB_DEV_CFG_3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xfff8ff)
#define XUSB_DEV_CFG_3_0_READ_MASK                         _MK_MASK_CONST(0xfff8ff)
#define XUSB_DEV_CFG_3_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_3_0_CLEAR_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_3_0_TGL_MASK                          _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_SHIFT              _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_FIELD             (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_SHIFT)
#define XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_RANGE             7:0
#define XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_WOFFSET           0
#define XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_DEFAULT_MASK      (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_SW_DEFAULT_MASK   (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_0                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_32                _MK_ENUM_CONST(0x00000020)
#define XUSB_DEV_CFG_3_0_CACHE_LINE_SIZE_64                _MK_ENUM_CONST(0x00000040)
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_SHIFT                _MK_SHIFT_CONST(11)
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_FIELD               (_MK_SHIFT_CONST(0x1f) << XUSB_DEV_CFG_3_0_LATENCY_TIMER_SHIFT)
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_RANGE               15:11
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_WOFFSET             0
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_DEFAULT_MASK        (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_0_CLOCKS            _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_8_CLOCKS            _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_240_CLOCKS          _MK_ENUM_CONST(0x0000001E)
#define XUSB_DEV_CFG_3_0_LATENCY_TIMER_248_CLOCKS          _MK_ENUM_CONST(0x0000001F)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_DEVICE_SHIFT           _MK_SHIFT_CONST(16)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_DEVICE_FIELD          (_MK_SHIFT_CONST(0x7f) << XUSB_DEV_CFG_3_0_HEADER_TYPE_DEVICE_SHIFT)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_DEVICE_RANGE          22:16
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_DEVICE_WOFFSET        0
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_DEVICE_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_DEVICE_DEFAULT_MASK   (_MK_MASK_CONST(0x7f)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_DEVICE_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_DEVICE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x7f)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_DEVICE_NON_BRIDGE     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_DEVICE_P2P_BRIDGE     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_FUNC_SHIFT             _MK_SHIFT_CONST(23)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_FUNC_FIELD            (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_3_0_HEADER_TYPE_FUNC_SHIFT)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_FUNC_RANGE            23:23
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_FUNC_WOFFSET          0
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_FUNC_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_FUNC_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_FUNC_SW_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_FUNC_SW_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_FUNC_SINGLE           _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_3_0_HEADER_TYPE_FUNC_MULTI            _MK_ENUM_CONST(0x00000001)


// 
// 
//                 Figure 10-4  PCI Configuration Register 0Ch
// 
// 
// 
// .TITLE PCI Configuration Register 10h
// 
// .FIELD SPACE_TYPE
//      The SPACE_TYPE bit indicates whether the register maps into Memory or I/O
// space.
// .FIELD ADDRESS_TYPE
//      The ADDRESS_TYPE bits contain the type of the Base Address.  It can be 32
// bits, 20 bits, or 64 bits wide.
// .FIELD BASE_ADDRESS
//      The BASE_ADDRESS bits contain the base address of the device.  The number
// of upper bits that a device actually implements depends on how much of the
// address space the device will respond to.  A device that wants a 1 MB memory
// address space (using a 32-bit base address register) would build the top 12
// bits of the address register, hardwiring the other bits to 0.  Power-up
// software can determine how much address space the device required by writing a
// value of all 1's to the register and then reading the value back.  The device
// will return 0's in all don't-care address bits, effectively specifying the
// address space required.
// 
// TBD: Explain XHCI BAR0
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                               |0 0 0 0 0|0 0|0| CFG_4
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 


#define XUSB_DEV_CFG_4_0                                   _MK_ADDR_CONST(0x00000010)
#define XUSB_DEV_CFG_4_0_SECURE                            0
#define XUSB_DEV_CFG_4_0_WORD_COUNT                        1
#define XUSB_DEV_CFG_4_0_RESET_VAL                         _MK_MASK_CONST(0xc)
#define XUSB_DEV_CFG_4_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0xc)
#define XUSB_DEV_CFG_4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_4_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_4_0_WRITE_MASK                        _MK_MASK_CONST(0xffff8000)
#define XUSB_DEV_CFG_4_0_CLEAR_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_4_0_TGL_MASK                          _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_4_0_SPACE_TYPE_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_4_0_SPACE_TYPE_FIELD                  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_4_0_SPACE_TYPE_SHIFT)
#define XUSB_DEV_CFG_4_0_SPACE_TYPE_RANGE                  0:0
#define XUSB_DEV_CFG_4_0_SPACE_TYPE_WOFFSET                0
#define XUSB_DEV_CFG_4_0_SPACE_TYPE_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_4_0_SPACE_TYPE_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_4_0_SPACE_TYPE_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_4_0_SPACE_TYPE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_4_0_SPACE_TYPE_MEMORY                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_4_0_SPACE_TYPE_IO                     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_4_0_ADDRESS_TYPE_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_DEV_CFG_4_0_ADDRESS_TYPE_FIELD                (_MK_SHIFT_CONST(0x3) << XUSB_DEV_CFG_4_0_ADDRESS_TYPE_SHIFT)
#define XUSB_DEV_CFG_4_0_ADDRESS_TYPE_RANGE                2:1
#define XUSB_DEV_CFG_4_0_ADDRESS_TYPE_WOFFSET              0
#define XUSB_DEV_CFG_4_0_ADDRESS_TYPE_DEFAULT              (_MK_MASK_CONST(0x00000002)
#define XUSB_DEV_CFG_4_0_ADDRESS_TYPE_DEFAULT_MASK         (_MK_MASK_CONST(0x3)
#define XUSB_DEV_CFG_4_0_ADDRESS_TYPE_SW_DEFAULT           (_MK_MASK_CONST(0x00000002)
#define XUSB_DEV_CFG_4_0_ADDRESS_TYPE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x3)
#define XUSB_DEV_CFG_4_0_ADDRESS_TYPE_32_BIT               _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_4_0_ADDRESS_TYPE_64_BIT               _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_CFG_4_0_PREFETCHABLE_SHIFT                 _MK_SHIFT_CONST(3)
#define XUSB_DEV_CFG_4_0_PREFETCHABLE_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_4_0_PREFETCHABLE_SHIFT)
#define XUSB_DEV_CFG_4_0_PREFETCHABLE_RANGE                3:3
#define XUSB_DEV_CFG_4_0_PREFETCHABLE_WOFFSET              0
#define XUSB_DEV_CFG_4_0_PREFETCHABLE_DEFAULT              (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_CFG_4_0_PREFETCHABLE_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_4_0_PREFETCHABLE_SW_DEFAULT           (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_CFG_4_0_PREFETCHABLE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_4_0_PREFETCHABLE_NOT                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_4_0_PREFETCHABLE_MERGABLE             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_4_0_BAR_SIZE_32KB_SHIFT                _MK_SHIFT_CONST(4)
#define XUSB_DEV_CFG_4_0_BAR_SIZE_32KB_FIELD               (_MK_SHIFT_CONST(0x7ff) << XUSB_DEV_CFG_4_0_BAR_SIZE_32KB_SHIFT)
#define XUSB_DEV_CFG_4_0_BAR_SIZE_32KB_RANGE               14:4
#define XUSB_DEV_CFG_4_0_BAR_SIZE_32KB_WOFFSET             0
#define XUSB_DEV_CFG_4_0_BAR_SIZE_32KB_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_4_0_BAR_SIZE_32KB_DEFAULT_MASK        (_MK_MASK_CONST(0x7ff)
#define XUSB_DEV_CFG_4_0_BAR_SIZE_32KB_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_4_0_BAR_SIZE_32KB_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x7ff)
#define XUSB_DEV_CFG_4_0_BAR_SIZE_32KB_RSVD                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_4_0_BASE_ADDRESS_SHIFT                 _MK_SHIFT_CONST(15)
#define XUSB_DEV_CFG_4_0_BASE_ADDRESS_FIELD                (_MK_SHIFT_CONST(0x1ffff) << XUSB_DEV_CFG_4_0_BASE_ADDRESS_SHIFT)
#define XUSB_DEV_CFG_4_0_BASE_ADDRESS_RANGE                31:15
#define XUSB_DEV_CFG_4_0_BASE_ADDRESS_WOFFSET              0
#define XUSB_DEV_CFG_4_0_BASE_ADDRESS_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_4_0_BASE_ADDRESS_DEFAULT_MASK         (_MK_MASK_CONST(0x1ffff)
#define XUSB_DEV_CFG_4_0_BASE_ADDRESS_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_4_0_BASE_ADDRESS_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1ffff)
#define XUSB_DEV_CFG_4_0_BASE_ADDRESS__NOPRDCHK            _MK_ENUM_CONST(0x00000001)


// 
// 
// // TBD - Change == to >= after ref manual flow is fixed.
// constraint cfg_4_base_address {(T_XUSB_DEV_CFG_4_BASE_ADDRESS  inside {[17'h00200:17'h1FFFF]});}
// 


#define XUSB_DEV_CFG_5_0                                   _MK_ADDR_CONST(0x00000014)
#define XUSB_DEV_CFG_5_0_SECURE                            0
#define XUSB_DEV_CFG_5_0_WORD_COUNT                        1
#define XUSB_DEV_CFG_5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_5_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_5_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_5_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_5_0_CLEAR_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_5_0_TGL_MASK                          _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_5_0_BASE_ADDRESSHI_SHIFT               _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_5_0_BASE_ADDRESSHI_FIELD              (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_CFG_5_0_BASE_ADDRESSHI_SHIFT)
#define XUSB_DEV_CFG_5_0_BASE_ADDRESSHI_RANGE              31:0
#define XUSB_DEV_CFG_5_0_BASE_ADDRESSHI_WOFFSET            0
#define XUSB_DEV_CFG_5_0_BASE_ADDRESSHI_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_5_0_BASE_ADDRESSHI_DEFAULT_MASK       (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_5_0_BASE_ADDRESSHI_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_5_0_BASE_ADDRESSHI_SW_DEFAULT_MASK    (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_5_0_BASE_ADDRESSHI__NOPRDCHK          _MK_ENUM_CONST(0x00000001)


// 
// constraint cfg_5_base_addresshi {(T_XUSB_DEV_CFG_5_BASE_ADDRESSHI  inside {[32'h00000000:32'h000000FC]});}
// 
// Array T_XUSB_DEV_CFG_6[5] (0x00000018+(i)*4)


#define XUSB_DEV_CFG_6_0                                   _MK_ADDR_CONST(0x18)
#define XUSB_DEV_CFG_6_0_SECURE                            0
#define XUSB_DEV_CFG_6_0_WORD_COUNT                        1
#define XUSB_DEV_CFG_6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_0_CLEAR_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_0_TGL_MASK                          _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_0_RSVD_SHIFT                         _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_6_0_RSVD_FIELD                        (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_CFG_6_0_RSVD_SHIFT)
#define XUSB_DEV_CFG_6_0_RSVD_RANGE                        31:0
#define XUSB_DEV_CFG_6_0_RSVD_WOFFSET                      0
#define XUSB_DEV_CFG_6_0_RSVD_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_6_0_RSVD_DEFAULT_MASK                 (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_0_RSVD_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_6_0_RSVD_SW_DEFAULT_MASK              (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_0_RSVD_00                           _MK_ENUM_CONST(0x00000000)




#define XUSB_DEV_CFG_6_1                                   _MK_ADDR_CONST(0x1c)
#define XUSB_DEV_CFG_6_1_SECURE                            0
#define XUSB_DEV_CFG_6_1_WORD_COUNT                        1
#define XUSB_DEV_CFG_6_1_RESET_VAL                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_1_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_1_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_1_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_1_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_1_CLEAR_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_1_TGL_MASK                          _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_1_RSVD_SHIFT                         _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_6_1_RSVD_FIELD                        (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_CFG_6_1_RSVD_SHIFT)
#define XUSB_DEV_CFG_6_1_RSVD_RANGE                        31:0
#define XUSB_DEV_CFG_6_1_RSVD_WOFFSET                      0
#define XUSB_DEV_CFG_6_1_RSVD_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_6_1_RSVD_DEFAULT_MASK                 (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_1_RSVD_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_6_1_RSVD_SW_DEFAULT_MASK              (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_1_RSVD_00                           _MK_ENUM_CONST(0x00000000)




#define XUSB_DEV_CFG_6_2                                   _MK_ADDR_CONST(0x20)
#define XUSB_DEV_CFG_6_2_SECURE                            0
#define XUSB_DEV_CFG_6_2_WORD_COUNT                        1
#define XUSB_DEV_CFG_6_2_RESET_VAL                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_2_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_2_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_2_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_2_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_2_CLEAR_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_2_TGL_MASK                          _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_2_RSVD_SHIFT                         _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_6_2_RSVD_FIELD                        (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_CFG_6_2_RSVD_SHIFT)
#define XUSB_DEV_CFG_6_2_RSVD_RANGE                        31:0
#define XUSB_DEV_CFG_6_2_RSVD_WOFFSET                      0
#define XUSB_DEV_CFG_6_2_RSVD_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_6_2_RSVD_DEFAULT_MASK                 (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_2_RSVD_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_6_2_RSVD_SW_DEFAULT_MASK              (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_2_RSVD_00                           _MK_ENUM_CONST(0x00000000)




#define XUSB_DEV_CFG_6_3                                   _MK_ADDR_CONST(0x24)
#define XUSB_DEV_CFG_6_3_SECURE                            0
#define XUSB_DEV_CFG_6_3_WORD_COUNT                        1
#define XUSB_DEV_CFG_6_3_RESET_VAL                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_3_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_3_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_3_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_3_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_3_CLEAR_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_3_TGL_MASK                          _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_3_RSVD_SHIFT                         _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_6_3_RSVD_FIELD                        (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_CFG_6_3_RSVD_SHIFT)
#define XUSB_DEV_CFG_6_3_RSVD_RANGE                        31:0
#define XUSB_DEV_CFG_6_3_RSVD_WOFFSET                      0
#define XUSB_DEV_CFG_6_3_RSVD_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_6_3_RSVD_DEFAULT_MASK                 (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_3_RSVD_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_6_3_RSVD_SW_DEFAULT_MASK              (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_3_RSVD_00                           _MK_ENUM_CONST(0x00000000)




#define XUSB_DEV_CFG_6_4                                   _MK_ADDR_CONST(0x28)
#define XUSB_DEV_CFG_6_4_SECURE                            0
#define XUSB_DEV_CFG_6_4_WORD_COUNT                        1
#define XUSB_DEV_CFG_6_4_RESET_VAL                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_4_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_4_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_4_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_4_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_4_CLEAR_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_4_TGL_MASK                          _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_6_4_RSVD_SHIFT                         _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_6_4_RSVD_FIELD                        (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_CFG_6_4_RSVD_SHIFT)
#define XUSB_DEV_CFG_6_4_RSVD_RANGE                        31:0
#define XUSB_DEV_CFG_6_4_RSVD_WOFFSET                      0
#define XUSB_DEV_CFG_6_4_RSVD_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_6_4_RSVD_DEFAULT_MASK                 (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_4_RSVD_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_6_4_RSVD_SW_DEFAULT_MASK              (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_6_4_RSVD_00                           _MK_ENUM_CONST(0x00000000)


// 
// .TITLE PCI Configuration Register 2Ch
//      The SUBSYSTEM_VENDOR_ID bits and SUBSYSTEM_ID bits are used to uniquely
// identify the add-in board or subsystem where the device resides.  When the
// device is on the motherboard, there is no serial ROM and the registers both
// initialize to NONE.  The motherboard BIOS must set the values of the Subsystem
// ID and Subsystem Vendor ID by writing the proper values to the
// SUBSYSTEM_VENDOR_ID and SUBSYSTEM_ID bits in the PCI_T_16 register
// (NOT PCI_T_11).
// //TBD - Show the proper backdoor register.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                               |                               | CFG_11
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 


#define XUSB_DEV_CFG_11_0                                  _MK_ADDR_CONST(0x0000002C)
#define XUSB_DEV_CFG_11_0_SECURE                           0
#define XUSB_DEV_CFG_11_0_WORD_COUNT                       1
#define XUSB_DEV_CFG_11_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_11_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_11_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_11_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_11_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_11_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_11_0_CLEAR_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_11_0_TGL_MASK                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_VENDOR_ID_SHIFT         _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_VENDOR_ID_FIELD        (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_CFG_11_0_SUBSYSTEM_VENDOR_ID_SHIFT)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_VENDOR_ID_RANGE        15:0
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_VENDOR_ID_WOFFSET      0
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_VENDOR_ID_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_VENDOR_ID_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_VENDOR_ID_SW_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_VENDOR_ID_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_VENDOR_ID_NONE         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_ID_SHIFT                _MK_SHIFT_CONST(16)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_ID_FIELD               (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_CFG_11_0_SUBSYSTEM_ID_SHIFT)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_ID_RANGE               31:16
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_ID_WOFFSET             0
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_ID_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_ID_DEFAULT_MASK        (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_ID_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_ID_SW_DEFAULT_MASK     (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_11_0_SUBSYSTEM_ID_NONE                _MK_ENUM_CONST(0x00000000)


// 
// 
// 
//                 Figure 10-6  FPCI Configuration Register 2Ch
// 
// .TITLE PCI Configuration Register 30h
//      The Expansion ROM Base Address configuration register should not be used
// for any FPCI integrated blocks.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_12
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 


#define XUSB_DEV_CFG_12_0                                  _MK_ADDR_CONST(0x00000030)
#define XUSB_DEV_CFG_12_0_SECURE                           0
#define XUSB_DEV_CFG_12_0_WORD_COUNT                       1
#define XUSB_DEV_CFG_12_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_12_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_12_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_12_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_12_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_12_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_12_0_CLEAR_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_12_0_TGL_MASK                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_12_0_RESERVED_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_12_0_RESERVED_FIELD                   (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_CFG_12_0_RESERVED_SHIFT)
#define XUSB_DEV_CFG_12_0_RESERVED_RANGE                   31:0
#define XUSB_DEV_CFG_12_0_RESERVED_WOFFSET                 0
#define XUSB_DEV_CFG_12_0_RESERVED_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_12_0_RESERVED_DEFAULT_MASK            (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_12_0_RESERVED_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_12_0_RESERVED_SW_DEFAULT_MASK         (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_12_0_RESERVED_0                       _MK_ENUM_CONST(0x00000000)


// 
// 
// 
//                 Figure 10-7  PCI Configuration Register 30h
// 
// .TITLE PCI Capability Pointer Register
// 
// .FIELD CAP_PTR
//      The CAP_PTR bits indicate the offset into configuration space where the
// capabilities list begins. This always points to 0x44 where at least the PCI-PM
// registers are expected to reside.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|0 1 0 0 0 1 0 0| CFG_13
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 


#define XUSB_DEV_CFG_13_0                                  _MK_ADDR_CONST(0x00000034)
#define XUSB_DEV_CFG_13_0_SECURE                           0
#define XUSB_DEV_CFG_13_0_WORD_COUNT                       1
#define XUSB_DEV_CFG_13_0_RESET_VAL                        _MK_MASK_CONST(0x44)
#define XUSB_DEV_CFG_13_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_13_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x44)
#define XUSB_DEV_CFG_13_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_13_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_13_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_13_0_CLEAR_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_13_0_TGL_MASK                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_13_0_CAP_PTR_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_13_0_CAP_PTR_FIELD                    (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_13_0_CAP_PTR_SHIFT)
#define XUSB_DEV_CFG_13_0_CAP_PTR_RANGE                    7:0
#define XUSB_DEV_CFG_13_0_CAP_PTR_WOFFSET                  0
#define XUSB_DEV_CFG_13_0_CAP_PTR_DEFAULT                  (_MK_MASK_CONST(0x00000044)
#define XUSB_DEV_CFG_13_0_CAP_PTR_DEFAULT_MASK             (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_13_0_CAP_PTR_SW_DEFAULT               (_MK_MASK_CONST(0x00000044)
#define XUSB_DEV_CFG_13_0_CAP_PTR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_13_0_CAP_PTR_PMCAP                    _MK_ENUM_CONST(0x00000044)
#define XUSB_DEV_CFG_13_0_CAP_PTR_MSI                      _MK_ENUM_CONST(0x000000C0)
#define XUSB_DEV_CFG_13_0_CAP_PTR_MSIX                     _MK_ENUM_CONST(0x00000070)
#define XUSB_DEV_CFG_13_0_CAP_PTR_MMAP                     _MK_ENUM_CONST(0x000000DC)


// 
// 
//                 Figure 10-8  FPCI Configuration Register 34h
// 
// .TITLE PCI Configuration Register 38h
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| CFG_14
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 


#define XUSB_DEV_CFG_14_0                                  _MK_ADDR_CONST(0x00000038)
#define XUSB_DEV_CFG_14_0_SECURE                           0
#define XUSB_DEV_CFG_14_0_WORD_COUNT                       1
#define XUSB_DEV_CFG_14_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_14_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_14_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_14_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_14_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_14_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_14_0_CLEAR_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_14_0_TGL_MASK                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_14_0_RESERVED_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_14_0_RESERVED_FIELD                   (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_CFG_14_0_RESERVED_SHIFT)
#define XUSB_DEV_CFG_14_0_RESERVED_RANGE                   31:0
#define XUSB_DEV_CFG_14_0_RESERVED_WOFFSET                 0
#define XUSB_DEV_CFG_14_0_RESERVED_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_14_0_RESERVED_DEFAULT_MASK            (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_14_0_RESERVED_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_14_0_RESERVED_SW_DEFAULT_MASK         (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_14_0_RESERVED_0                       _MK_ENUM_CONST(0x00000000)


// 
// 
//                 Figure 10-9  FPCI Configuration Register 38h
// 
// 
// .TITLE PCI Configuration Register 3Ch
// 
// 
// .FIELD INTR_LINE
//      The INTR_LINE bits contain the interrupt routing information.  The
// register is read/write and must be implemented by any device (or device
// function) that uses an interrupt pin.  POST software will write the routing
// information into this register as it initializes and configures the system.
// The value in this register tells which input of the system interrupt
// controller(s) the device's interrupt pin is connected to.  Device drivers and
// operating systems can use this information to determine priority and vector
// information.  INTR_LINE is initialized to 0xff (no connection) at reset.  Some
// PCI BIOS' can't handle aliased INTR_LINEs.  Some PCI BIOS' can't handle
// INTR_LINE initialized to 0xff.
// .FIELD INTR_PIN
//      The INTR_PIN bits contain the interrupt pin the device (or device
// function) uses.  A value of 1 corresponds to INTA#.  A value of 2 corresponds
// to INTB#.  A value of 3 corresponds to INTC#.  A value of 4 corresponds to
// INTD#.  Devices (or device functions) that don't use an interrupt pin must put
// a 0 in this register.  This register is read-only.
// .FIELD MIN_GNT
//      The MIN_GNT bits contain the length of the burst period a device needs
// assuming a clock rate of 33 MHz.  This read-only register is used to specify
// the device's desired settings for Latency Timer values.  The value specifies a
// period of time in units of 1/4 microsecond.  Values of 0 indicate that the
// device has no major requirements for the settings of Latency Timers.  MIN_GNT
// is nonzero.
// .FIELD MAX_LAT
//      The MAX_LAT bits contain the maximum time the device requires to gain
// access to the CPI bus.  This read-only register is used to specify the
// device's desired settings for Latency Timer values.  The value specifies a
// period of time in units of 1/4 microsecond.  Values of 0 indicate that the
// device has no major requirements for the settings of Latency Timers.  MAX_LAT
// is nonzero.
// 
//      The INTR_PIN, MIN_GNT, and MAX_LAT are configurable per block.
// //TBD Review this description
// For a 64 byte buffer, with two 32 byte sections, the maximum
// tolerable latency for the XHCI once a large XUSB ISO transaction
// has begun is about 23 uSec.  The latency timer is hardwired to
// 20uS.  This value only applies in External PCI operation.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 1|0 0 0 0 0 0 1 1|0 0 0 0 0 0 0 1|               | CFG_15
// `-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-'
// 


#define XUSB_DEV_CFG_15_0                                  _MK_ADDR_CONST(0x0000003C)
#define XUSB_DEV_CFG_15_0_SECURE                           0
#define XUSB_DEV_CFG_15_0_WORD_COUNT                       1
#define XUSB_DEV_CFG_15_0_RESET_VAL                        _MK_MASK_CONST(0x100)
#define XUSB_DEV_CFG_15_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_15_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x100)
#define XUSB_DEV_CFG_15_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_15_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_15_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_15_0_CLEAR_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_15_0_TGL_MASK                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_15_0_INTR_LINE_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_15_0_INTR_LINE_FIELD                  (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_15_0_INTR_LINE_SHIFT)
#define XUSB_DEV_CFG_15_0_INTR_LINE_RANGE                  7:0
#define XUSB_DEV_CFG_15_0_INTR_LINE_WOFFSET                0
#define XUSB_DEV_CFG_15_0_INTR_LINE_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_15_0_INTR_LINE_DEFAULT_MASK           (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_15_0_INTR_LINE_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_15_0_INTR_LINE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_15_0_INTR_LINE__NOPRDCHK              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_15_0_INTR_LINE_IRQ0                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_15_0_INTR_LINE_IRQ1                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_15_0_INTR_LINE_IRQ15                  _MK_ENUM_CONST(0x0000000F)
#define XUSB_DEV_CFG_15_0_INTR_LINE_UNKNOWN                _MK_ENUM_CONST(0x000000FF)
#define XUSB_DEV_CFG_15_0_INTR_PIN_SHIFT                    _MK_SHIFT_CONST(8)
#define XUSB_DEV_CFG_15_0_INTR_PIN_FIELD                   (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_15_0_INTR_PIN_SHIFT)
#define XUSB_DEV_CFG_15_0_INTR_PIN_RANGE                   15:8
#define XUSB_DEV_CFG_15_0_INTR_PIN_WOFFSET                 0
#define XUSB_DEV_CFG_15_0_INTR_PIN_DEFAULT                 (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_CFG_15_0_INTR_PIN_DEFAULT_MASK            (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_15_0_INTR_PIN_SW_DEFAULT              (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_CFG_15_0_INTR_PIN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_15_0_INTR_PIN_NONE                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_15_0_INTR_PIN_INTA                    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_15_0_INTR_PIN_INTB                    _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_CFG_15_0_INTR_PIN_INTC                    _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_CFG_15_0_INTR_PIN_INTD                    _MK_ENUM_CONST(0x00000004)
#define XUSB_DEV_CFG_15_0_MIN_GNT_SHIFT                     _MK_SHIFT_CONST(16)
#define XUSB_DEV_CFG_15_0_MIN_GNT_FIELD                    (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_15_0_MIN_GNT_SHIFT)
#define XUSB_DEV_CFG_15_0_MIN_GNT_RANGE                    23:16
#define XUSB_DEV_CFG_15_0_MIN_GNT_WOFFSET                  0
#define XUSB_DEV_CFG_15_0_MIN_GNT_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_15_0_MIN_GNT_DEFAULT_MASK             (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_15_0_MIN_GNT_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_15_0_MIN_GNT_SW_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_15_0_MIN_GNT_NO_REQUIREMENTS          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_15_0_MIN_GNT_240NS                    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_15_0_MAX_LAT_SHIFT                     _MK_SHIFT_CONST(24)
#define XUSB_DEV_CFG_15_0_MAX_LAT_FIELD                    (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_15_0_MAX_LAT_SHIFT)
#define XUSB_DEV_CFG_15_0_MAX_LAT_RANGE                    31:24
#define XUSB_DEV_CFG_15_0_MAX_LAT_WOFFSET                  0
#define XUSB_DEV_CFG_15_0_MAX_LAT_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_15_0_MAX_LAT_DEFAULT_MASK             (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_15_0_MAX_LAT_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_15_0_MAX_LAT_SW_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define XUSB_DEV_CFG_15_0_MAX_LAT_NO_REQUIREMENTS          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_15_0_MAX_LAT_5US                      _MK_ENUM_CONST(0x00000014)
#define XUSB_DEV_CFG_15_0_MAX_LAT_20US                     _MK_ENUM_CONST(0x00000050)


// 
// 
//                 Figure 10-10  FPCI Configuration Register 3Ch
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// 
// 
//  Backdoor register write for updating subsystem id/vendor id.
// 


#define XUSB_DEV_CFG_16_0                                  _MK_ADDR_CONST(0x00000040)
#define XUSB_DEV_CFG_16_0_SECURE                           0
#define XUSB_DEV_CFG_16_0_WORD_COUNT                       1
#define XUSB_DEV_CFG_16_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_16_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_16_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_16_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_16_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_16_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_16_0_CLEAR_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_16_0_TGL_MASK                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_VENDOR_ID_SHIFT         _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_VENDOR_ID_FIELD        (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_CFG_16_0_SUBSYSTEM_VENDOR_ID_SHIFT)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_VENDOR_ID_RANGE        15:0
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_VENDOR_ID_WOFFSET      0
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_VENDOR_ID_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_VENDOR_ID_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_VENDOR_ID_SW_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_VENDOR_ID_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_VENDOR_ID__NOPRDCHK    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_VENDOR_ID_NONE         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_ID_SHIFT                _MK_SHIFT_CONST(16)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_ID_FIELD               (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_CFG_16_0_SUBSYSTEM_ID_SHIFT)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_ID_RANGE               31:16
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_ID_WOFFSET             0
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_ID_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_ID_DEFAULT_MASK        (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_ID_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_ID_SW_DEFAULT_MASK     (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_ID__NOPRDCHK           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_16_0_SUBSYSTEM_ID_NONE                _MK_ENUM_CONST(0x00000000)


// - - - - - - - - - - - - - - - - - - - - - - - - - - - - --- -- - - - - - - - - - - - - -
// 
// 
// //TBD - Debug Capability might have to be moved into BAR0 Extended Config Space
// 
// //PCI PM Cap


#define XUSB_DEV_CFG_17_0                                  _MK_ADDR_CONST(0x00000044)
#define XUSB_DEV_CFG_17_0_SECURE                           0
#define XUSB_DEV_CFG_17_0_WORD_COUNT                       1
#define XUSB_DEV_CFG_17_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_17_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_17_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_17_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_17_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_CFG_17_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_17_0_CLEAR_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_17_0_TGL_MASK                         _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_17_0_CAP_SHIFT                         _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_17_0_CAP_FIELD                        (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_17_0_CAP_SHIFT)
#define XUSB_DEV_CFG_17_0_CAP_RANGE                        7:0
#define XUSB_DEV_CFG_17_0_CAP_WOFFSET                      0
#define XUSB_DEV_CFG_17_0_CAP_PCIPM                        _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_17_0_NEXT_PTR_SHIFT                    _MK_SHIFT_CONST(8)
#define XUSB_DEV_CFG_17_0_NEXT_PTR_FIELD                   (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_17_0_NEXT_PTR_SHIFT)
#define XUSB_DEV_CFG_17_0_NEXT_PTR_RANGE                   15:8
#define XUSB_DEV_CFG_17_0_NEXT_PTR_WOFFSET                 0
#define XUSB_DEV_CFG_17_0_NEXT_PTR_MSI                     _MK_ENUM_CONST(0x000000C0)
#define XUSB_DEV_CFG_17_0_NEXT_PTR_MSIX                    _MK_ENUM_CONST(0x00000070)
#define XUSB_DEV_CFG_17_0_NEXT_PTR_MMAP                    _MK_ENUM_CONST(0x000000DC)
#define XUSB_DEV_CFG_17_0_NEXT_PTR_NULL                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_17_0_VER_SHIFT                         _MK_SHIFT_CONST(16)
#define XUSB_DEV_CFG_17_0_VER_FIELD                        (_MK_SHIFT_CONST(0x7) << XUSB_DEV_CFG_17_0_VER_SHIFT)
#define XUSB_DEV_CFG_17_0_VER_RANGE                        18:16
#define XUSB_DEV_CFG_17_0_VER_WOFFSET                      0
#define XUSB_DEV_CFG_17_0_VER_1P2                          _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_CFG_17_0_PMECLK_SHIFT                      _MK_SHIFT_CONST(19)
#define XUSB_DEV_CFG_17_0_PMECLK_FIELD                     (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_17_0_PMECLK_SHIFT)
#define XUSB_DEV_CFG_17_0_PMECLK_RANGE                     19:19
#define XUSB_DEV_CFG_17_0_PMECLK_WOFFSET                   0
#define XUSB_DEV_CFG_17_0_PMECLK_NOT_REQUIRED              _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_17_0_PMECLK_REQUIRED                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_17_0_RSVD_SHIFT                        _MK_SHIFT_CONST(20)
#define XUSB_DEV_CFG_17_0_RSVD_FIELD                       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_17_0_RSVD_SHIFT)
#define XUSB_DEV_CFG_17_0_RSVD_RANGE                       20:20
#define XUSB_DEV_CFG_17_0_RSVD_WOFFSET                     0
#define XUSB_DEV_CFG_17_0_RSVD_0                           _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_17_0_DSI_SHIFT                         _MK_SHIFT_CONST(21)
#define XUSB_DEV_CFG_17_0_DSI_FIELD                        (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_17_0_DSI_SHIFT)
#define XUSB_DEV_CFG_17_0_DSI_RANGE                        21:21
#define XUSB_DEV_CFG_17_0_DSI_WOFFSET                      0
#define XUSB_DEV_CFG_17_0_DSI_NONE                         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_17_0_DSI_NEEDED                       _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_17_0_AUXCUR_SHIFT                      _MK_SHIFT_CONST(22)
#define XUSB_DEV_CFG_17_0_AUXCUR_FIELD                     (_MK_SHIFT_CONST(0x7) << XUSB_DEV_CFG_17_0_AUXCUR_SHIFT)
#define XUSB_DEV_CFG_17_0_AUXCUR_RANGE                     24:22
#define XUSB_DEV_CFG_17_0_AUXCUR_WOFFSET                   0
#define XUSB_DEV_CFG_17_0_AUXCUR_SELF                      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_17_0_AUXCUR_55MA                      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_17_0_AUXCUR_100MA                     _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_CFG_17_0_AUXCUR_160MA                     _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_CFG_17_0_AUXCUR_220MA                     _MK_ENUM_CONST(0x00000004)
#define XUSB_DEV_CFG_17_0_AUXCUR_270MA                     _MK_ENUM_CONST(0x00000005)
#define XUSB_DEV_CFG_17_0_AUXCUR_320MA                     _MK_ENUM_CONST(0x00000006)
#define XUSB_DEV_CFG_17_0_AUXCUR_375MA                     _MK_ENUM_CONST(0x00000007)
#define XUSB_DEV_CFG_17_0_D1_SUPPORT_SHIFT                  _MK_SHIFT_CONST(25)
#define XUSB_DEV_CFG_17_0_D1_SUPPORT_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_17_0_D1_SUPPORT_SHIFT)
#define XUSB_DEV_CFG_17_0_D1_SUPPORT_RANGE                 25:25
#define XUSB_DEV_CFG_17_0_D1_SUPPORT_WOFFSET               0
#define XUSB_DEV_CFG_17_0_D1_SUPPORT_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_17_0_D1_SUPPORT_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_17_0_D2_SUPPORT_SHIFT                  _MK_SHIFT_CONST(26)
#define XUSB_DEV_CFG_17_0_D2_SUPPORT_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_17_0_D2_SUPPORT_SHIFT)
#define XUSB_DEV_CFG_17_0_D2_SUPPORT_RANGE                 26:26
#define XUSB_DEV_CFG_17_0_D2_SUPPORT_WOFFSET               0
#define XUSB_DEV_CFG_17_0_D2_SUPPORT_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_17_0_D2_SUPPORT_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_17_0_D0PME_SUPPORT_SHIFT               _MK_SHIFT_CONST(27)
#define XUSB_DEV_CFG_17_0_D0PME_SUPPORT_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_17_0_D0PME_SUPPORT_SHIFT)
#define XUSB_DEV_CFG_17_0_D0PME_SUPPORT_RANGE              27:27
#define XUSB_DEV_CFG_17_0_D0PME_SUPPORT_WOFFSET            0
#define XUSB_DEV_CFG_17_0_D0PME_SUPPORT_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_17_0_D0PME_SUPPORT_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_17_0_D1PME_SUPPORT_SHIFT               _MK_SHIFT_CONST(28)
#define XUSB_DEV_CFG_17_0_D1PME_SUPPORT_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_17_0_D1PME_SUPPORT_SHIFT)
#define XUSB_DEV_CFG_17_0_D1PME_SUPPORT_RANGE              28:28
#define XUSB_DEV_CFG_17_0_D1PME_SUPPORT_WOFFSET            0
#define XUSB_DEV_CFG_17_0_D1PME_SUPPORT_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_17_0_D1PME_SUPPORT_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_17_0_D2PME_SUPPORT_SHIFT               _MK_SHIFT_CONST(29)
#define XUSB_DEV_CFG_17_0_D2PME_SUPPORT_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_17_0_D2PME_SUPPORT_SHIFT)
#define XUSB_DEV_CFG_17_0_D2PME_SUPPORT_RANGE              29:29
#define XUSB_DEV_CFG_17_0_D2PME_SUPPORT_WOFFSET            0
#define XUSB_DEV_CFG_17_0_D2PME_SUPPORT_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_17_0_D2PME_SUPPORT_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_17_0_D3HPME_SUPPORT_SHIFT              _MK_SHIFT_CONST(30)
#define XUSB_DEV_CFG_17_0_D3HPME_SUPPORT_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_17_0_D3HPME_SUPPORT_SHIFT)
#define XUSB_DEV_CFG_17_0_D3HPME_SUPPORT_RANGE             30:30
#define XUSB_DEV_CFG_17_0_D3HPME_SUPPORT_WOFFSET           0
#define XUSB_DEV_CFG_17_0_D3HPME_SUPPORT_YES               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_17_0_D3HPME_SUPPORT_NO                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_17_0_D3CPME_SUPPORT_SHIFT              _MK_SHIFT_CONST(31)
#define XUSB_DEV_CFG_17_0_D3CPME_SUPPORT_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_17_0_D3CPME_SUPPORT_SHIFT)
#define XUSB_DEV_CFG_17_0_D3CPME_SUPPORT_RANGE             31:31
#define XUSB_DEV_CFG_17_0_D3CPME_SUPPORT_WOFFSET           0
#define XUSB_DEV_CFG_17_0_D3CPME_SUPPORT_YES               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_17_0_D3CPME_SUPPORT_NO                _MK_ENUM_CONST(0x00000000)


// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// 
// 
// 
// 


#define XUSB_DEV_CFG_18_PMCSR_0                            _MK_ADDR_CONST(0x00000048)
#define XUSB_DEV_CFG_18_PMCSR_0_SECURE                     0
#define XUSB_DEV_CFG_18_PMCSR_0_WORD_COUNT                 1
#define XUSB_DEV_CFG_18_PMCSR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_18_PMCSR_0_RESET_MASK                 _MK_MASK_CONST(0x8103)
#define XUSB_DEV_CFG_18_PMCSR_0_SW_DEFAULT_VAL             _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_18_PMCSR_0_SW_DEFAULT_MASK            _MK_MASK_CONST(0x8103)
#define XUSB_DEV_CFG_18_PMCSR_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
#define XUSB_DEV_CFG_18_PMCSR_0_WRITE_MASK                 _MK_MASK_CONST(0x8103)
#define XUSB_DEV_CFG_18_PMCSR_0_CLEAR_MASK                 _MK_MASK_CONST(0x8000)
#define XUSB_DEV_CFG_18_PMCSR_0_TGL_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_SHIFT              _MK_SHIFT_CONST(0)
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_FIELD             (_MK_SHIFT_CONST(0x3) << XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_SHIFT)
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_RANGE             1:0
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_WOFFSET           0
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_DEFAULT_MASK      (_MK_MASK_CONST(0x3)
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x3)
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_D0                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_D1                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_D2                _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_CFG_18_PMCSR_0_PWRSTATE_D3H               _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_CFG_18_PMCSR_0_RSVD0_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_DEV_CFG_18_PMCSR_0_RSVD0_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_18_PMCSR_0_RSVD0_SHIFT)
#define XUSB_DEV_CFG_18_PMCSR_0_RSVD0_RANGE                2:2
#define XUSB_DEV_CFG_18_PMCSR_0_RSVD0_WOFFSET              0
#define XUSB_DEV_CFG_18_PMCSR_0_RSVD0_0                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_NSR_SHIFT                   _MK_SHIFT_CONST(3)
#define XUSB_DEV_CFG_18_PMCSR_0_NSR_FIELD                  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_18_PMCSR_0_NSR_SHIFT)
#define XUSB_DEV_CFG_18_PMCSR_0_NSR_RANGE                  3:3
#define XUSB_DEV_CFG_18_PMCSR_0_NSR_WOFFSET                0
#define XUSB_DEV_CFG_18_PMCSR_0_NSR_NORESET                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_18_PMCSR_0_NSR_RESET                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_RSVD1_SHIFT                 _MK_SHIFT_CONST(4)
#define XUSB_DEV_CFG_18_PMCSR_0_RSVD1_FIELD                (_MK_SHIFT_CONST(0xf) << XUSB_DEV_CFG_18_PMCSR_0_RSVD1_SHIFT)
#define XUSB_DEV_CFG_18_PMCSR_0_RSVD1_RANGE                7:4
#define XUSB_DEV_CFG_18_PMCSR_0_RSVD1_WOFFSET              0
#define XUSB_DEV_CFG_18_PMCSR_0_RSVD1_00                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_PME_SHIFT                   _MK_SHIFT_CONST(8)
#define XUSB_DEV_CFG_18_PMCSR_0_PME_FIELD                  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_18_PMCSR_0_PME_SHIFT)
#define XUSB_DEV_CFG_18_PMCSR_0_PME_RANGE                  8:8
#define XUSB_DEV_CFG_18_PMCSR_0_PME_WOFFSET                0
#define XUSB_DEV_CFG_18_PMCSR_0_PME_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_PME_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_18_PMCSR_0_PME_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_PME_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_18_PMCSR_0_PME_ENABLE                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_18_PMCSR_0_PME_DISABLE                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_DSEL_SHIFT                  _MK_SHIFT_CONST(9)
#define XUSB_DEV_CFG_18_PMCSR_0_DSEL_FIELD                 (_MK_SHIFT_CONST(0xf) << XUSB_DEV_CFG_18_PMCSR_0_DSEL_SHIFT)
#define XUSB_DEV_CFG_18_PMCSR_0_DSEL_RANGE                 12:9
#define XUSB_DEV_CFG_18_PMCSR_0_DSEL_WOFFSET               0
#define XUSB_DEV_CFG_18_PMCSR_0_DSEL_INIT                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_DSCALE_SHIFT                _MK_SHIFT_CONST(13)
#define XUSB_DEV_CFG_18_PMCSR_0_DSCALE_FIELD               (_MK_SHIFT_CONST(0x3) << XUSB_DEV_CFG_18_PMCSR_0_DSCALE_SHIFT)
#define XUSB_DEV_CFG_18_PMCSR_0_DSCALE_RANGE               14:13
#define XUSB_DEV_CFG_18_PMCSR_0_DSCALE_WOFFSET             0
#define XUSB_DEV_CFG_18_PMCSR_0_DSCALE_INIT                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_SHIFT             _MK_SHIFT_CONST(15)
#define XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_FIELD            (_MK_SHIFT_CONST(0x1) << XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_SHIFT)
#define XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_RANGE            15:15
#define XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_WOFFSET          0
#define XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_SW_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_SW_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_NOT_PENDING      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_PENDING          _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_18_PMCSR_0_PMESTATUS_CLEAR            _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_CFG_18_PMCSR_0_BSE_RSVD_SHIFT              _MK_SHIFT_CONST(16)
#define XUSB_DEV_CFG_18_PMCSR_0_BSE_RSVD_FIELD             (_MK_SHIFT_CONST(0xff) << XUSB_DEV_CFG_18_PMCSR_0_BSE_RSVD_SHIFT)
#define XUSB_DEV_CFG_18_PMCSR_0_BSE_RSVD_RANGE             23:16
#define XUSB_DEV_CFG_18_PMCSR_0_BSE_RSVD_WOFFSET           0
#define XUSB_DEV_CFG_18_PMCSR_0_BSE_RSVD_00                _MK_ENUM_CONST(0x00000000)


// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// 
// 
// 
// .LABEL PUBLIC
// Following are registers required to support MSI interrupt modes.
// 
// //TBD - Define the interrupts and their purpose
// .TITLE MSI Message Control and Capability Register B0h
// 
// MSI_CTRL is the main control register for MSI support.
// 
// .FIELD CAP_ID
//    The CAP_ID field identifies this capability block as the MSI capability block.
// This is read-only as 0x5.
// .FIELD NEXT_PTR
//    The NEXT_PTR field identifies the next item in the capabilities list.  It is
// a read-only field.
// .FIELD MSI_ENABLE
//    The MSI_ENABLE field enables the MSI capability.  If MSI_ENABLE is written
// to a 1, the controller is permitted to use MSI to request service and is
// prohibited from using the legacy interrupt.  System configuration software
// sets this bit to enable MSI.
//    A device driver is prohibited from writing this bit to mask the
// controller's service request.
//    If this bit is written to a 0, the controller is prohibited from using
// MSI to request service.
// .FIELD MULT_MSG_CAP
//    System software reads this field to determine the number of requested
// vectors.  The number of requested vectors must be aligned to a power of two.
// Values of 6 and 7 in this field are reserved.
// .FIELD MULT_MSG_ENABLE
//    System software writes to this field to indicate the number of
// allocated vectors (less than or equal to  the number of vectors
// requested).  The number of vectors is aligned as a power of two.
// When MSI is enabled, the controller will be allocated at least one vector.
// .FIELD 64_ADDR_CAP
//    The 64_ADDR_CAP field indicates whether or not the controller is
// capable of generating a 64-bit message address.  A value of 1 means
// the controller is capable of generating a 64-bit message address.
// .FIELD VECTOR_MASK_CAP
//   The VECTOR_MASK_CAP field indicates whether or not the controller
// supports MSI-per-vector masking.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0|                                               | MSI_CTRL
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 


#define XUSB_DEV_MSI_CTRL_0                                _MK_ADDR_CONST(0x000000C0)
#define XUSB_DEV_MSI_CTRL_0_SECURE                         0
#define XUSB_DEV_MSI_CTRL_0_WORD_COUNT                     1
#define XUSB_DEV_MSI_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x800005)
#define XUSB_DEV_MSI_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0x1ffffff)
#define XUSB_DEV_MSI_CTRL_0_SW_DEFAULT_VAL                 _MK_MASK_CONST(0x800005)
#define XUSB_DEV_MSI_CTRL_0_SW_DEFAULT_MASK                _MK_MASK_CONST(0x1ffffff)
#define XUSB_DEV_MSI_CTRL_0_READ_MASK                      _MK_MASK_CONST(0x1ffffff)
#define XUSB_DEV_MSI_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x710000)
#define XUSB_DEV_MSI_CTRL_0_CLEAR_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_CTRL_0_TGL_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_CTRL_0_CAP_ID_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_DEV_MSI_CTRL_0_CAP_ID_FIELD                   (_MK_SHIFT_CONST(0xff) << XUSB_DEV_MSI_CTRL_0_CAP_ID_SHIFT)
#define XUSB_DEV_MSI_CTRL_0_CAP_ID_RANGE                   7:0
#define XUSB_DEV_MSI_CTRL_0_CAP_ID_WOFFSET                 0
#define XUSB_DEV_MSI_CTRL_0_CAP_ID_DEFAULT                 (_MK_MASK_CONST(0x00000005)
#define XUSB_DEV_MSI_CTRL_0_CAP_ID_DEFAULT_MASK            (_MK_MASK_CONST(0xff)
#define XUSB_DEV_MSI_CTRL_0_CAP_ID_SW_DEFAULT              (_MK_MASK_CONST(0x00000005)
#define XUSB_DEV_MSI_CTRL_0_CAP_ID_SW_DEFAULT_MASK         (_MK_MASK_CONST(0xff)
#define XUSB_DEV_MSI_CTRL_0_CAP_ID_MSI                     _MK_ENUM_CONST(0x00000005)
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_SHIFT                  _MK_SHIFT_CONST(8)
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_FIELD                 (_MK_SHIFT_CONST(0xff) << XUSB_DEV_MSI_CTRL_0_NEXT_PTR_SHIFT)
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_RANGE                 15:8
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_WOFFSET               0
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_SW_DEFAULT_MASK       (_MK_MASK_CONST(0xff)
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_MSIX                  _MK_ENUM_CONST(0x00000070)
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_MMAP                  _MK_ENUM_CONST(0x000000DC)
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_PMCAP                 _MK_ENUM_CONST(0x00000044)
#define XUSB_DEV_MSI_CTRL_0_NEXT_PTR_NULL                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_MSI_ENABLE_SHIFT                _MK_SHIFT_CONST(16)
#define XUSB_DEV_MSI_CTRL_0_MSI_ENABLE_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_MSI_CTRL_0_MSI_ENABLE_SHIFT)
#define XUSB_DEV_MSI_CTRL_0_MSI_ENABLE_RANGE               16:16
#define XUSB_DEV_MSI_CTRL_0_MSI_ENABLE_WOFFSET             0
#define XUSB_DEV_MSI_CTRL_0_MSI_ENABLE_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_MSI_ENABLE_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_CTRL_0_MSI_ENABLE_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_MSI_ENABLE_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_CTRL_0_MSI_ENABLE_OFF                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_MSI_ENABLE_ON                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_SHIFT              _MK_SHIFT_CONST(17)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_FIELD             (_MK_SHIFT_CONST(0x7) << XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_SHIFT)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_RANGE             19:17
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_WOFFSET           0
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_DEFAULT_MASK      (_MK_MASK_CONST(0x7)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x7)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_1                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_2                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_4                 _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_8                 _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_16                _MK_ENUM_CONST(0x00000004)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_CAP_32                _MK_ENUM_CONST(0x00000005)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_SHIFT           _MK_SHIFT_CONST(20)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_FIELD          (_MK_SHIFT_CONST(0x7) << XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_SHIFT)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_RANGE          22:20
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_WOFFSET        0
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_DEFAULT_MASK   (_MK_MASK_CONST(0x7)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x7)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_1              _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_2              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_4              _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_8              _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_16             _MK_ENUM_CONST(0x00000004)
#define XUSB_DEV_MSI_CTRL_0_MULT_MSG_ENABLE_32             _MK_ENUM_CONST(0x00000005)
#define XUSB_DEV_MSI_CTRL_0_64_ADDR_CAP_SHIFT               _MK_SHIFT_CONST(23)
#define XUSB_DEV_MSI_CTRL_0_64_ADDR_CAP_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_MSI_CTRL_0_64_ADDR_CAP_SHIFT)
#define XUSB_DEV_MSI_CTRL_0_64_ADDR_CAP_RANGE              23:23
#define XUSB_DEV_MSI_CTRL_0_64_ADDR_CAP_WOFFSET            0
#define XUSB_DEV_MSI_CTRL_0_64_ADDR_CAP_DEFAULT            (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_MSI_CTRL_0_64_ADDR_CAP_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_CTRL_0_64_ADDR_CAP_SW_DEFAULT         (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_MSI_CTRL_0_64_ADDR_CAP_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_CTRL_0_64_ADDR_CAP_DIS                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_64_ADDR_CAP_EN                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_MSI_CTRL_0_VECTOR_MASK_CAP_SHIFT           _MK_SHIFT_CONST(24)
#define XUSB_DEV_MSI_CTRL_0_VECTOR_MASK_CAP_FIELD          (_MK_SHIFT_CONST(0x1) << XUSB_DEV_MSI_CTRL_0_VECTOR_MASK_CAP_SHIFT)
#define XUSB_DEV_MSI_CTRL_0_VECTOR_MASK_CAP_RANGE          24:24
#define XUSB_DEV_MSI_CTRL_0_VECTOR_MASK_CAP_WOFFSET        0
#define XUSB_DEV_MSI_CTRL_0_VECTOR_MASK_CAP_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_VECTOR_MASK_CAP_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_CTRL_0_VECTOR_MASK_CAP_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_VECTOR_MASK_CAP_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_CTRL_0_VECTOR_MASK_CAP_DIS            _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_MSI_CTRL_0_VECTOR_MASK_CAP_EN             _MK_ENUM_CONST(0x00000001)


// 
//                 Figure 10-42
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// 
// 
// .TITLE MSI Message Address Register 84h
// 
// MSI_ADDR1 specifies the lower 32 bits to which a MSI memory write transaction
// should occur.
// 
// .FIELD MSG_ADDR
//    System-specified message address.  When MSI is enabled, this field
// specifies the dword-aligned address for the MSI memory write transaction.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |                                                           |0 0| MSI_ADDR1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 


#define XUSB_DEV_MSI_ADDR1_0                               _MK_ADDR_CONST(0x000000C4)
#define XUSB_DEV_MSI_ADDR1_0_SECURE                        0
#define XUSB_DEV_MSI_ADDR1_0_WORD_COUNT                    1
#define XUSB_DEV_MSI_ADDR1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_ADDR1_0_RESET_MASK                    _MK_MASK_CONST(0xfffffffc)
#define XUSB_DEV_MSI_ADDR1_0_SW_DEFAULT_VAL                _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_ADDR1_0_SW_DEFAULT_MASK               _MK_MASK_CONST(0xfffffffc)
#define XUSB_DEV_MSI_ADDR1_0_READ_MASK                     _MK_MASK_CONST(0xfffffffc)
#define XUSB_DEV_MSI_ADDR1_0_WRITE_MASK                    _MK_MASK_CONST(0xfffffffc)
#define XUSB_DEV_MSI_ADDR1_0_CLEAR_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_ADDR1_0_TGL_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_ADDR1_0_MSG_ADDR_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_DEV_MSI_ADDR1_0_MSG_ADDR_FIELD                (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_MSI_ADDR1_0_MSG_ADDR_SHIFT)
#define XUSB_DEV_MSI_ADDR1_0_MSG_ADDR_RANGE                31:2
#define XUSB_DEV_MSI_ADDR1_0_MSG_ADDR_WOFFSET              0
#define XUSB_DEV_MSI_ADDR1_0_MSG_ADDR_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_ADDR1_0_MSG_ADDR_DEFAULT_MASK         (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_MSI_ADDR1_0_MSG_ADDR_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_ADDR1_0_MSG_ADDR_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x3fffffff)


// 
//                 Figure 10-43
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// 
// .TITLE MSI Message Upper Address Register 88h
// 
// MSI_ADDR2 specifies the upper 32 bits to which a MSI memory write transaction
// should occur.
// 
// .FIELD MSG_ADDR
//    System-specified message address.  When MSI is enabled, this field
// specifies the upper 32-bits of the address for the MSI memory
// write transaction.  The contents of this register only apply
// when T_XUSB_DEV_CFG_MSI_CTRL_64_ADDR_CAP bit is set.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|               | MSI_ADDR2
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 


#define XUSB_DEV_MSI_ADDR2_0                               _MK_ADDR_CONST(0x000000C8)
#define XUSB_DEV_MSI_ADDR2_0_SECURE                        0
#define XUSB_DEV_MSI_ADDR2_0_WORD_COUNT                    1
#define XUSB_DEV_MSI_ADDR2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_ADDR2_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_MSI_ADDR2_0_SW_DEFAULT_VAL                _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_ADDR2_0_SW_DEFAULT_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_MSI_ADDR2_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_MSI_ADDR2_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_MSI_ADDR2_0_CLEAR_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_ADDR2_0_TGL_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_ADDR2_0_MSG_ADDR_SHIFT                 _MK_SHIFT_CONST(0)
#define XUSB_DEV_MSI_ADDR2_0_MSG_ADDR_FIELD                (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_MSI_ADDR2_0_MSG_ADDR_SHIFT)
#define XUSB_DEV_MSI_ADDR2_0_MSG_ADDR_RANGE                31:0
#define XUSB_DEV_MSI_ADDR2_0_MSG_ADDR_WOFFSET              0
#define XUSB_DEV_MSI_ADDR2_0_MSG_ADDR_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_ADDR2_0_MSG_ADDR_DEFAULT_MASK         (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_MSI_ADDR2_0_MSG_ADDR_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_ADDR2_0_MSG_ADDR_SW_DEFAULT_MASK      (_MK_MASK_CONST(0xffffffff)


// 
//                 Figure 10-44
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// 
// .TITLE MSI Message Data Register 8Ch
// 
// The MSI_DATA register contains the system-specified message.
// 
// .FIELD MSG_DATA
// System-specified message  When MSI is enabled, the message
// data is driven onto the lower 16-bits of the MSI memory write.
// 
// The MULT_MSG_ENABLE field in configuration register 80h specifies
// the number of low order message data bits that the XHCI is permitted
// to modify to generate its system software allocated vectors.
// 
// //Essentially, MSG_DATA contains the base MSI message data for
// //MSI vector 0.  For MSI vector 1, the message data that will be sent
// //out will be (MSG_DATA + 1); for MSI vector 2, message data that
// //will be sent out will be (MSG_DATA + 2), etc.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|                               | MSI_DATA
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 


#define XUSB_DEV_MSI_DATA_0                                _MK_ADDR_CONST(0x000000CC)
#define XUSB_DEV_MSI_DATA_0_SECURE                         0
#define XUSB_DEV_MSI_DATA_0_WORD_COUNT                     1
#define XUSB_DEV_MSI_DATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_DATA_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
#define XUSB_DEV_MSI_DATA_0_SW_DEFAULT_VAL                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_DATA_0_SW_DEFAULT_MASK                _MK_MASK_CONST(0xffff)
#define XUSB_DEV_MSI_DATA_0_READ_MASK                      _MK_MASK_CONST(0xffff)
#define XUSB_DEV_MSI_DATA_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
#define XUSB_DEV_MSI_DATA_0_CLEAR_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_DATA_0_TGL_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_DATA_0_MSG_DATA_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_DEV_MSI_DATA_0_MSG_DATA_FIELD                 (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_MSI_DATA_0_MSG_DATA_SHIFT)
#define XUSB_DEV_MSI_DATA_0_MSG_DATA_RANGE                 15:0
#define XUSB_DEV_MSI_DATA_0_MSG_DATA_WOFFSET               0
#define XUSB_DEV_MSI_DATA_0_MSG_DATA_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_DATA_0_MSG_DATA_DEFAULT_MASK          (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_MSI_DATA_0_MSG_DATA_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_DATA_0_MSG_DATA_SW_DEFAULT_MASK       (_MK_MASK_CONST(0xffff)


// 
//                 Figure 10-45
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// 
// 
// .TITLE MSI Mask Bits Register 60h
// 
// The MSI_MASK register enables software to mask or defer message
// generation on a per-vector basis.
// 
// .FIELD BIT
// For each mask bit that is set, the controller is prohibited from
// generating the associated message.
//         bit 0 corresponds to MSI vector 0
//         bit 1 corresponds to MSI vector 1
//         bit 2 corresponds to MSI vector 2
//         bit 3 corresponds to MSI vector 3
//         bit 4 corresponds to MSI vector 4
//         bit 5 corresponds to MSI vector 5
//         bit 6 corresponds to MSI vector 6
//         bit 7 corresponds to MSI vector 7
//                 etc.
// 
// //Remember, a value of 0 means to allow MSI generation for
// //that vector; value of 1 means to prevent MSI generation
// //for that vector.
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|                               | MSI_MASK
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 


#define XUSB_DEV_MSI_MASK_0                                _MK_ADDR_CONST(0x000000D0)
#define XUSB_DEV_MSI_MASK_0_SECURE                         0
#define XUSB_DEV_MSI_MASK_0_WORD_COUNT                     1
#define XUSB_DEV_MSI_MASK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_MASK_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_MASK_0_SW_DEFAULT_VAL                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_MASK_0_SW_DEFAULT_MASK                _MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_MASK_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_MASK_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_MASK_0_CLEAR_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_MASK_0_TGL_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_MASK_0_BIT_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_DEV_MSI_MASK_0_BIT_FIELD                      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_MSI_MASK_0_BIT_SHIFT)
#define XUSB_DEV_MSI_MASK_0_BIT_RANGE                      0:0
#define XUSB_DEV_MSI_MASK_0_BIT_WOFFSET                    0
#define XUSB_DEV_MSI_MASK_0_BIT_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_MASK_0_BIT_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_MASK_0_BIT_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_MASK_0_BIT_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_MASK_0_BIT__NOPRDCHK                  _MK_ENUM_CONST(0x00000001)


// 
//                 Figure 10-24  PCI Configuration Register 60h
// 
// .TITLE MSI Pending Bits Register 64h
// 
// The MSI_PEND register shows which MSI vectors have pending interrupts.
// 
// .FIELD BIT
// For each Pending bit that is set XUSB has a pending associated message.
// 
//         bit 0 corresponds to MSI vector 0
//         bit 1 corresponds to MSI vector 1
//         bit 2 corresponds to MSI vector 2
//         bit 3 corresponds to MSI vector 3
//         bit 4 corresponds to MSI vector 4
//         bit 5 corresponds to MSI vector 5
//         bit 6 corresponds to MSI vector 6
//         bit 7 corresponds to MSI vector 7
//                 etc.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|                               | MSI_PEND
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 


#define XUSB_DEV_MSI_PEND_0                                _MK_ADDR_CONST(0x000000D4)
#define XUSB_DEV_MSI_PEND_0_SECURE                         0
#define XUSB_DEV_MSI_PEND_0_WORD_COUNT                     1
#define XUSB_DEV_MSI_PEND_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_PEND_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
#define XUSB_DEV_MSI_PEND_0_SW_DEFAULT_VAL                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_PEND_0_SW_DEFAULT_MASK                _MK_MASK_CONST(0xffff)
#define XUSB_DEV_MSI_PEND_0_READ_MASK                      _MK_MASK_CONST(0xffff)
#define XUSB_DEV_MSI_PEND_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_PEND_0_CLEAR_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_PEND_0_TGL_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_PEND_0_BIT_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_DEV_MSI_PEND_0_BIT_FIELD                      (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_MSI_PEND_0_BIT_SHIFT)
#define XUSB_DEV_MSI_PEND_0_BIT_RANGE                      15:0
#define XUSB_DEV_MSI_PEND_0_BIT_WOFFSET                    0
#define XUSB_DEV_MSI_PEND_0_BIT_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_PEND_0_BIT_DEFAULT_MASK               (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_MSI_PEND_0_BIT_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_PEND_0_BIT_SW_DEFAULT_MASK            (_MK_MASK_CONST(0xffff)


// 
//                 Figure 10-25  PCI Configuration Register 64h
// 
// .LABEL CYA_PRIVATE INT_REL
// 
// .TITLE MSI Message Queue Configuration Register 68h
// 
// The MSI_QUEUE register is a private register.  It specifies to which
// virtual channel queue (ISO or NON-ISO) that the MSI message will be
// sent to before being sent out on FPCI bus.
// 
// //Note:  When the MSI message is created, the FPCI wrapper won't know
// //       which physical queue to put the MSI message into.  The MSI_QUEUE
// //       setting will determine this on a vector-by-vector basis.  If
// //       the corresponding bit is set to 1, FPCI wrapper will put
// //       that MSI message into the ISO command/data queue; otherwise
// //       by default the message is placed in the NONISO queue.
// //       After the MSI message is popped from the ISO/NONISO queue,
// //       the settings in FPCICFG_ISOCMD, FPCICFG_PASSPW, and FPCICFG_RSPPASSPW
// //       will apply.  Since the XUSB FPCI wrapper, physically, only contains
// //       the NONISO command/data queues (from MCP8x and beyond), the
// //       MSI_QUEUE bits must be all set to 0 for all MSI vectors.
// 
// .FIELD BITS
// The BITS field specifies to which VC queue a particular MSI message will be sent to.
// 
//         bit 0 corresponds to MSI vector 0
//         bit 1 corresponds to MSI vector 1
//         bit 2 corresponds to MSI vector 2
//         bit 3 corresponds to MSI vector 3
//         bit 4 corresponds to MSI vector 4
//         bit 5 corresponds to MSI vector 5
//         bit 6 corresponds to MSI vector 6
//         bit 7 corresponds to MSI vector 7
//                 etc.
// 
// //TBD - Change for XUSB
// //        Since XUSB only has an NONISO queue in recent chipsets, the queue
// //        bits should be set to 0x0000 (all MSI messages go to the NONISO queue)
// //              Note:  XUSB only has NONISO QUEUE from MCP8x and beyond
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|                               | MSI_QUEUE
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 


#define XUSB_DEV_MSI_QUEUE_0                               _MK_ADDR_CONST(0x000000D8)
#define XUSB_DEV_MSI_QUEUE_0_SECURE                        0
#define XUSB_DEV_MSI_QUEUE_0_WORD_COUNT                    1
#define XUSB_DEV_MSI_QUEUE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_QUEUE_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_QUEUE_0_SW_DEFAULT_VAL                _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_QUEUE_0_SW_DEFAULT_MASK               _MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_QUEUE_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_QUEUE_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_QUEUE_0_CLEAR_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_QUEUE_0_TGL_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_QUEUE_0_BITS_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_DEV_MSI_QUEUE_0_BITS_FIELD                    (_MK_SHIFT_CONST(0x1) << XUSB_DEV_MSI_QUEUE_0_BITS_SHIFT)
#define XUSB_DEV_MSI_QUEUE_0_BITS_RANGE                    0:0
#define XUSB_DEV_MSI_QUEUE_0_BITS_WOFFSET                  0
#define XUSB_DEV_MSI_QUEUE_0_BITS_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_QUEUE_0_BITS_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_QUEUE_0_BITS_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_QUEUE_0_BITS_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_QUEUE_0_BITS_ALL_NONISO               _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_MSI_QUEUE_0_BITS_ALL_ISO                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_MSI_QUEUE_0_BITS__PROD                    _MK_ENUM_CONST(0x00000000)


// 
//                 Figure 10-26  PCI Configuration Register 68h
// 
// .LABEL PCI_CONFIG
// 
// .TITLE MSI Mapping Capability Register 6Ch
// 
// The MSI_MAP register is used to tell the OS that MSIs are supported in K8 mode.
// //The register is for S/W information purposes only and doesn't do anything in H/W.
// 
// This is the per-device HT MSI Capability Block.
// 
// //From the HT 2.00a Draft 3 spec:
// //This capability is used by PCI bridges to define the address range where MSIs are
// //mapped to HT interrupt messages.  There must be an MSI mapping capability in each device
// //number that supports MSI mapping, preferably in function 0.  The capability affects
// //MSIs generated in all functions of that device.  It is expected that all MSI mapping
// //capabilities found in a system will be programmed with the same address.
// 
// .FIELD CAP_ID
//    The CAP_ID field identifies that this is an HT capability
// list item. (Read-only as 0x8).
// 
// .FIELD NEXT_PTR
//    The NEXT_PTR field points to the next item in the capabilities list.
// It is a read-only field.
// //In MCP04/CK804/MCP51, this points to NULL (end of list).
// 
// .FIELD EN
//    The EN bit indicates if the mapping is active.  It is cleared upon warm reset.
// 
// .FIELD FIXD
//    The FIXD bit is a read-only bit indicating if the the next 2 dwords
// for programmable address are present in the capability.  If set, the
// address for mapping MSIs is fixed at 0x0000_0000_FEEx_xxxx and that this
// capability block is 1 dword long.
// 
// .FIELD CAP_TYPE
//    The CAP_TYPE    field is read only at 0x15 to indicate that this is an MSI
// Mapping Capability block.
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |1 0 1 0 1|0 0 0|0 0 0 0 0 0|1| |0 0 0 0 0 0 0 0|0 0 0 0 1 0 0 0| MSI_MAP
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 


#define XUSB_DEV_MSI_MAP_0                                 _MK_ADDR_CONST(0x000000DC)
#define XUSB_DEV_MSI_MAP_0_SECURE                          0
#define XUSB_DEV_MSI_MAP_0_WORD_COUNT                      1
#define XUSB_DEV_MSI_MAP_0_RESET_VAL                       _MK_MASK_CONST(0xa8020008)
#define XUSB_DEV_MSI_MAP_0_RESET_MASK                      _MK_MASK_CONST(0xf803ffff)
#define XUSB_DEV_MSI_MAP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0xa8020008)
#define XUSB_DEV_MSI_MAP_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0xf803ffff)
#define XUSB_DEV_MSI_MAP_0_READ_MASK                       _MK_MASK_CONST(0xf803ffff)
#define XUSB_DEV_MSI_MAP_0_WRITE_MASK                      _MK_MASK_CONST(0x10000)
#define XUSB_DEV_MSI_MAP_0_CLEAR_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_MAP_0_TGL_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_MSI_MAP_0_CAP_TYPE_SHIFT                   _MK_SHIFT_CONST(27)
#define XUSB_DEV_MSI_MAP_0_CAP_TYPE_FIELD                  (_MK_SHIFT_CONST(0x1f) << XUSB_DEV_MSI_MAP_0_CAP_TYPE_SHIFT)
#define XUSB_DEV_MSI_MAP_0_CAP_TYPE_RANGE                  31:27
#define XUSB_DEV_MSI_MAP_0_CAP_TYPE_WOFFSET                0
#define XUSB_DEV_MSI_MAP_0_CAP_TYPE_DEFAULT                (_MK_MASK_CONST(0x00000015)
#define XUSB_DEV_MSI_MAP_0_CAP_TYPE_DEFAULT_MASK           (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_MSI_MAP_0_CAP_TYPE_SW_DEFAULT             (_MK_MASK_CONST(0x00000015)
#define XUSB_DEV_MSI_MAP_0_CAP_TYPE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_MSI_MAP_0_FIXD_SHIFT                       _MK_SHIFT_CONST(17)
#define XUSB_DEV_MSI_MAP_0_FIXD_FIELD                      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_MSI_MAP_0_FIXD_SHIFT)
#define XUSB_DEV_MSI_MAP_0_FIXD_RANGE                      17:17
#define XUSB_DEV_MSI_MAP_0_FIXD_WOFFSET                    0
#define XUSB_DEV_MSI_MAP_0_FIXD_DEFAULT                    (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_MSI_MAP_0_FIXD_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_MAP_0_FIXD_SW_DEFAULT                 (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_MSI_MAP_0_FIXD_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_MAP_0_FIXD_ON                         _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_MSI_MAP_0_EN_SHIFT                         _MK_SHIFT_CONST(16)
#define XUSB_DEV_MSI_MAP_0_EN_FIELD                        (_MK_SHIFT_CONST(0x1) << XUSB_DEV_MSI_MAP_0_EN_SHIFT)
#define XUSB_DEV_MSI_MAP_0_EN_RANGE                        16:16
#define XUSB_DEV_MSI_MAP_0_EN_WOFFSET                      0
#define XUSB_DEV_MSI_MAP_0_EN_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_MAP_0_EN_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_MAP_0_EN_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_MAP_0_EN_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define XUSB_DEV_MSI_MAP_0_EN__NOPRDCHK                    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_MSI_MAP_0_EN_OFF                          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_MSI_MAP_0_EN_ON                           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_SHIFT                   _MK_SHIFT_CONST(8)
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_FIELD                  (_MK_SHIFT_CONST(0xff) << XUSB_DEV_MSI_MAP_0_NEXT_PTR_SHIFT)
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_RANGE                  15:8
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_WOFFSET                0
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_DEFAULT_MASK           (_MK_MASK_CONST(0xff)
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_SW_DEFAULT_MASK        (_MK_MASK_CONST(0xff)
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_MSI                    _MK_ENUM_CONST(0x000000C0)
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_MSIX                   _MK_ENUM_CONST(0x00000070)
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_PMCAP                  _MK_ENUM_CONST(0x00000044)
#define XUSB_DEV_MSI_MAP_0_NEXT_PTR_NULL                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_MSI_MAP_0_CAP_ID_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_DEV_MSI_MAP_0_CAP_ID_FIELD                    (_MK_SHIFT_CONST(0xff) << XUSB_DEV_MSI_MAP_0_CAP_ID_SHIFT)
#define XUSB_DEV_MSI_MAP_0_CAP_ID_RANGE                    7:0
#define XUSB_DEV_MSI_MAP_0_CAP_ID_WOFFSET                  0
#define XUSB_DEV_MSI_MAP_0_CAP_ID_DEFAULT                  (_MK_MASK_CONST(0x00000008)
#define XUSB_DEV_MSI_MAP_0_CAP_ID_DEFAULT_MASK             (_MK_MASK_CONST(0xff)
#define XUSB_DEV_MSI_MAP_0_CAP_ID_SW_DEFAULT               (_MK_MASK_CONST(0x00000008)
#define XUSB_DEV_MSI_MAP_0_CAP_ID_SW_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define XUSB_DEV_MSI_MAP_0_CAP_ID_MSI                      _MK_ENUM_CONST(0x00000008)


// 
//                 Figure 10-27  PCI Configuration Register 6Ch
// 
// 
// .LABEL INT_REL
// .POWER MAIN
// 
// .TITLE XUSB Internal Bus Configuration
//     The AXI Config register provides configuration options to the C112AXI Wrapper
// 
// 
//  31           24 23           16 15            8 7             0
// .-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-.
// |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| AXICFG
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// 


#define XUSB_DEV_AXI_CFG_0                                 _MK_ADDR_CONST(0x000000F8)
#define XUSB_DEV_AXI_CFG_0_SECURE                          0
#define XUSB_DEV_AXI_CFG_0_WORD_COUNT                      1
#define XUSB_DEV_AXI_CFG_0_RESET_VAL                       _MK_MASK_CONST(0xa)
#define XUSB_DEV_AXI_CFG_0_RESET_MASK                      _MK_MASK_CONST(0x11f)
#define XUSB_DEV_AXI_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0xa)
#define XUSB_DEV_AXI_CFG_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x11f)
#define XUSB_DEV_AXI_CFG_0_READ_MASK                       _MK_MASK_CONST(0x11f)
#define XUSB_DEV_AXI_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0x11f)
#define XUSB_DEV_AXI_CFG_0_CLEAR_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_DEV_AXI_CFG_0_TGL_MASK                        _MK_MASK_CONST(0x100)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_COH_SHIFT               _MK_SHIFT_CONST(0)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_COH_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_AXI_CFG_0_AR_FORCE_COH_SHIFT)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_COH_RANGE              0:0
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_COH_WOFFSET            0
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_COH_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_COH_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_COH_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_COH_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_COH_FALSE              _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_COH_TRUE               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_NONCOH_SHIFT            _MK_SHIFT_CONST(1)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_NONCOH_FIELD           (_MK_SHIFT_CONST(0x1) << XUSB_DEV_AXI_CFG_0_AR_FORCE_NONCOH_SHIFT)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_NONCOH_RANGE           1:1
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_NONCOH_WOFFSET         0
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_NONCOH_DEFAULT         (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_NONCOH_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_NONCOH_SW_DEFAULT      (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_NONCOH_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_NONCOH_FALSE           _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_AR_FORCE_NONCOH_TRUE            _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_COH_SHIFT               _MK_SHIFT_CONST(2)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_COH_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_AXI_CFG_0_AW_FORCE_COH_SHIFT)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_COH_RANGE              2:2
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_COH_WOFFSET            0
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_COH_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_COH_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_COH_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_COH_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_COH_FALSE              _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_COH_TRUE               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_NONCOH_SHIFT            _MK_SHIFT_CONST(3)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_NONCOH_FIELD           (_MK_SHIFT_CONST(0x1) << XUSB_DEV_AXI_CFG_0_AW_FORCE_NONCOH_SHIFT)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_NONCOH_RANGE           3:3
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_NONCOH_WOFFSET         0
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_NONCOH_DEFAULT         (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_NONCOH_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_NONCOH_SW_DEFAULT      (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_NONCOH_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_NONCOH_FALSE           _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_AW_FORCE_NONCOH_TRUE            _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_AXI_CFG_0_ORDER_RSP_VS_WRITES_SHIFT        _MK_SHIFT_CONST(4)
#define XUSB_DEV_AXI_CFG_0_ORDER_RSP_VS_WRITES_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_AXI_CFG_0_ORDER_RSP_VS_WRITES_SHIFT)
#define XUSB_DEV_AXI_CFG_0_ORDER_RSP_VS_WRITES_RANGE       4:4
#define XUSB_DEV_AXI_CFG_0_ORDER_RSP_VS_WRITES_WOFFSET     0
#define XUSB_DEV_AXI_CFG_0_ORDER_RSP_VS_WRITES_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_ORDER_RSP_VS_WRITES_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_ORDER_RSP_VS_WRITES_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_ORDER_RSP_VS_WRITES_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_ORDER_RSP_VS_WRITES_FALSE       _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_ORDER_RSP_VS_WRITES_TRUE        _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_SHIFT               _MK_SHIFT_CONST(8)
#define XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_SHIFT)
#define XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_RANGE              8:8
#define XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_WOFFSET            0
#define XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_NOT_PENDING        _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_PENDING            _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_AXI_CFG_0_CLR_MSI_INTR_TRIGGER            _MK_ENUM_CONST(0x00000001)


// 
// 
// 
// TBD - PCIE CAP and HT MSI CAP
// 
// 
// // Init registers to be used by advanced ref manual flow
// 
// // Initialize Base address for XHCI BAR0 Space.
// .INIT_REG T_XUSB_DEV_CFG_4
// .INIT_REG T_XUSB_DEV_CFG_5
// 
// // Enable MMIO decoding and Bus mastering capabilities of the Bus wrapper.
// .INIT_REG T_XUSB_DEV_CFG_1
// 
// 
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// 

// REGISTER LIST

#define LIST_XUSB_DEV_0_REGS(_op_) \
  _op_(XUSB_DEV_CFG_0_0) \
  _op_(XUSB_DEV_CFG_1_0) \
  _op_(XUSB_DEV_CFG_2_0) \
  _op_(XUSB_DEV_CFG_3_0) \
  _op_(XUSB_DEV_CFG_4_0) \
  _op_(XUSB_DEV_CFG_5_0) \
  _op_(XUSB_DEV_CFG_6_0) \
  _op_(XUSB_DEV_CFG_6_1) \
  _op_(XUSB_DEV_CFG_6_2) \
  _op_(XUSB_DEV_CFG_6_3) \
  _op_(XUSB_DEV_CFG_6_4) \
  _op_(XUSB_DEV_CFG_11_0) \
  _op_(XUSB_DEV_CFG_12_0) \
  _op_(XUSB_DEV_CFG_13_0) \
  _op_(XUSB_DEV_CFG_14_0) \
  _op_(XUSB_DEV_CFG_15_0) \
  _op_(XUSB_DEV_CFG_16_0) \
  _op_(XUSB_DEV_CFG_17_0) \
  _op_(XUSB_DEV_CFG_18_PMCSR_0) \
  _op_(XUSB_DEV_MSI_CTRL_0) \
  _op_(XUSB_DEV_MSI_ADDR1_0) \
  _op_(XUSB_DEV_MSI_ADDR2_0) \
  _op_(XUSB_DEV_MSI_DATA_0) \
  _op_(XUSB_DEV_MSI_MASK_0) \
  _op_(XUSB_DEV_MSI_PEND_0) \
  _op_(XUSB_DEV_MSI_QUEUE_0) \
  _op_(XUSB_DEV_MSI_MAP_0) \
  _op_(XUSB_DEV_AXI_CFG_0) 


#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif

#endif
