//
// Copyright (c) 2014 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//  * Redistributions of source code must retain the above copyright
//    notice, this list of conditions and the following disclaimer.
//  * Redistributions in binary form must reproduce the above copyright
//    notice, this list of conditions and the following disclaimer in the
//    documentation and/or other materials provided with the distribution.
//  * Neither the name of NVIDIA CORPORATION nor the names of its
//    contributors may be used to endorse or promote products derived
//    from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARAPBDMA_H_INC_
#define ___ARAPBDMA_H_INC_

// Register APBDMA_COMMAND_0
#define APBDMA_COMMAND_0                        _MK_ADDR_CONST(0x0)
#define APBDMA_COMMAND_0_SECURE                         0x0
#define APBDMA_COMMAND_0_SCR                    0
#define APBDMA_COMMAND_0_WORD_COUNT                     0x1
#define APBDMA_COMMAND_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APBDMA_COMMAND_0_RESET_MASK                     _MK_MASK_CONST(0x80000000)
#define APBDMA_COMMAND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APBDMA_COMMAND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_COMMAND_0_READ_MASK                      _MK_MASK_CONST(0x80000000)
#define APBDMA_COMMAND_0_WRITE_MASK                     _MK_MASK_CONST(0x80000000)
#define APBDMA_COMMAND_0_GEN_SHIFT                      _MK_SHIFT_CONST(31)
#define APBDMA_COMMAND_0_GEN_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_COMMAND_0_GEN_SHIFT)
#define APBDMA_COMMAND_0_GEN_RANGE                      31:31
#define APBDMA_COMMAND_0_GEN_WOFFSET                    0x0
#define APBDMA_COMMAND_0_GEN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_COMMAND_0_GEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_COMMAND_0_GEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_COMMAND_0_GEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_COMMAND_0_GEN_DISABLE                    _MK_ENUM_CONST(0)
#define APBDMA_COMMAND_0_GEN_ENABLE                     _MK_ENUM_CONST(1)


// Register APBDMA_STATUS_0
#define APBDMA_STATUS_0                 _MK_ADDR_CONST(0x4)
#define APBDMA_STATUS_0_SECURE                  0x0
#define APBDMA_STATUS_0_SCR                     0
#define APBDMA_STATUS_0_WORD_COUNT                      0x1
#define APBDMA_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define APBDMA_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define APBDMA_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_31_SHIFT                    _MK_SHIFT_CONST(31)
#define APBDMA_STATUS_0_BSY_31_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_31_SHIFT)
#define APBDMA_STATUS_0_BSY_31_RANGE                    31:31
#define APBDMA_STATUS_0_BSY_31_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_31_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_31_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_31_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_31_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_31_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_31_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_30_SHIFT                    _MK_SHIFT_CONST(30)
#define APBDMA_STATUS_0_BSY_30_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_30_SHIFT)
#define APBDMA_STATUS_0_BSY_30_RANGE                    30:30
#define APBDMA_STATUS_0_BSY_30_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_30_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_30_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_30_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_30_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_30_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_30_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_29_SHIFT                    _MK_SHIFT_CONST(29)
#define APBDMA_STATUS_0_BSY_29_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_29_SHIFT)
#define APBDMA_STATUS_0_BSY_29_RANGE                    29:29
#define APBDMA_STATUS_0_BSY_29_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_29_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_29_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_29_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_29_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_29_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_29_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_28_SHIFT                    _MK_SHIFT_CONST(28)
#define APBDMA_STATUS_0_BSY_28_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_28_SHIFT)
#define APBDMA_STATUS_0_BSY_28_RANGE                    28:28
#define APBDMA_STATUS_0_BSY_28_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_28_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_28_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_28_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_28_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_28_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_28_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_27_SHIFT                    _MK_SHIFT_CONST(27)
#define APBDMA_STATUS_0_BSY_27_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_27_SHIFT)
#define APBDMA_STATUS_0_BSY_27_RANGE                    27:27
#define APBDMA_STATUS_0_BSY_27_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_27_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_27_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_27_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_27_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_27_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_27_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_26_SHIFT                    _MK_SHIFT_CONST(26)
#define APBDMA_STATUS_0_BSY_26_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_26_SHIFT)
#define APBDMA_STATUS_0_BSY_26_RANGE                    26:26
#define APBDMA_STATUS_0_BSY_26_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_26_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_26_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_26_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_26_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_26_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_26_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_25_SHIFT                    _MK_SHIFT_CONST(25)
#define APBDMA_STATUS_0_BSY_25_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_25_SHIFT)
#define APBDMA_STATUS_0_BSY_25_RANGE                    25:25
#define APBDMA_STATUS_0_BSY_25_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_25_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_25_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_25_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_25_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_25_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_25_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_24_SHIFT                    _MK_SHIFT_CONST(24)
#define APBDMA_STATUS_0_BSY_24_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_24_SHIFT)
#define APBDMA_STATUS_0_BSY_24_RANGE                    24:24
#define APBDMA_STATUS_0_BSY_24_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_24_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_24_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_24_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_24_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_24_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_24_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_23_SHIFT                    _MK_SHIFT_CONST(23)
#define APBDMA_STATUS_0_BSY_23_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_23_SHIFT)
#define APBDMA_STATUS_0_BSY_23_RANGE                    23:23
#define APBDMA_STATUS_0_BSY_23_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_23_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_23_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_23_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_23_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_23_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_23_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_22_SHIFT                    _MK_SHIFT_CONST(22)
#define APBDMA_STATUS_0_BSY_22_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_22_SHIFT)
#define APBDMA_STATUS_0_BSY_22_RANGE                    22:22
#define APBDMA_STATUS_0_BSY_22_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_22_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_22_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_22_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_22_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_22_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_22_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_21_SHIFT                    _MK_SHIFT_CONST(21)
#define APBDMA_STATUS_0_BSY_21_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_21_SHIFT)
#define APBDMA_STATUS_0_BSY_21_RANGE                    21:21
#define APBDMA_STATUS_0_BSY_21_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_21_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_21_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_21_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_21_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_21_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_21_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_20_SHIFT                    _MK_SHIFT_CONST(20)
#define APBDMA_STATUS_0_BSY_20_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_20_SHIFT)
#define APBDMA_STATUS_0_BSY_20_RANGE                    20:20
#define APBDMA_STATUS_0_BSY_20_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_20_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_20_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_20_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_20_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_20_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_20_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_19_SHIFT                    _MK_SHIFT_CONST(19)
#define APBDMA_STATUS_0_BSY_19_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_19_SHIFT)
#define APBDMA_STATUS_0_BSY_19_RANGE                    19:19
#define APBDMA_STATUS_0_BSY_19_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_19_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_19_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_19_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_19_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_19_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_19_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_18_SHIFT                    _MK_SHIFT_CONST(18)
#define APBDMA_STATUS_0_BSY_18_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_18_SHIFT)
#define APBDMA_STATUS_0_BSY_18_RANGE                    18:18
#define APBDMA_STATUS_0_BSY_18_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_18_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_18_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_18_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_18_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_18_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_18_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_17_SHIFT                    _MK_SHIFT_CONST(17)
#define APBDMA_STATUS_0_BSY_17_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_17_SHIFT)
#define APBDMA_STATUS_0_BSY_17_RANGE                    17:17
#define APBDMA_STATUS_0_BSY_17_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_17_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_17_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_17_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_17_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_17_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_17_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_16_SHIFT                    _MK_SHIFT_CONST(16)
#define APBDMA_STATUS_0_BSY_16_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_16_SHIFT)
#define APBDMA_STATUS_0_BSY_16_RANGE                    16:16
#define APBDMA_STATUS_0_BSY_16_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_16_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_16_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_16_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_16_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_16_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_16_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_15_SHIFT                    _MK_SHIFT_CONST(15)
#define APBDMA_STATUS_0_BSY_15_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_15_SHIFT)
#define APBDMA_STATUS_0_BSY_15_RANGE                    15:15
#define APBDMA_STATUS_0_BSY_15_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_15_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_15_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_15_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_14_SHIFT                    _MK_SHIFT_CONST(14)
#define APBDMA_STATUS_0_BSY_14_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_14_SHIFT)
#define APBDMA_STATUS_0_BSY_14_RANGE                    14:14
#define APBDMA_STATUS_0_BSY_14_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_14_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_14_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_14_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_13_SHIFT                    _MK_SHIFT_CONST(13)
#define APBDMA_STATUS_0_BSY_13_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_13_SHIFT)
#define APBDMA_STATUS_0_BSY_13_RANGE                    13:13
#define APBDMA_STATUS_0_BSY_13_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_13_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_13_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_13_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_12_SHIFT                    _MK_SHIFT_CONST(12)
#define APBDMA_STATUS_0_BSY_12_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_12_SHIFT)
#define APBDMA_STATUS_0_BSY_12_RANGE                    12:12
#define APBDMA_STATUS_0_BSY_12_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_12_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_12_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_12_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_11_SHIFT                    _MK_SHIFT_CONST(11)
#define APBDMA_STATUS_0_BSY_11_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_11_SHIFT)
#define APBDMA_STATUS_0_BSY_11_RANGE                    11:11
#define APBDMA_STATUS_0_BSY_11_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_11_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_11_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_11_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_10_SHIFT                    _MK_SHIFT_CONST(10)
#define APBDMA_STATUS_0_BSY_10_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_10_SHIFT)
#define APBDMA_STATUS_0_BSY_10_RANGE                    10:10
#define APBDMA_STATUS_0_BSY_10_WOFFSET                  0x0
#define APBDMA_STATUS_0_BSY_10_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_10_NOT_BUSY                 _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_10_BUSY                     _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_9_SHIFT                     _MK_SHIFT_CONST(9)
#define APBDMA_STATUS_0_BSY_9_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_9_SHIFT)
#define APBDMA_STATUS_0_BSY_9_RANGE                     9:9
#define APBDMA_STATUS_0_BSY_9_WOFFSET                   0x0
#define APBDMA_STATUS_0_BSY_9_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_9_NOT_BUSY                  _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_9_BUSY                      _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_8_SHIFT                     _MK_SHIFT_CONST(8)
#define APBDMA_STATUS_0_BSY_8_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_8_SHIFT)
#define APBDMA_STATUS_0_BSY_8_RANGE                     8:8
#define APBDMA_STATUS_0_BSY_8_WOFFSET                   0x0
#define APBDMA_STATUS_0_BSY_8_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_8_NOT_BUSY                  _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_8_BUSY                      _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_7_SHIFT                     _MK_SHIFT_CONST(7)
#define APBDMA_STATUS_0_BSY_7_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_7_SHIFT)
#define APBDMA_STATUS_0_BSY_7_RANGE                     7:7
#define APBDMA_STATUS_0_BSY_7_WOFFSET                   0x0
#define APBDMA_STATUS_0_BSY_7_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_7_NOT_BUSY                  _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_7_BUSY                      _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_6_SHIFT                     _MK_SHIFT_CONST(6)
#define APBDMA_STATUS_0_BSY_6_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_6_SHIFT)
#define APBDMA_STATUS_0_BSY_6_RANGE                     6:6
#define APBDMA_STATUS_0_BSY_6_WOFFSET                   0x0
#define APBDMA_STATUS_0_BSY_6_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_6_NOT_BUSY                  _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_6_BUSY                      _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_5_SHIFT                     _MK_SHIFT_CONST(5)
#define APBDMA_STATUS_0_BSY_5_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_5_SHIFT)
#define APBDMA_STATUS_0_BSY_5_RANGE                     5:5
#define APBDMA_STATUS_0_BSY_5_WOFFSET                   0x0
#define APBDMA_STATUS_0_BSY_5_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_5_NOT_BUSY                  _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_5_BUSY                      _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_4_SHIFT                     _MK_SHIFT_CONST(4)
#define APBDMA_STATUS_0_BSY_4_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_4_SHIFT)
#define APBDMA_STATUS_0_BSY_4_RANGE                     4:4
#define APBDMA_STATUS_0_BSY_4_WOFFSET                   0x0
#define APBDMA_STATUS_0_BSY_4_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_4_NOT_BUSY                  _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_4_BUSY                      _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_3_SHIFT                     _MK_SHIFT_CONST(3)
#define APBDMA_STATUS_0_BSY_3_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_3_SHIFT)
#define APBDMA_STATUS_0_BSY_3_RANGE                     3:3
#define APBDMA_STATUS_0_BSY_3_WOFFSET                   0x0
#define APBDMA_STATUS_0_BSY_3_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_3_NOT_BUSY                  _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_3_BUSY                      _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_2_SHIFT                     _MK_SHIFT_CONST(2)
#define APBDMA_STATUS_0_BSY_2_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_2_SHIFT)
#define APBDMA_STATUS_0_BSY_2_RANGE                     2:2
#define APBDMA_STATUS_0_BSY_2_WOFFSET                   0x0
#define APBDMA_STATUS_0_BSY_2_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_2_NOT_BUSY                  _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_2_BUSY                      _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_1_SHIFT                     _MK_SHIFT_CONST(1)
#define APBDMA_STATUS_0_BSY_1_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_1_SHIFT)
#define APBDMA_STATUS_0_BSY_1_RANGE                     1:1
#define APBDMA_STATUS_0_BSY_1_WOFFSET                   0x0
#define APBDMA_STATUS_0_BSY_1_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_1_NOT_BUSY                  _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_1_BUSY                      _MK_ENUM_CONST(1)

#define APBDMA_STATUS_0_BSY_0_SHIFT                     _MK_SHIFT_CONST(0)
#define APBDMA_STATUS_0_BSY_0_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_STATUS_0_BSY_0_SHIFT)
#define APBDMA_STATUS_0_BSY_0_RANGE                     0:0
#define APBDMA_STATUS_0_BSY_0_WOFFSET                   0x0
#define APBDMA_STATUS_0_BSY_0_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_STATUS_0_BSY_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_STATUS_0_BSY_0_NOT_BUSY                  _MK_ENUM_CONST(0)
#define APBDMA_STATUS_0_BSY_0_BUSY                      _MK_ENUM_CONST(1)


// Register APBDMA_REQUESTORS_TX_0
#define APBDMA_REQUESTORS_TX_0                  _MK_ADDR_CONST(0x8)
#define APBDMA_REQUESTORS_TX_0_SECURE                   0x0
#define APBDMA_REQUESTORS_TX_0_SCR                      0
#define APBDMA_REQUESTORS_TX_0_WORD_COUNT                       0x1
#define APBDMA_REQUESTORS_TX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_RESET_MASK                       _MK_MASK_CONST(0x5fff8721)
#define APBDMA_REQUESTORS_TX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_READ_MASK                        _MK_MASK_CONST(0x5fff8721)
#define APBDMA_REQUESTORS_TX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_6_SHIFT                      _MK_SHIFT_CONST(30)
#define APBDMA_REQUESTORS_TX_0_I2C_6_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_I2C_6_SHIFT)
#define APBDMA_REQUESTORS_TX_0_I2C_6_RANGE                      30:30
#define APBDMA_REQUESTORS_TX_0_I2C_6_WOFFSET                    0x0
#define APBDMA_REQUESTORS_TX_0_I2C_6_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_I2C_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_6_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_I2C_6_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_SL2B6_SHIFT                      _MK_SHIFT_CONST(28)
#define APBDMA_REQUESTORS_TX_0_SL2B6_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_SL2B6_SHIFT)
#define APBDMA_REQUESTORS_TX_0_SL2B6_RANGE                      28:28
#define APBDMA_REQUESTORS_TX_0_SL2B6_WOFFSET                    0x0
#define APBDMA_REQUESTORS_TX_0_SL2B6_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_SL2B6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B6_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_SL2B6_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_SL2B5_SHIFT                      _MK_SHIFT_CONST(27)
#define APBDMA_REQUESTORS_TX_0_SL2B5_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_SL2B5_SHIFT)
#define APBDMA_REQUESTORS_TX_0_SL2B5_RANGE                      27:27
#define APBDMA_REQUESTORS_TX_0_SL2B5_WOFFSET                    0x0
#define APBDMA_REQUESTORS_TX_0_SL2B5_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_SL2B5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B5_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_SL2B5_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_I2C_4_SHIFT                      _MK_SHIFT_CONST(26)
#define APBDMA_REQUESTORS_TX_0_I2C_4_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_I2C_4_SHIFT)
#define APBDMA_REQUESTORS_TX_0_I2C_4_RANGE                      26:26
#define APBDMA_REQUESTORS_TX_0_I2C_4_WOFFSET                    0x0
#define APBDMA_REQUESTORS_TX_0_I2C_4_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_I2C_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_4_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_I2C_4_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_OWR_SHIFT                        _MK_SHIFT_CONST(25)
#define APBDMA_REQUESTORS_TX_0_OWR_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_OWR_SHIFT)
#define APBDMA_REQUESTORS_TX_0_OWR_RANGE                        25:25
#define APBDMA_REQUESTORS_TX_0_OWR_WOFFSET                      0x0
#define APBDMA_REQUESTORS_TX_0_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_OWR_NOT_ACTIVE                   _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_OWR_ACTIVE                       _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_DVC_I2C_SHIFT                    _MK_SHIFT_CONST(24)
#define APBDMA_REQUESTORS_TX_0_DVC_I2C_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_DVC_I2C_SHIFT)
#define APBDMA_REQUESTORS_TX_0_DVC_I2C_RANGE                    24:24
#define APBDMA_REQUESTORS_TX_0_DVC_I2C_WOFFSET                  0x0
#define APBDMA_REQUESTORS_TX_0_DVC_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_DVC_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_DVC_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_DVC_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_DVC_I2C_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_DVC_I2C_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_I2C_3_SHIFT                      _MK_SHIFT_CONST(23)
#define APBDMA_REQUESTORS_TX_0_I2C_3_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_I2C_3_SHIFT)
#define APBDMA_REQUESTORS_TX_0_I2C_3_RANGE                      23:23
#define APBDMA_REQUESTORS_TX_0_I2C_3_WOFFSET                    0x0
#define APBDMA_REQUESTORS_TX_0_I2C_3_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_I2C_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_I2C_3_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_I2C_2_SHIFT                      _MK_SHIFT_CONST(22)
#define APBDMA_REQUESTORS_TX_0_I2C_2_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_I2C_2_SHIFT)
#define APBDMA_REQUESTORS_TX_0_I2C_2_RANGE                      22:22
#define APBDMA_REQUESTORS_TX_0_I2C_2_WOFFSET                    0x0
#define APBDMA_REQUESTORS_TX_0_I2C_2_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_I2C_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_I2C_2_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_I2C_1_SHIFT                      _MK_SHIFT_CONST(21)
#define APBDMA_REQUESTORS_TX_0_I2C_1_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_I2C_1_SHIFT)
#define APBDMA_REQUESTORS_TX_0_I2C_1_RANGE                      21:21
#define APBDMA_REQUESTORS_TX_0_I2C_1_WOFFSET                    0x0
#define APBDMA_REQUESTORS_TX_0_I2C_1_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_I2C_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_I2C_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_I2C_1_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_UART_E_SHIFT                     _MK_SHIFT_CONST(20)
#define APBDMA_REQUESTORS_TX_0_UART_E_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_UART_E_SHIFT)
#define APBDMA_REQUESTORS_TX_0_UART_E_RANGE                     20:20
#define APBDMA_REQUESTORS_TX_0_UART_E_WOFFSET                   0x0
#define APBDMA_REQUESTORS_TX_0_UART_E_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_E_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_UART_E_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_E_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_E_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_UART_E_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_UART_D_SHIFT                     _MK_SHIFT_CONST(19)
#define APBDMA_REQUESTORS_TX_0_UART_D_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_UART_D_SHIFT)
#define APBDMA_REQUESTORS_TX_0_UART_D_RANGE                     19:19
#define APBDMA_REQUESTORS_TX_0_UART_D_WOFFSET                   0x0
#define APBDMA_REQUESTORS_TX_0_UART_D_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_UART_D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_D_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_UART_D_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_SL2B4_SHIFT                      _MK_SHIFT_CONST(18)
#define APBDMA_REQUESTORS_TX_0_SL2B4_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_SL2B4_SHIFT)
#define APBDMA_REQUESTORS_TX_0_SL2B4_RANGE                      18:18
#define APBDMA_REQUESTORS_TX_0_SL2B4_WOFFSET                    0x0
#define APBDMA_REQUESTORS_TX_0_SL2B4_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_SL2B4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B4_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_SL2B4_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_SL2B3_SHIFT                      _MK_SHIFT_CONST(17)
#define APBDMA_REQUESTORS_TX_0_SL2B3_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_SL2B3_SHIFT)
#define APBDMA_REQUESTORS_TX_0_SL2B3_RANGE                      17:17
#define APBDMA_REQUESTORS_TX_0_SL2B3_WOFFSET                    0x0
#define APBDMA_REQUESTORS_TX_0_SL2B3_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_SL2B3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_SL2B3_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_SL2B2_SHIFT                      _MK_SHIFT_CONST(16)
#define APBDMA_REQUESTORS_TX_0_SL2B2_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_SL2B2_SHIFT)
#define APBDMA_REQUESTORS_TX_0_SL2B2_RANGE                      16:16
#define APBDMA_REQUESTORS_TX_0_SL2B2_WOFFSET                    0x0
#define APBDMA_REQUESTORS_TX_0_SL2B2_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_SL2B2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_SL2B2_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_SL2B1_SHIFT                      _MK_SHIFT_CONST(15)
#define APBDMA_REQUESTORS_TX_0_SL2B1_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_SL2B1_SHIFT)
#define APBDMA_REQUESTORS_TX_0_SL2B1_RANGE                      15:15
#define APBDMA_REQUESTORS_TX_0_SL2B1_WOFFSET                    0x0
#define APBDMA_REQUESTORS_TX_0_SL2B1_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_SL2B1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_SL2B1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_SL2B1_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_UART_C_SHIFT                     _MK_SHIFT_CONST(10)
#define APBDMA_REQUESTORS_TX_0_UART_C_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_UART_C_SHIFT)
#define APBDMA_REQUESTORS_TX_0_UART_C_RANGE                     10:10
#define APBDMA_REQUESTORS_TX_0_UART_C_WOFFSET                   0x0
#define APBDMA_REQUESTORS_TX_0_UART_C_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_C_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_UART_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_C_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_UART_C_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_UART_B_SHIFT                     _MK_SHIFT_CONST(9)
#define APBDMA_REQUESTORS_TX_0_UART_B_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_UART_B_SHIFT)
#define APBDMA_REQUESTORS_TX_0_UART_B_RANGE                     9:9
#define APBDMA_REQUESTORS_TX_0_UART_B_WOFFSET                   0x0
#define APBDMA_REQUESTORS_TX_0_UART_B_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_UART_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_B_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_UART_B_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_UART_A_SHIFT                     _MK_SHIFT_CONST(8)
#define APBDMA_REQUESTORS_TX_0_UART_A_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_UART_A_SHIFT)
#define APBDMA_REQUESTORS_TX_0_UART_A_RANGE                     8:8
#define APBDMA_REQUESTORS_TX_0_UART_A_WOFFSET                   0x0
#define APBDMA_REQUESTORS_TX_0_UART_A_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_UART_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_UART_A_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_UART_A_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_QSPI_SHIFT                       _MK_SHIFT_CONST(5)
#define APBDMA_REQUESTORS_TX_0_QSPI_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_QSPI_SHIFT)
#define APBDMA_REQUESTORS_TX_0_QSPI_RANGE                       5:5
#define APBDMA_REQUESTORS_TX_0_QSPI_WOFFSET                     0x0
#define APBDMA_REQUESTORS_TX_0_QSPI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_QSPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_QSPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_QSPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_QSPI_NOT_ACTIVE                  _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_QSPI_ACTIVE                      _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SHIFT                   _MK_SHIFT_CONST(0)
#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_TX_0_CNTR_REQ_SHIFT)
#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_RANGE                   0:0
#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_WOFFSET                 0x0
#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_ACTIVE                  _MK_ENUM_CONST(1)


// Register APBDMA_REQUESTORS_RX_0
#define APBDMA_REQUESTORS_RX_0                  _MK_ADDR_CONST(0xc)
#define APBDMA_REQUESTORS_RX_0_SECURE                   0x0
#define APBDMA_REQUESTORS_RX_0_SCR                      0
#define APBDMA_REQUESTORS_RX_0_WORD_COUNT                       0x1
#define APBDMA_REQUESTORS_RX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_RESET_MASK                       _MK_MASK_CONST(0x5fff8f21)
#define APBDMA_REQUESTORS_RX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_READ_MASK                        _MK_MASK_CONST(0x5fff8f21)
#define APBDMA_REQUESTORS_RX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_6_SHIFT                      _MK_SHIFT_CONST(30)
#define APBDMA_REQUESTORS_RX_0_I2C_6_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_I2C_6_SHIFT)
#define APBDMA_REQUESTORS_RX_0_I2C_6_RANGE                      30:30
#define APBDMA_REQUESTORS_RX_0_I2C_6_WOFFSET                    0x0
#define APBDMA_REQUESTORS_RX_0_I2C_6_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_I2C_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_6_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_I2C_6_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_SL2B6_SHIFT                      _MK_SHIFT_CONST(28)
#define APBDMA_REQUESTORS_RX_0_SL2B6_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_SL2B6_SHIFT)
#define APBDMA_REQUESTORS_RX_0_SL2B6_RANGE                      28:28
#define APBDMA_REQUESTORS_RX_0_SL2B6_WOFFSET                    0x0
#define APBDMA_REQUESTORS_RX_0_SL2B6_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_SL2B6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B6_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_SL2B6_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_SL2B5_SHIFT                      _MK_SHIFT_CONST(27)
#define APBDMA_REQUESTORS_RX_0_SL2B5_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_SL2B5_SHIFT)
#define APBDMA_REQUESTORS_RX_0_SL2B5_RANGE                      27:27
#define APBDMA_REQUESTORS_RX_0_SL2B5_WOFFSET                    0x0
#define APBDMA_REQUESTORS_RX_0_SL2B5_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_SL2B5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B5_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_SL2B5_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_I2C_4_SHIFT                      _MK_SHIFT_CONST(26)
#define APBDMA_REQUESTORS_RX_0_I2C_4_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_I2C_4_SHIFT)
#define APBDMA_REQUESTORS_RX_0_I2C_4_RANGE                      26:26
#define APBDMA_REQUESTORS_RX_0_I2C_4_WOFFSET                    0x0
#define APBDMA_REQUESTORS_RX_0_I2C_4_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_I2C_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_4_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_I2C_4_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_OWR_SHIFT                        _MK_SHIFT_CONST(25)
#define APBDMA_REQUESTORS_RX_0_OWR_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_OWR_SHIFT)
#define APBDMA_REQUESTORS_RX_0_OWR_RANGE                        25:25
#define APBDMA_REQUESTORS_RX_0_OWR_WOFFSET                      0x0
#define APBDMA_REQUESTORS_RX_0_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_OWR_NOT_ACTIVE                   _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_OWR_ACTIVE                       _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_DVC_I2C_SHIFT                    _MK_SHIFT_CONST(24)
#define APBDMA_REQUESTORS_RX_0_DVC_I2C_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_DVC_I2C_SHIFT)
#define APBDMA_REQUESTORS_RX_0_DVC_I2C_RANGE                    24:24
#define APBDMA_REQUESTORS_RX_0_DVC_I2C_WOFFSET                  0x0
#define APBDMA_REQUESTORS_RX_0_DVC_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_DVC_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_DVC_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_DVC_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_DVC_I2C_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_DVC_I2C_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_I2C_3_SHIFT                      _MK_SHIFT_CONST(23)
#define APBDMA_REQUESTORS_RX_0_I2C_3_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_I2C_3_SHIFT)
#define APBDMA_REQUESTORS_RX_0_I2C_3_RANGE                      23:23
#define APBDMA_REQUESTORS_RX_0_I2C_3_WOFFSET                    0x0
#define APBDMA_REQUESTORS_RX_0_I2C_3_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_I2C_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_I2C_3_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_I2C_2_SHIFT                      _MK_SHIFT_CONST(22)
#define APBDMA_REQUESTORS_RX_0_I2C_2_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_I2C_2_SHIFT)
#define APBDMA_REQUESTORS_RX_0_I2C_2_RANGE                      22:22
#define APBDMA_REQUESTORS_RX_0_I2C_2_WOFFSET                    0x0
#define APBDMA_REQUESTORS_RX_0_I2C_2_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_I2C_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_I2C_2_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_I2C_1_SHIFT                      _MK_SHIFT_CONST(21)
#define APBDMA_REQUESTORS_RX_0_I2C_1_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_I2C_1_SHIFT)
#define APBDMA_REQUESTORS_RX_0_I2C_1_RANGE                      21:21
#define APBDMA_REQUESTORS_RX_0_I2C_1_WOFFSET                    0x0
#define APBDMA_REQUESTORS_RX_0_I2C_1_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_I2C_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_I2C_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_I2C_1_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_UART_E_SHIFT                     _MK_SHIFT_CONST(20)
#define APBDMA_REQUESTORS_RX_0_UART_E_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_UART_E_SHIFT)
#define APBDMA_REQUESTORS_RX_0_UART_E_RANGE                     20:20
#define APBDMA_REQUESTORS_RX_0_UART_E_WOFFSET                   0x0
#define APBDMA_REQUESTORS_RX_0_UART_E_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_E_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_UART_E_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_E_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_E_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_UART_E_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_UART_D_SHIFT                     _MK_SHIFT_CONST(19)
#define APBDMA_REQUESTORS_RX_0_UART_D_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_UART_D_SHIFT)
#define APBDMA_REQUESTORS_RX_0_UART_D_RANGE                     19:19
#define APBDMA_REQUESTORS_RX_0_UART_D_WOFFSET                   0x0
#define APBDMA_REQUESTORS_RX_0_UART_D_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_UART_D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_D_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_UART_D_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_SL2B4_SHIFT                      _MK_SHIFT_CONST(18)
#define APBDMA_REQUESTORS_RX_0_SL2B4_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_SL2B4_SHIFT)
#define APBDMA_REQUESTORS_RX_0_SL2B4_RANGE                      18:18
#define APBDMA_REQUESTORS_RX_0_SL2B4_WOFFSET                    0x0
#define APBDMA_REQUESTORS_RX_0_SL2B4_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_SL2B4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B4_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_SL2B4_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_SL2B3_SHIFT                      _MK_SHIFT_CONST(17)
#define APBDMA_REQUESTORS_RX_0_SL2B3_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_SL2B3_SHIFT)
#define APBDMA_REQUESTORS_RX_0_SL2B3_RANGE                      17:17
#define APBDMA_REQUESTORS_RX_0_SL2B3_WOFFSET                    0x0
#define APBDMA_REQUESTORS_RX_0_SL2B3_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_SL2B3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_SL2B3_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_SL2B2_SHIFT                      _MK_SHIFT_CONST(16)
#define APBDMA_REQUESTORS_RX_0_SL2B2_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_SL2B2_SHIFT)
#define APBDMA_REQUESTORS_RX_0_SL2B2_RANGE                      16:16
#define APBDMA_REQUESTORS_RX_0_SL2B2_WOFFSET                    0x0
#define APBDMA_REQUESTORS_RX_0_SL2B2_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_SL2B2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_SL2B2_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_SL2B1_SHIFT                      _MK_SHIFT_CONST(15)
#define APBDMA_REQUESTORS_RX_0_SL2B1_FIELD                      _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_SL2B1_SHIFT)
#define APBDMA_REQUESTORS_RX_0_SL2B1_RANGE                      15:15
#define APBDMA_REQUESTORS_RX_0_SL2B1_WOFFSET                    0x0
#define APBDMA_REQUESTORS_RX_0_SL2B1_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_SL2B1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SL2B1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_SL2B1_ACTIVE                     _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_SPI_SHIFT                        _MK_SHIFT_CONST(11)
#define APBDMA_REQUESTORS_RX_0_SPI_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_SPI_SHIFT)
#define APBDMA_REQUESTORS_RX_0_SPI_RANGE                        11:11
#define APBDMA_REQUESTORS_RX_0_SPI_WOFFSET                      0x0
#define APBDMA_REQUESTORS_RX_0_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_SPI_NOT_ACTIVE                   _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_SPI_ACTIVE                       _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_UART_C_SHIFT                     _MK_SHIFT_CONST(10)
#define APBDMA_REQUESTORS_RX_0_UART_C_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_UART_C_SHIFT)
#define APBDMA_REQUESTORS_RX_0_UART_C_RANGE                     10:10
#define APBDMA_REQUESTORS_RX_0_UART_C_WOFFSET                   0x0
#define APBDMA_REQUESTORS_RX_0_UART_C_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_C_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_UART_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_C_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_UART_C_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_UART_B_SHIFT                     _MK_SHIFT_CONST(9)
#define APBDMA_REQUESTORS_RX_0_UART_B_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_UART_B_SHIFT)
#define APBDMA_REQUESTORS_RX_0_UART_B_RANGE                     9:9
#define APBDMA_REQUESTORS_RX_0_UART_B_WOFFSET                   0x0
#define APBDMA_REQUESTORS_RX_0_UART_B_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_UART_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_B_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_UART_B_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_UART_A_SHIFT                     _MK_SHIFT_CONST(8)
#define APBDMA_REQUESTORS_RX_0_UART_A_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_UART_A_SHIFT)
#define APBDMA_REQUESTORS_RX_0_UART_A_RANGE                     8:8
#define APBDMA_REQUESTORS_RX_0_UART_A_WOFFSET                   0x0
#define APBDMA_REQUESTORS_RX_0_UART_A_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_UART_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_UART_A_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_UART_A_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_QSPI_SHIFT                       _MK_SHIFT_CONST(5)
#define APBDMA_REQUESTORS_RX_0_QSPI_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_QSPI_SHIFT)
#define APBDMA_REQUESTORS_RX_0_QSPI_RANGE                       5:5
#define APBDMA_REQUESTORS_RX_0_QSPI_WOFFSET                     0x0
#define APBDMA_REQUESTORS_RX_0_QSPI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_QSPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_QSPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_QSPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_QSPI_NOT_ACTIVE                  _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_QSPI_ACTIVE                      _MK_ENUM_CONST(1)

#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SHIFT                   _MK_SHIFT_CONST(0)
#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_REQUESTORS_RX_0_CNTR_REQ_SHIFT)
#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_RANGE                   0:0
#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_WOFFSET                 0x0
#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_ACTIVE                  _MK_ENUM_CONST(1)


// Register APBDMA_CNTRL_REG_0
#define APBDMA_CNTRL_REG_0                      _MK_ADDR_CONST(0x10)
#define APBDMA_CNTRL_REG_0_SECURE                       0x0
#define APBDMA_CNTRL_REG_0_SCR                  0
#define APBDMA_CNTRL_REG_0_WORD_COUNT                   0x1
#define APBDMA_CNTRL_REG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APBDMA_CNTRL_REG_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
#define APBDMA_CNTRL_REG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APBDMA_CNTRL_REG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_CNTRL_REG_0_READ_MASK                    _MK_MASK_CONST(0xffff)
#define APBDMA_CNTRL_REG_0_WRITE_MASK                   _MK_MASK_CONST(0xffff)
#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define APBDMA_CNTRL_REG_0_COUNT_VALUE_FIELD                    _MK_FIELD_CONST(0xffff, APBDMA_CNTRL_REG_0_COUNT_VALUE_SHIFT)
#define APBDMA_CNTRL_REG_0_COUNT_VALUE_RANGE                    15:0
#define APBDMA_CNTRL_REG_0_COUNT_VALUE_WOFFSET                  0x0
#define APBDMA_CNTRL_REG_0_COUNT_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CNTRL_REG_0_COUNT_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register APBDMA_IRQ_STA_CPU_0
#define APBDMA_IRQ_STA_CPU_0                    _MK_ADDR_CONST(0x14)
#define APBDMA_IRQ_STA_CPU_0_SECURE                     0x0
#define APBDMA_IRQ_STA_CPU_0_SCR                        0
#define APBDMA_IRQ_STA_CPU_0_WORD_COUNT                         0x1
#define APBDMA_IRQ_STA_CPU_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define APBDMA_IRQ_STA_CPU_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define APBDMA_IRQ_STA_CPU_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH31_SHIFT                 _MK_SHIFT_CONST(31)
#define APBDMA_IRQ_STA_CPU_0_CH31_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH31_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH31_RANGE                 31:31
#define APBDMA_IRQ_STA_CPU_0_CH31_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH31_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH31_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH31_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH31_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH31_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH31_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH30_SHIFT                 _MK_SHIFT_CONST(30)
#define APBDMA_IRQ_STA_CPU_0_CH30_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH30_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH30_RANGE                 30:30
#define APBDMA_IRQ_STA_CPU_0_CH30_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH30_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH30_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH30_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH30_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH30_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH30_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH29_SHIFT                 _MK_SHIFT_CONST(29)
#define APBDMA_IRQ_STA_CPU_0_CH29_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH29_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH29_RANGE                 29:29
#define APBDMA_IRQ_STA_CPU_0_CH29_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH29_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH29_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH29_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH29_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH29_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH29_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH28_SHIFT                 _MK_SHIFT_CONST(28)
#define APBDMA_IRQ_STA_CPU_0_CH28_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH28_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH28_RANGE                 28:28
#define APBDMA_IRQ_STA_CPU_0_CH28_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH28_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH28_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH28_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH28_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH28_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH28_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH27_SHIFT                 _MK_SHIFT_CONST(27)
#define APBDMA_IRQ_STA_CPU_0_CH27_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH27_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH27_RANGE                 27:27
#define APBDMA_IRQ_STA_CPU_0_CH27_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH27_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH27_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH27_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH27_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH27_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH27_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH26_SHIFT                 _MK_SHIFT_CONST(26)
#define APBDMA_IRQ_STA_CPU_0_CH26_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH26_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH26_RANGE                 26:26
#define APBDMA_IRQ_STA_CPU_0_CH26_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH26_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH26_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH26_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH26_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH26_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH26_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH25_SHIFT                 _MK_SHIFT_CONST(25)
#define APBDMA_IRQ_STA_CPU_0_CH25_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH25_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH25_RANGE                 25:25
#define APBDMA_IRQ_STA_CPU_0_CH25_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH25_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH25_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH25_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH25_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH25_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH25_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH24_SHIFT                 _MK_SHIFT_CONST(24)
#define APBDMA_IRQ_STA_CPU_0_CH24_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH24_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH24_RANGE                 24:24
#define APBDMA_IRQ_STA_CPU_0_CH24_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH24_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH24_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH24_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH24_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH24_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH24_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH23_SHIFT                 _MK_SHIFT_CONST(23)
#define APBDMA_IRQ_STA_CPU_0_CH23_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH23_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH23_RANGE                 23:23
#define APBDMA_IRQ_STA_CPU_0_CH23_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH23_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH23_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH23_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH23_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH23_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH23_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH22_SHIFT                 _MK_SHIFT_CONST(22)
#define APBDMA_IRQ_STA_CPU_0_CH22_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH22_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH22_RANGE                 22:22
#define APBDMA_IRQ_STA_CPU_0_CH22_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH22_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH22_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH22_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH22_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH22_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH22_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH21_SHIFT                 _MK_SHIFT_CONST(21)
#define APBDMA_IRQ_STA_CPU_0_CH21_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH21_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH21_RANGE                 21:21
#define APBDMA_IRQ_STA_CPU_0_CH21_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH21_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH21_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH21_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH21_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH21_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH21_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH20_SHIFT                 _MK_SHIFT_CONST(20)
#define APBDMA_IRQ_STA_CPU_0_CH20_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH20_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH20_RANGE                 20:20
#define APBDMA_IRQ_STA_CPU_0_CH20_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH20_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH20_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH20_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH20_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH20_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH20_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH19_SHIFT                 _MK_SHIFT_CONST(19)
#define APBDMA_IRQ_STA_CPU_0_CH19_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH19_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH19_RANGE                 19:19
#define APBDMA_IRQ_STA_CPU_0_CH19_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH19_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH19_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH19_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH19_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH19_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH19_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH18_SHIFT                 _MK_SHIFT_CONST(18)
#define APBDMA_IRQ_STA_CPU_0_CH18_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH18_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH18_RANGE                 18:18
#define APBDMA_IRQ_STA_CPU_0_CH18_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH18_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH18_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH18_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH18_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH18_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH18_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH17_SHIFT                 _MK_SHIFT_CONST(17)
#define APBDMA_IRQ_STA_CPU_0_CH17_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH17_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH17_RANGE                 17:17
#define APBDMA_IRQ_STA_CPU_0_CH17_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH17_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH17_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH17_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH17_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH17_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH17_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH16_SHIFT                 _MK_SHIFT_CONST(16)
#define APBDMA_IRQ_STA_CPU_0_CH16_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH16_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH16_RANGE                 16:16
#define APBDMA_IRQ_STA_CPU_0_CH16_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH16_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH16_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH16_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH16_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH16_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH16_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH15_SHIFT                 _MK_SHIFT_CONST(15)
#define APBDMA_IRQ_STA_CPU_0_CH15_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH15_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH15_RANGE                 15:15
#define APBDMA_IRQ_STA_CPU_0_CH15_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH15_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH15_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH15_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH14_SHIFT                 _MK_SHIFT_CONST(14)
#define APBDMA_IRQ_STA_CPU_0_CH14_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH14_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH14_RANGE                 14:14
#define APBDMA_IRQ_STA_CPU_0_CH14_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH14_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH14_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH14_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH13_SHIFT                 _MK_SHIFT_CONST(13)
#define APBDMA_IRQ_STA_CPU_0_CH13_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH13_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH13_RANGE                 13:13
#define APBDMA_IRQ_STA_CPU_0_CH13_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH13_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH13_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH13_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH12_SHIFT                 _MK_SHIFT_CONST(12)
#define APBDMA_IRQ_STA_CPU_0_CH12_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH12_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH12_RANGE                 12:12
#define APBDMA_IRQ_STA_CPU_0_CH12_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH12_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH12_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH12_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH11_SHIFT                 _MK_SHIFT_CONST(11)
#define APBDMA_IRQ_STA_CPU_0_CH11_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH11_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH11_RANGE                 11:11
#define APBDMA_IRQ_STA_CPU_0_CH11_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH11_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH11_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH11_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH10_SHIFT                 _MK_SHIFT_CONST(10)
#define APBDMA_IRQ_STA_CPU_0_CH10_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH10_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH10_RANGE                 10:10
#define APBDMA_IRQ_STA_CPU_0_CH10_WOFFSET                       0x0
#define APBDMA_IRQ_STA_CPU_0_CH10_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH10_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH10_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH9_SHIFT                  _MK_SHIFT_CONST(9)
#define APBDMA_IRQ_STA_CPU_0_CH9_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH9_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH9_RANGE                  9:9
#define APBDMA_IRQ_STA_CPU_0_CH9_WOFFSET                        0x0
#define APBDMA_IRQ_STA_CPU_0_CH9_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH9_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH9_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH8_SHIFT                  _MK_SHIFT_CONST(8)
#define APBDMA_IRQ_STA_CPU_0_CH8_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH8_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH8_RANGE                  8:8
#define APBDMA_IRQ_STA_CPU_0_CH8_WOFFSET                        0x0
#define APBDMA_IRQ_STA_CPU_0_CH8_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH8_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH8_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH7_SHIFT                  _MK_SHIFT_CONST(7)
#define APBDMA_IRQ_STA_CPU_0_CH7_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH7_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH7_RANGE                  7:7
#define APBDMA_IRQ_STA_CPU_0_CH7_WOFFSET                        0x0
#define APBDMA_IRQ_STA_CPU_0_CH7_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH7_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH7_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH6_SHIFT                  _MK_SHIFT_CONST(6)
#define APBDMA_IRQ_STA_CPU_0_CH6_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH6_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH6_RANGE                  6:6
#define APBDMA_IRQ_STA_CPU_0_CH6_WOFFSET                        0x0
#define APBDMA_IRQ_STA_CPU_0_CH6_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH6_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH6_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH5_SHIFT                  _MK_SHIFT_CONST(5)
#define APBDMA_IRQ_STA_CPU_0_CH5_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH5_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH5_RANGE                  5:5
#define APBDMA_IRQ_STA_CPU_0_CH5_WOFFSET                        0x0
#define APBDMA_IRQ_STA_CPU_0_CH5_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH5_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH5_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH4_SHIFT                  _MK_SHIFT_CONST(4)
#define APBDMA_IRQ_STA_CPU_0_CH4_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH4_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH4_RANGE                  4:4
#define APBDMA_IRQ_STA_CPU_0_CH4_WOFFSET                        0x0
#define APBDMA_IRQ_STA_CPU_0_CH4_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH4_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH4_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH3_SHIFT                  _MK_SHIFT_CONST(3)
#define APBDMA_IRQ_STA_CPU_0_CH3_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH3_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH3_RANGE                  3:3
#define APBDMA_IRQ_STA_CPU_0_CH3_WOFFSET                        0x0
#define APBDMA_IRQ_STA_CPU_0_CH3_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH3_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH3_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH2_SHIFT                  _MK_SHIFT_CONST(2)
#define APBDMA_IRQ_STA_CPU_0_CH2_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH2_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH2_RANGE                  2:2
#define APBDMA_IRQ_STA_CPU_0_CH2_WOFFSET                        0x0
#define APBDMA_IRQ_STA_CPU_0_CH2_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH2_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH2_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH1_SHIFT                  _MK_SHIFT_CONST(1)
#define APBDMA_IRQ_STA_CPU_0_CH1_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH1_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH1_RANGE                  1:1
#define APBDMA_IRQ_STA_CPU_0_CH1_WOFFSET                        0x0
#define APBDMA_IRQ_STA_CPU_0_CH1_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH1_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH1_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_CPU_0_CH0_SHIFT                  _MK_SHIFT_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH0_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_CPU_0_CH0_SHIFT)
#define APBDMA_IRQ_STA_CPU_0_CH0_RANGE                  0:0
#define APBDMA_IRQ_STA_CPU_0_CH0_WOFFSET                        0x0
#define APBDMA_IRQ_STA_CPU_0_CH0_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_CPU_0_CH0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_CPU_0_CH0_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_CPU_0_CH0_ENABLE                 _MK_ENUM_CONST(1)


// Register APBDMA_IRQ_STA_COP_0
#define APBDMA_IRQ_STA_COP_0                    _MK_ADDR_CONST(0x18)
#define APBDMA_IRQ_STA_COP_0_SECURE                     0x0
#define APBDMA_IRQ_STA_COP_0_SCR                        0
#define APBDMA_IRQ_STA_COP_0_WORD_COUNT                         0x1
#define APBDMA_IRQ_STA_COP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define APBDMA_IRQ_STA_COP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define APBDMA_IRQ_STA_COP_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH31_SHIFT                 _MK_SHIFT_CONST(31)
#define APBDMA_IRQ_STA_COP_0_CH31_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH31_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH31_RANGE                 31:31
#define APBDMA_IRQ_STA_COP_0_CH31_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH31_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH31_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH31_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH31_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH31_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH31_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH30_SHIFT                 _MK_SHIFT_CONST(30)
#define APBDMA_IRQ_STA_COP_0_CH30_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH30_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH30_RANGE                 30:30
#define APBDMA_IRQ_STA_COP_0_CH30_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH30_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH30_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH30_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH30_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH30_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH30_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH29_SHIFT                 _MK_SHIFT_CONST(29)
#define APBDMA_IRQ_STA_COP_0_CH29_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH29_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH29_RANGE                 29:29
#define APBDMA_IRQ_STA_COP_0_CH29_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH29_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH29_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH29_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH29_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH29_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH29_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH28_SHIFT                 _MK_SHIFT_CONST(28)
#define APBDMA_IRQ_STA_COP_0_CH28_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH28_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH28_RANGE                 28:28
#define APBDMA_IRQ_STA_COP_0_CH28_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH28_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH28_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH28_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH28_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH28_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH28_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH27_SHIFT                 _MK_SHIFT_CONST(27)
#define APBDMA_IRQ_STA_COP_0_CH27_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH27_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH27_RANGE                 27:27
#define APBDMA_IRQ_STA_COP_0_CH27_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH27_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH27_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH27_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH27_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH27_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH27_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH26_SHIFT                 _MK_SHIFT_CONST(26)
#define APBDMA_IRQ_STA_COP_0_CH26_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH26_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH26_RANGE                 26:26
#define APBDMA_IRQ_STA_COP_0_CH26_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH26_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH26_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH26_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH26_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH26_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH26_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH25_SHIFT                 _MK_SHIFT_CONST(25)
#define APBDMA_IRQ_STA_COP_0_CH25_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH25_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH25_RANGE                 25:25
#define APBDMA_IRQ_STA_COP_0_CH25_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH25_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH25_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH25_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH25_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH25_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH25_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH24_SHIFT                 _MK_SHIFT_CONST(24)
#define APBDMA_IRQ_STA_COP_0_CH24_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH24_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH24_RANGE                 24:24
#define APBDMA_IRQ_STA_COP_0_CH24_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH24_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH24_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH24_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH24_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH24_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH24_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH23_SHIFT                 _MK_SHIFT_CONST(23)
#define APBDMA_IRQ_STA_COP_0_CH23_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH23_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH23_RANGE                 23:23
#define APBDMA_IRQ_STA_COP_0_CH23_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH23_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH23_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH23_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH23_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH23_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH23_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH22_SHIFT                 _MK_SHIFT_CONST(22)
#define APBDMA_IRQ_STA_COP_0_CH22_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH22_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH22_RANGE                 22:22
#define APBDMA_IRQ_STA_COP_0_CH22_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH22_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH22_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH22_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH22_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH22_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH22_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH21_SHIFT                 _MK_SHIFT_CONST(21)
#define APBDMA_IRQ_STA_COP_0_CH21_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH21_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH21_RANGE                 21:21
#define APBDMA_IRQ_STA_COP_0_CH21_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH21_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH21_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH21_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH21_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH21_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH21_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH20_SHIFT                 _MK_SHIFT_CONST(20)
#define APBDMA_IRQ_STA_COP_0_CH20_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH20_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH20_RANGE                 20:20
#define APBDMA_IRQ_STA_COP_0_CH20_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH20_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH20_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH20_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH20_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH20_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH20_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH19_SHIFT                 _MK_SHIFT_CONST(19)
#define APBDMA_IRQ_STA_COP_0_CH19_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH19_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH19_RANGE                 19:19
#define APBDMA_IRQ_STA_COP_0_CH19_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH19_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH19_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH19_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH19_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH19_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH19_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH18_SHIFT                 _MK_SHIFT_CONST(18)
#define APBDMA_IRQ_STA_COP_0_CH18_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH18_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH18_RANGE                 18:18
#define APBDMA_IRQ_STA_COP_0_CH18_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH18_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH18_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH18_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH18_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH18_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH18_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH17_SHIFT                 _MK_SHIFT_CONST(17)
#define APBDMA_IRQ_STA_COP_0_CH17_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH17_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH17_RANGE                 17:17
#define APBDMA_IRQ_STA_COP_0_CH17_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH17_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH17_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH17_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH17_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH17_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH17_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH16_SHIFT                 _MK_SHIFT_CONST(16)
#define APBDMA_IRQ_STA_COP_0_CH16_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH16_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH16_RANGE                 16:16
#define APBDMA_IRQ_STA_COP_0_CH16_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH16_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH16_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH16_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH16_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH16_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH16_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH15_SHIFT                 _MK_SHIFT_CONST(15)
#define APBDMA_IRQ_STA_COP_0_CH15_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH15_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH15_RANGE                 15:15
#define APBDMA_IRQ_STA_COP_0_CH15_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH15_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH15_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH15_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH14_SHIFT                 _MK_SHIFT_CONST(14)
#define APBDMA_IRQ_STA_COP_0_CH14_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH14_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH14_RANGE                 14:14
#define APBDMA_IRQ_STA_COP_0_CH14_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH14_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH14_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH14_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH13_SHIFT                 _MK_SHIFT_CONST(13)
#define APBDMA_IRQ_STA_COP_0_CH13_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH13_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH13_RANGE                 13:13
#define APBDMA_IRQ_STA_COP_0_CH13_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH13_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH13_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH13_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH12_SHIFT                 _MK_SHIFT_CONST(12)
#define APBDMA_IRQ_STA_COP_0_CH12_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH12_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH12_RANGE                 12:12
#define APBDMA_IRQ_STA_COP_0_CH12_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH12_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH12_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH12_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH11_SHIFT                 _MK_SHIFT_CONST(11)
#define APBDMA_IRQ_STA_COP_0_CH11_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH11_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH11_RANGE                 11:11
#define APBDMA_IRQ_STA_COP_0_CH11_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH11_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH11_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH11_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH10_SHIFT                 _MK_SHIFT_CONST(10)
#define APBDMA_IRQ_STA_COP_0_CH10_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH10_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH10_RANGE                 10:10
#define APBDMA_IRQ_STA_COP_0_CH10_WOFFSET                       0x0
#define APBDMA_IRQ_STA_COP_0_CH10_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH10_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH10_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH9_SHIFT                  _MK_SHIFT_CONST(9)
#define APBDMA_IRQ_STA_COP_0_CH9_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH9_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH9_RANGE                  9:9
#define APBDMA_IRQ_STA_COP_0_CH9_WOFFSET                        0x0
#define APBDMA_IRQ_STA_COP_0_CH9_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH9_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH9_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH8_SHIFT                  _MK_SHIFT_CONST(8)
#define APBDMA_IRQ_STA_COP_0_CH8_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH8_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH8_RANGE                  8:8
#define APBDMA_IRQ_STA_COP_0_CH8_WOFFSET                        0x0
#define APBDMA_IRQ_STA_COP_0_CH8_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH8_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH8_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH7_SHIFT                  _MK_SHIFT_CONST(7)
#define APBDMA_IRQ_STA_COP_0_CH7_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH7_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH7_RANGE                  7:7
#define APBDMA_IRQ_STA_COP_0_CH7_WOFFSET                        0x0
#define APBDMA_IRQ_STA_COP_0_CH7_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH7_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH7_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH6_SHIFT                  _MK_SHIFT_CONST(6)
#define APBDMA_IRQ_STA_COP_0_CH6_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH6_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH6_RANGE                  6:6
#define APBDMA_IRQ_STA_COP_0_CH6_WOFFSET                        0x0
#define APBDMA_IRQ_STA_COP_0_CH6_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH6_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH6_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH5_SHIFT                  _MK_SHIFT_CONST(5)
#define APBDMA_IRQ_STA_COP_0_CH5_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH5_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH5_RANGE                  5:5
#define APBDMA_IRQ_STA_COP_0_CH5_WOFFSET                        0x0
#define APBDMA_IRQ_STA_COP_0_CH5_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH5_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH5_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH4_SHIFT                  _MK_SHIFT_CONST(4)
#define APBDMA_IRQ_STA_COP_0_CH4_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH4_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH4_RANGE                  4:4
#define APBDMA_IRQ_STA_COP_0_CH4_WOFFSET                        0x0
#define APBDMA_IRQ_STA_COP_0_CH4_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH4_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH4_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH3_SHIFT                  _MK_SHIFT_CONST(3)
#define APBDMA_IRQ_STA_COP_0_CH3_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH3_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH3_RANGE                  3:3
#define APBDMA_IRQ_STA_COP_0_CH3_WOFFSET                        0x0
#define APBDMA_IRQ_STA_COP_0_CH3_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH3_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH3_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH2_SHIFT                  _MK_SHIFT_CONST(2)
#define APBDMA_IRQ_STA_COP_0_CH2_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH2_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH2_RANGE                  2:2
#define APBDMA_IRQ_STA_COP_0_CH2_WOFFSET                        0x0
#define APBDMA_IRQ_STA_COP_0_CH2_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH2_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH2_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH1_SHIFT                  _MK_SHIFT_CONST(1)
#define APBDMA_IRQ_STA_COP_0_CH1_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH1_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH1_RANGE                  1:1
#define APBDMA_IRQ_STA_COP_0_CH1_WOFFSET                        0x0
#define APBDMA_IRQ_STA_COP_0_CH1_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH1_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH1_ENABLE                 _MK_ENUM_CONST(1)

#define APBDMA_IRQ_STA_COP_0_CH0_SHIFT                  _MK_SHIFT_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH0_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_IRQ_STA_COP_0_CH0_SHIFT)
#define APBDMA_IRQ_STA_COP_0_CH0_RANGE                  0:0
#define APBDMA_IRQ_STA_COP_0_CH0_WOFFSET                        0x0
#define APBDMA_IRQ_STA_COP_0_CH0_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_STA_COP_0_CH0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_STA_COP_0_CH0_DISABLE                        _MK_ENUM_CONST(0)
#define APBDMA_IRQ_STA_COP_0_CH0_ENABLE                 _MK_ENUM_CONST(1)


// Register APBDMA_IRQ_MASK_0
#define APBDMA_IRQ_MASK_0                       _MK_ADDR_CONST(0x1c)
#define APBDMA_IRQ_MASK_0_SECURE                        0x0
#define APBDMA_IRQ_MASK_0_SCR                   0
#define APBDMA_IRQ_MASK_0_WORD_COUNT                    0x1
#define APBDMA_IRQ_MASK_0_RESET_VAL                     _MK_MASK_CONST(0xffffffff)
#define APBDMA_IRQ_MASK_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define APBDMA_IRQ_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define APBDMA_IRQ_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH31_SHIFT                    _MK_SHIFT_CONST(31)
#define APBDMA_IRQ_MASK_0_CH31_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH31_SHIFT)
#define APBDMA_IRQ_MASK_0_CH31_RANGE                    31:31
#define APBDMA_IRQ_MASK_0_CH31_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH31_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH31_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH31_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH31_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH31_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH31_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH30_SHIFT                    _MK_SHIFT_CONST(30)
#define APBDMA_IRQ_MASK_0_CH30_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH30_SHIFT)
#define APBDMA_IRQ_MASK_0_CH30_RANGE                    30:30
#define APBDMA_IRQ_MASK_0_CH30_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH30_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH30_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH30_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH30_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH30_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH30_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH29_SHIFT                    _MK_SHIFT_CONST(29)
#define APBDMA_IRQ_MASK_0_CH29_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH29_SHIFT)
#define APBDMA_IRQ_MASK_0_CH29_RANGE                    29:29
#define APBDMA_IRQ_MASK_0_CH29_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH29_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH29_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH29_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH29_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH29_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH29_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH28_SHIFT                    _MK_SHIFT_CONST(28)
#define APBDMA_IRQ_MASK_0_CH28_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH28_SHIFT)
#define APBDMA_IRQ_MASK_0_CH28_RANGE                    28:28
#define APBDMA_IRQ_MASK_0_CH28_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH28_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH28_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH28_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH28_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH28_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH28_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH27_SHIFT                    _MK_SHIFT_CONST(27)
#define APBDMA_IRQ_MASK_0_CH27_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH27_SHIFT)
#define APBDMA_IRQ_MASK_0_CH27_RANGE                    27:27
#define APBDMA_IRQ_MASK_0_CH27_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH27_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH27_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH27_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH27_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH27_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH27_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH26_SHIFT                    _MK_SHIFT_CONST(26)
#define APBDMA_IRQ_MASK_0_CH26_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH26_SHIFT)
#define APBDMA_IRQ_MASK_0_CH26_RANGE                    26:26
#define APBDMA_IRQ_MASK_0_CH26_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH26_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH26_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH26_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH26_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH26_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH26_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH25_SHIFT                    _MK_SHIFT_CONST(25)
#define APBDMA_IRQ_MASK_0_CH25_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH25_SHIFT)
#define APBDMA_IRQ_MASK_0_CH25_RANGE                    25:25
#define APBDMA_IRQ_MASK_0_CH25_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH25_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH25_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH25_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH25_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH25_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH25_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH24_SHIFT                    _MK_SHIFT_CONST(24)
#define APBDMA_IRQ_MASK_0_CH24_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH24_SHIFT)
#define APBDMA_IRQ_MASK_0_CH24_RANGE                    24:24
#define APBDMA_IRQ_MASK_0_CH24_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH24_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH24_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH24_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH24_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH24_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH24_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH23_SHIFT                    _MK_SHIFT_CONST(23)
#define APBDMA_IRQ_MASK_0_CH23_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH23_SHIFT)
#define APBDMA_IRQ_MASK_0_CH23_RANGE                    23:23
#define APBDMA_IRQ_MASK_0_CH23_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH23_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH23_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH23_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH23_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH23_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH23_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH22_SHIFT                    _MK_SHIFT_CONST(22)
#define APBDMA_IRQ_MASK_0_CH22_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH22_SHIFT)
#define APBDMA_IRQ_MASK_0_CH22_RANGE                    22:22
#define APBDMA_IRQ_MASK_0_CH22_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH22_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH22_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH22_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH22_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH22_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH22_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH21_SHIFT                    _MK_SHIFT_CONST(21)
#define APBDMA_IRQ_MASK_0_CH21_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH21_SHIFT)
#define APBDMA_IRQ_MASK_0_CH21_RANGE                    21:21
#define APBDMA_IRQ_MASK_0_CH21_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH21_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH21_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH21_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH21_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH21_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH21_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH20_SHIFT                    _MK_SHIFT_CONST(20)
#define APBDMA_IRQ_MASK_0_CH20_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH20_SHIFT)
#define APBDMA_IRQ_MASK_0_CH20_RANGE                    20:20
#define APBDMA_IRQ_MASK_0_CH20_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH20_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH20_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH20_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH20_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH20_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH20_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH19_SHIFT                    _MK_SHIFT_CONST(19)
#define APBDMA_IRQ_MASK_0_CH19_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH19_SHIFT)
#define APBDMA_IRQ_MASK_0_CH19_RANGE                    19:19
#define APBDMA_IRQ_MASK_0_CH19_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH19_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH19_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH19_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH19_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH19_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH19_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH18_SHIFT                    _MK_SHIFT_CONST(18)
#define APBDMA_IRQ_MASK_0_CH18_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH18_SHIFT)
#define APBDMA_IRQ_MASK_0_CH18_RANGE                    18:18
#define APBDMA_IRQ_MASK_0_CH18_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH18_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH18_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH18_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH18_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH18_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH18_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH17_SHIFT                    _MK_SHIFT_CONST(17)
#define APBDMA_IRQ_MASK_0_CH17_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH17_SHIFT)
#define APBDMA_IRQ_MASK_0_CH17_RANGE                    17:17
#define APBDMA_IRQ_MASK_0_CH17_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH17_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH17_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH17_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH17_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH17_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH17_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH16_SHIFT                    _MK_SHIFT_CONST(16)
#define APBDMA_IRQ_MASK_0_CH16_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH16_SHIFT)
#define APBDMA_IRQ_MASK_0_CH16_RANGE                    16:16
#define APBDMA_IRQ_MASK_0_CH16_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH16_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH16_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH16_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH16_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH16_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH16_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH15_SHIFT                    _MK_SHIFT_CONST(15)
#define APBDMA_IRQ_MASK_0_CH15_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH15_SHIFT)
#define APBDMA_IRQ_MASK_0_CH15_RANGE                    15:15
#define APBDMA_IRQ_MASK_0_CH15_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH15_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH15_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH15_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH14_SHIFT                    _MK_SHIFT_CONST(14)
#define APBDMA_IRQ_MASK_0_CH14_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH14_SHIFT)
#define APBDMA_IRQ_MASK_0_CH14_RANGE                    14:14
#define APBDMA_IRQ_MASK_0_CH14_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH14_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH14_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH14_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH13_SHIFT                    _MK_SHIFT_CONST(13)
#define APBDMA_IRQ_MASK_0_CH13_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH13_SHIFT)
#define APBDMA_IRQ_MASK_0_CH13_RANGE                    13:13
#define APBDMA_IRQ_MASK_0_CH13_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH13_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH13_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH13_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH12_SHIFT                    _MK_SHIFT_CONST(12)
#define APBDMA_IRQ_MASK_0_CH12_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH12_SHIFT)
#define APBDMA_IRQ_MASK_0_CH12_RANGE                    12:12
#define APBDMA_IRQ_MASK_0_CH12_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH12_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH12_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH12_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH11_SHIFT                    _MK_SHIFT_CONST(11)
#define APBDMA_IRQ_MASK_0_CH11_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH11_SHIFT)
#define APBDMA_IRQ_MASK_0_CH11_RANGE                    11:11
#define APBDMA_IRQ_MASK_0_CH11_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH11_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH11_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH11_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH10_SHIFT                    _MK_SHIFT_CONST(10)
#define APBDMA_IRQ_MASK_0_CH10_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH10_SHIFT)
#define APBDMA_IRQ_MASK_0_CH10_RANGE                    10:10
#define APBDMA_IRQ_MASK_0_CH10_WOFFSET                  0x0
#define APBDMA_IRQ_MASK_0_CH10_DEFAULT                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH10_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH10_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH9_SHIFT                     _MK_SHIFT_CONST(9)
#define APBDMA_IRQ_MASK_0_CH9_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH9_SHIFT)
#define APBDMA_IRQ_MASK_0_CH9_RANGE                     9:9
#define APBDMA_IRQ_MASK_0_CH9_WOFFSET                   0x0
#define APBDMA_IRQ_MASK_0_CH9_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH9_DISABLE                   _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH9_ENABLE                    _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH8_SHIFT                     _MK_SHIFT_CONST(8)
#define APBDMA_IRQ_MASK_0_CH8_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH8_SHIFT)
#define APBDMA_IRQ_MASK_0_CH8_RANGE                     8:8
#define APBDMA_IRQ_MASK_0_CH8_WOFFSET                   0x0
#define APBDMA_IRQ_MASK_0_CH8_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH8_DISABLE                   _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH8_ENABLE                    _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH7_SHIFT                     _MK_SHIFT_CONST(7)
#define APBDMA_IRQ_MASK_0_CH7_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH7_SHIFT)
#define APBDMA_IRQ_MASK_0_CH7_RANGE                     7:7
#define APBDMA_IRQ_MASK_0_CH7_WOFFSET                   0x0
#define APBDMA_IRQ_MASK_0_CH7_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH7_DISABLE                   _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH7_ENABLE                    _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH6_SHIFT                     _MK_SHIFT_CONST(6)
#define APBDMA_IRQ_MASK_0_CH6_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH6_SHIFT)
#define APBDMA_IRQ_MASK_0_CH6_RANGE                     6:6
#define APBDMA_IRQ_MASK_0_CH6_WOFFSET                   0x0
#define APBDMA_IRQ_MASK_0_CH6_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH6_DISABLE                   _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH6_ENABLE                    _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH5_SHIFT                     _MK_SHIFT_CONST(5)
#define APBDMA_IRQ_MASK_0_CH5_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH5_SHIFT)
#define APBDMA_IRQ_MASK_0_CH5_RANGE                     5:5
#define APBDMA_IRQ_MASK_0_CH5_WOFFSET                   0x0
#define APBDMA_IRQ_MASK_0_CH5_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH5_DISABLE                   _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH5_ENABLE                    _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH4_SHIFT                     _MK_SHIFT_CONST(4)
#define APBDMA_IRQ_MASK_0_CH4_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH4_SHIFT)
#define APBDMA_IRQ_MASK_0_CH4_RANGE                     4:4
#define APBDMA_IRQ_MASK_0_CH4_WOFFSET                   0x0
#define APBDMA_IRQ_MASK_0_CH4_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH4_DISABLE                   _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH4_ENABLE                    _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH3_SHIFT                     _MK_SHIFT_CONST(3)
#define APBDMA_IRQ_MASK_0_CH3_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH3_SHIFT)
#define APBDMA_IRQ_MASK_0_CH3_RANGE                     3:3
#define APBDMA_IRQ_MASK_0_CH3_WOFFSET                   0x0
#define APBDMA_IRQ_MASK_0_CH3_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH3_DISABLE                   _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH3_ENABLE                    _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH2_SHIFT                     _MK_SHIFT_CONST(2)
#define APBDMA_IRQ_MASK_0_CH2_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH2_SHIFT)
#define APBDMA_IRQ_MASK_0_CH2_RANGE                     2:2
#define APBDMA_IRQ_MASK_0_CH2_WOFFSET                   0x0
#define APBDMA_IRQ_MASK_0_CH2_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH2_DISABLE                   _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH2_ENABLE                    _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH1_SHIFT                     _MK_SHIFT_CONST(1)
#define APBDMA_IRQ_MASK_0_CH1_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH1_SHIFT)
#define APBDMA_IRQ_MASK_0_CH1_RANGE                     1:1
#define APBDMA_IRQ_MASK_0_CH1_WOFFSET                   0x0
#define APBDMA_IRQ_MASK_0_CH1_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH1_DISABLE                   _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH1_ENABLE                    _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_0_CH0_SHIFT                     _MK_SHIFT_CONST(0)
#define APBDMA_IRQ_MASK_0_CH0_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_0_CH0_SHIFT)
#define APBDMA_IRQ_MASK_0_CH0_RANGE                     0:0
#define APBDMA_IRQ_MASK_0_CH0_WOFFSET                   0x0
#define APBDMA_IRQ_MASK_0_CH0_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_0_CH0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_0_CH0_DISABLE                   _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_0_CH0_ENABLE                    _MK_ENUM_CONST(1)


// Register APBDMA_IRQ_MASK_SET_0
#define APBDMA_IRQ_MASK_SET_0                   _MK_ADDR_CONST(0x20)
#define APBDMA_IRQ_MASK_SET_0_SECURE                    0x0
#define APBDMA_IRQ_MASK_SET_0_SCR                       0
#define APBDMA_IRQ_MASK_SET_0_WORD_COUNT                        0x1
#define APBDMA_IRQ_MASK_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_IRQ_MASK_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_READ_MASK                         _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_IRQ_MASK_SET_0_CH31_SHIFT                        _MK_SHIFT_CONST(31)
#define APBDMA_IRQ_MASK_SET_0_CH31_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH31_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH31_RANGE                        31:31
#define APBDMA_IRQ_MASK_SET_0_CH31_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH31_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH31_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH31_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH31_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH31_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH31_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH30_SHIFT                        _MK_SHIFT_CONST(30)
#define APBDMA_IRQ_MASK_SET_0_CH30_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH30_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH30_RANGE                        30:30
#define APBDMA_IRQ_MASK_SET_0_CH30_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH30_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH30_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH30_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH30_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH30_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH30_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH29_SHIFT                        _MK_SHIFT_CONST(29)
#define APBDMA_IRQ_MASK_SET_0_CH29_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH29_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH29_RANGE                        29:29
#define APBDMA_IRQ_MASK_SET_0_CH29_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH29_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH29_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH29_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH29_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH29_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH29_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH28_SHIFT                        _MK_SHIFT_CONST(28)
#define APBDMA_IRQ_MASK_SET_0_CH28_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH28_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH28_RANGE                        28:28
#define APBDMA_IRQ_MASK_SET_0_CH28_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH28_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH28_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH28_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH28_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH28_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH28_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH27_SHIFT                        _MK_SHIFT_CONST(27)
#define APBDMA_IRQ_MASK_SET_0_CH27_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH27_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH27_RANGE                        27:27
#define APBDMA_IRQ_MASK_SET_0_CH27_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH27_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH27_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH27_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH27_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH27_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH27_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH26_SHIFT                        _MK_SHIFT_CONST(26)
#define APBDMA_IRQ_MASK_SET_0_CH26_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH26_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH26_RANGE                        26:26
#define APBDMA_IRQ_MASK_SET_0_CH26_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH26_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH26_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH26_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH26_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH26_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH26_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH25_SHIFT                        _MK_SHIFT_CONST(25)
#define APBDMA_IRQ_MASK_SET_0_CH25_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH25_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH25_RANGE                        25:25
#define APBDMA_IRQ_MASK_SET_0_CH25_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH25_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH25_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH25_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH25_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH25_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH25_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH24_SHIFT                        _MK_SHIFT_CONST(24)
#define APBDMA_IRQ_MASK_SET_0_CH24_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH24_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH24_RANGE                        24:24
#define APBDMA_IRQ_MASK_SET_0_CH24_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH24_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH24_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH24_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH24_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH24_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH24_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH23_SHIFT                        _MK_SHIFT_CONST(23)
#define APBDMA_IRQ_MASK_SET_0_CH23_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH23_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH23_RANGE                        23:23
#define APBDMA_IRQ_MASK_SET_0_CH23_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH23_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH23_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH23_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH23_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH23_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH23_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH22_SHIFT                        _MK_SHIFT_CONST(22)
#define APBDMA_IRQ_MASK_SET_0_CH22_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH22_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH22_RANGE                        22:22
#define APBDMA_IRQ_MASK_SET_0_CH22_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH22_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH22_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH22_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH22_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH22_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH22_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH21_SHIFT                        _MK_SHIFT_CONST(21)
#define APBDMA_IRQ_MASK_SET_0_CH21_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH21_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH21_RANGE                        21:21
#define APBDMA_IRQ_MASK_SET_0_CH21_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH21_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH21_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH21_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH21_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH21_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH21_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH20_SHIFT                        _MK_SHIFT_CONST(20)
#define APBDMA_IRQ_MASK_SET_0_CH20_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH20_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH20_RANGE                        20:20
#define APBDMA_IRQ_MASK_SET_0_CH20_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH20_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH20_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH20_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH20_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH20_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH20_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH19_SHIFT                        _MK_SHIFT_CONST(19)
#define APBDMA_IRQ_MASK_SET_0_CH19_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH19_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH19_RANGE                        19:19
#define APBDMA_IRQ_MASK_SET_0_CH19_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH19_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH19_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH19_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH19_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH19_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH19_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH18_SHIFT                        _MK_SHIFT_CONST(18)
#define APBDMA_IRQ_MASK_SET_0_CH18_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH18_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH18_RANGE                        18:18
#define APBDMA_IRQ_MASK_SET_0_CH18_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH18_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH18_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH18_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH18_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH18_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH18_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH17_SHIFT                        _MK_SHIFT_CONST(17)
#define APBDMA_IRQ_MASK_SET_0_CH17_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH17_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH17_RANGE                        17:17
#define APBDMA_IRQ_MASK_SET_0_CH17_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH17_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH17_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH17_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH17_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH17_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH17_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH16_SHIFT                        _MK_SHIFT_CONST(16)
#define APBDMA_IRQ_MASK_SET_0_CH16_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH16_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH16_RANGE                        16:16
#define APBDMA_IRQ_MASK_SET_0_CH16_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH16_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH16_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH16_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH16_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH16_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH16_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH15_SHIFT                        _MK_SHIFT_CONST(15)
#define APBDMA_IRQ_MASK_SET_0_CH15_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH15_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH15_RANGE                        15:15
#define APBDMA_IRQ_MASK_SET_0_CH15_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH15_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH15_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH15_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH14_SHIFT                        _MK_SHIFT_CONST(14)
#define APBDMA_IRQ_MASK_SET_0_CH14_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH14_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH14_RANGE                        14:14
#define APBDMA_IRQ_MASK_SET_0_CH14_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH14_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH14_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH14_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH13_SHIFT                        _MK_SHIFT_CONST(13)
#define APBDMA_IRQ_MASK_SET_0_CH13_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH13_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH13_RANGE                        13:13
#define APBDMA_IRQ_MASK_SET_0_CH13_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH13_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH13_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH13_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH12_SHIFT                        _MK_SHIFT_CONST(12)
#define APBDMA_IRQ_MASK_SET_0_CH12_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH12_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH12_RANGE                        12:12
#define APBDMA_IRQ_MASK_SET_0_CH12_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH12_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH12_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH12_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH11_SHIFT                        _MK_SHIFT_CONST(11)
#define APBDMA_IRQ_MASK_SET_0_CH11_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH11_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH11_RANGE                        11:11
#define APBDMA_IRQ_MASK_SET_0_CH11_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH11_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH11_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH11_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH10_SHIFT                        _MK_SHIFT_CONST(10)
#define APBDMA_IRQ_MASK_SET_0_CH10_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH10_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH10_RANGE                        10:10
#define APBDMA_IRQ_MASK_SET_0_CH10_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_SET_0_CH10_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH10_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH10_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH9_SHIFT                 _MK_SHIFT_CONST(9)
#define APBDMA_IRQ_MASK_SET_0_CH9_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH9_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH9_RANGE                 9:9
#define APBDMA_IRQ_MASK_SET_0_CH9_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_SET_0_CH9_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH9_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH9_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH8_SHIFT                 _MK_SHIFT_CONST(8)
#define APBDMA_IRQ_MASK_SET_0_CH8_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH8_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH8_RANGE                 8:8
#define APBDMA_IRQ_MASK_SET_0_CH8_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_SET_0_CH8_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH8_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH8_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH7_SHIFT                 _MK_SHIFT_CONST(7)
#define APBDMA_IRQ_MASK_SET_0_CH7_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH7_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH7_RANGE                 7:7
#define APBDMA_IRQ_MASK_SET_0_CH7_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_SET_0_CH7_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH7_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH7_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH6_SHIFT                 _MK_SHIFT_CONST(6)
#define APBDMA_IRQ_MASK_SET_0_CH6_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH6_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH6_RANGE                 6:6
#define APBDMA_IRQ_MASK_SET_0_CH6_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_SET_0_CH6_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH6_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH6_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH5_SHIFT                 _MK_SHIFT_CONST(5)
#define APBDMA_IRQ_MASK_SET_0_CH5_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH5_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH5_RANGE                 5:5
#define APBDMA_IRQ_MASK_SET_0_CH5_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_SET_0_CH5_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH5_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH5_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH4_SHIFT                 _MK_SHIFT_CONST(4)
#define APBDMA_IRQ_MASK_SET_0_CH4_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH4_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH4_RANGE                 4:4
#define APBDMA_IRQ_MASK_SET_0_CH4_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_SET_0_CH4_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH4_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH4_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH3_SHIFT                 _MK_SHIFT_CONST(3)
#define APBDMA_IRQ_MASK_SET_0_CH3_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH3_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH3_RANGE                 3:3
#define APBDMA_IRQ_MASK_SET_0_CH3_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_SET_0_CH3_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH3_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH3_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH2_SHIFT                 _MK_SHIFT_CONST(2)
#define APBDMA_IRQ_MASK_SET_0_CH2_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH2_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH2_RANGE                 2:2
#define APBDMA_IRQ_MASK_SET_0_CH2_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_SET_0_CH2_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH2_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH2_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH1_SHIFT                 _MK_SHIFT_CONST(1)
#define APBDMA_IRQ_MASK_SET_0_CH1_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH1_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH1_RANGE                 1:1
#define APBDMA_IRQ_MASK_SET_0_CH1_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_SET_0_CH1_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH1_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH1_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_SET_0_CH0_SHIFT                 _MK_SHIFT_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH0_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_SET_0_CH0_SHIFT)
#define APBDMA_IRQ_MASK_SET_0_CH0_RANGE                 0:0
#define APBDMA_IRQ_MASK_SET_0_CH0_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_SET_0_CH0_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_SET_0_CH0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_SET_0_CH0_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_SET_0_CH0_ENABLE                        _MK_ENUM_CONST(1)


// Register APBDMA_IRQ_MASK_CLR_0
#define APBDMA_IRQ_MASK_CLR_0                   _MK_ADDR_CONST(0x24)
#define APBDMA_IRQ_MASK_CLR_0_SECURE                    0x0
#define APBDMA_IRQ_MASK_CLR_0_SCR                       0
#define APBDMA_IRQ_MASK_CLR_0_WORD_COUNT                        0x1
#define APBDMA_IRQ_MASK_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_IRQ_MASK_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_READ_MASK                         _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_IRQ_MASK_CLR_0_CH31_SHIFT                        _MK_SHIFT_CONST(31)
#define APBDMA_IRQ_MASK_CLR_0_CH31_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH31_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH31_RANGE                        31:31
#define APBDMA_IRQ_MASK_CLR_0_CH31_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH31_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH31_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH31_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH31_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH31_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH31_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH30_SHIFT                        _MK_SHIFT_CONST(30)
#define APBDMA_IRQ_MASK_CLR_0_CH30_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH30_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH30_RANGE                        30:30
#define APBDMA_IRQ_MASK_CLR_0_CH30_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH30_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH30_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH30_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH30_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH30_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH30_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH29_SHIFT                        _MK_SHIFT_CONST(29)
#define APBDMA_IRQ_MASK_CLR_0_CH29_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH29_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH29_RANGE                        29:29
#define APBDMA_IRQ_MASK_CLR_0_CH29_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH29_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH29_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH29_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH29_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH29_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH29_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH28_SHIFT                        _MK_SHIFT_CONST(28)
#define APBDMA_IRQ_MASK_CLR_0_CH28_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH28_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH28_RANGE                        28:28
#define APBDMA_IRQ_MASK_CLR_0_CH28_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH28_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH28_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH28_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH28_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH28_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH28_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH27_SHIFT                        _MK_SHIFT_CONST(27)
#define APBDMA_IRQ_MASK_CLR_0_CH27_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH27_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH27_RANGE                        27:27
#define APBDMA_IRQ_MASK_CLR_0_CH27_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH27_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH27_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH27_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH27_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH27_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH27_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH26_SHIFT                        _MK_SHIFT_CONST(26)
#define APBDMA_IRQ_MASK_CLR_0_CH26_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH26_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH26_RANGE                        26:26
#define APBDMA_IRQ_MASK_CLR_0_CH26_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH26_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH26_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH26_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH26_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH26_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH26_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH25_SHIFT                        _MK_SHIFT_CONST(25)
#define APBDMA_IRQ_MASK_CLR_0_CH25_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH25_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH25_RANGE                        25:25
#define APBDMA_IRQ_MASK_CLR_0_CH25_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH25_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH25_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH25_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH25_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH25_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH25_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH24_SHIFT                        _MK_SHIFT_CONST(24)
#define APBDMA_IRQ_MASK_CLR_0_CH24_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH24_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH24_RANGE                        24:24
#define APBDMA_IRQ_MASK_CLR_0_CH24_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH24_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH24_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH24_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH24_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH24_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH24_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH23_SHIFT                        _MK_SHIFT_CONST(23)
#define APBDMA_IRQ_MASK_CLR_0_CH23_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH23_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH23_RANGE                        23:23
#define APBDMA_IRQ_MASK_CLR_0_CH23_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH23_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH23_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH23_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH23_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH23_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH23_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH22_SHIFT                        _MK_SHIFT_CONST(22)
#define APBDMA_IRQ_MASK_CLR_0_CH22_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH22_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH22_RANGE                        22:22
#define APBDMA_IRQ_MASK_CLR_0_CH22_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH22_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH22_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH22_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH22_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH22_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH22_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH21_SHIFT                        _MK_SHIFT_CONST(21)
#define APBDMA_IRQ_MASK_CLR_0_CH21_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH21_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH21_RANGE                        21:21
#define APBDMA_IRQ_MASK_CLR_0_CH21_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH21_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH21_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH21_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH21_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH21_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH21_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH20_SHIFT                        _MK_SHIFT_CONST(20)
#define APBDMA_IRQ_MASK_CLR_0_CH20_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH20_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH20_RANGE                        20:20
#define APBDMA_IRQ_MASK_CLR_0_CH20_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH20_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH20_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH20_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH20_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH20_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH20_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH19_SHIFT                        _MK_SHIFT_CONST(19)
#define APBDMA_IRQ_MASK_CLR_0_CH19_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH19_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH19_RANGE                        19:19
#define APBDMA_IRQ_MASK_CLR_0_CH19_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH19_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH19_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH19_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH19_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH19_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH19_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH18_SHIFT                        _MK_SHIFT_CONST(18)
#define APBDMA_IRQ_MASK_CLR_0_CH18_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH18_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH18_RANGE                        18:18
#define APBDMA_IRQ_MASK_CLR_0_CH18_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH18_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH18_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH18_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH18_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH18_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH18_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH17_SHIFT                        _MK_SHIFT_CONST(17)
#define APBDMA_IRQ_MASK_CLR_0_CH17_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH17_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH17_RANGE                        17:17
#define APBDMA_IRQ_MASK_CLR_0_CH17_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH17_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH17_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH17_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH17_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH17_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH17_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH16_SHIFT                        _MK_SHIFT_CONST(16)
#define APBDMA_IRQ_MASK_CLR_0_CH16_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH16_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH16_RANGE                        16:16
#define APBDMA_IRQ_MASK_CLR_0_CH16_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH16_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH16_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH16_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH16_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH16_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH16_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH15_SHIFT                        _MK_SHIFT_CONST(15)
#define APBDMA_IRQ_MASK_CLR_0_CH15_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH15_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH15_RANGE                        15:15
#define APBDMA_IRQ_MASK_CLR_0_CH15_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH15_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH15_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH15_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH14_SHIFT                        _MK_SHIFT_CONST(14)
#define APBDMA_IRQ_MASK_CLR_0_CH14_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH14_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH14_RANGE                        14:14
#define APBDMA_IRQ_MASK_CLR_0_CH14_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH14_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH14_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH14_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH13_SHIFT                        _MK_SHIFT_CONST(13)
#define APBDMA_IRQ_MASK_CLR_0_CH13_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH13_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH13_RANGE                        13:13
#define APBDMA_IRQ_MASK_CLR_0_CH13_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH13_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH13_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH13_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH12_SHIFT                        _MK_SHIFT_CONST(12)
#define APBDMA_IRQ_MASK_CLR_0_CH12_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH12_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH12_RANGE                        12:12
#define APBDMA_IRQ_MASK_CLR_0_CH12_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH12_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH12_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH12_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH11_SHIFT                        _MK_SHIFT_CONST(11)
#define APBDMA_IRQ_MASK_CLR_0_CH11_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH11_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH11_RANGE                        11:11
#define APBDMA_IRQ_MASK_CLR_0_CH11_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH11_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH11_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH11_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH10_SHIFT                        _MK_SHIFT_CONST(10)
#define APBDMA_IRQ_MASK_CLR_0_CH10_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH10_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH10_RANGE                        10:10
#define APBDMA_IRQ_MASK_CLR_0_CH10_WOFFSET                      0x0
#define APBDMA_IRQ_MASK_CLR_0_CH10_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH10_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH10_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH9_SHIFT                 _MK_SHIFT_CONST(9)
#define APBDMA_IRQ_MASK_CLR_0_CH9_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH9_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH9_RANGE                 9:9
#define APBDMA_IRQ_MASK_CLR_0_CH9_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_CLR_0_CH9_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH9_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH9_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH8_SHIFT                 _MK_SHIFT_CONST(8)
#define APBDMA_IRQ_MASK_CLR_0_CH8_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH8_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH8_RANGE                 8:8
#define APBDMA_IRQ_MASK_CLR_0_CH8_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_CLR_0_CH8_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH8_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH8_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH7_SHIFT                 _MK_SHIFT_CONST(7)
#define APBDMA_IRQ_MASK_CLR_0_CH7_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH7_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH7_RANGE                 7:7
#define APBDMA_IRQ_MASK_CLR_0_CH7_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_CLR_0_CH7_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH7_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH7_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH6_SHIFT                 _MK_SHIFT_CONST(6)
#define APBDMA_IRQ_MASK_CLR_0_CH6_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH6_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH6_RANGE                 6:6
#define APBDMA_IRQ_MASK_CLR_0_CH6_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_CLR_0_CH6_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH6_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH6_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH5_SHIFT                 _MK_SHIFT_CONST(5)
#define APBDMA_IRQ_MASK_CLR_0_CH5_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH5_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH5_RANGE                 5:5
#define APBDMA_IRQ_MASK_CLR_0_CH5_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_CLR_0_CH5_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH5_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH5_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH4_SHIFT                 _MK_SHIFT_CONST(4)
#define APBDMA_IRQ_MASK_CLR_0_CH4_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH4_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH4_RANGE                 4:4
#define APBDMA_IRQ_MASK_CLR_0_CH4_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_CLR_0_CH4_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH4_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH4_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH3_SHIFT                 _MK_SHIFT_CONST(3)
#define APBDMA_IRQ_MASK_CLR_0_CH3_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH3_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH3_RANGE                 3:3
#define APBDMA_IRQ_MASK_CLR_0_CH3_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_CLR_0_CH3_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH3_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH3_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH2_SHIFT                 _MK_SHIFT_CONST(2)
#define APBDMA_IRQ_MASK_CLR_0_CH2_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH2_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH2_RANGE                 2:2
#define APBDMA_IRQ_MASK_CLR_0_CH2_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_CLR_0_CH2_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH2_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH2_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH1_SHIFT                 _MK_SHIFT_CONST(1)
#define APBDMA_IRQ_MASK_CLR_0_CH1_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH1_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH1_RANGE                 1:1
#define APBDMA_IRQ_MASK_CLR_0_CH1_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_CLR_0_CH1_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH1_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH1_ENABLE                        _MK_ENUM_CONST(1)

#define APBDMA_IRQ_MASK_CLR_0_CH0_SHIFT                 _MK_SHIFT_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH0_FIELD                 _MK_FIELD_CONST(0x1, APBDMA_IRQ_MASK_CLR_0_CH0_SHIFT)
#define APBDMA_IRQ_MASK_CLR_0_CH0_RANGE                 0:0
#define APBDMA_IRQ_MASK_CLR_0_CH0_WOFFSET                       0x0
#define APBDMA_IRQ_MASK_CLR_0_CH0_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APBDMA_IRQ_MASK_CLR_0_CH0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_IRQ_MASK_CLR_0_CH0_DISABLE                       _MK_ENUM_CONST(0)
#define APBDMA_IRQ_MASK_CLR_0_CH0_ENABLE                        _MK_ENUM_CONST(1)


// Register APBDMA_TRIG_REG_0
#define APBDMA_TRIG_REG_0                       _MK_ADDR_CONST(0x28)
#define APBDMA_TRIG_REG_0_SECURE                        0x0
#define APBDMA_TRIG_REG_0_SCR                   0
#define APBDMA_TRIG_REG_0_WORD_COUNT                    0x1
#define APBDMA_TRIG_REG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_RESET_MASK                    _MK_MASK_CONST(0x1fe)
#define APBDMA_TRIG_REG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_READ_MASK                     _MK_MASK_CONST(0x1fe)
#define APBDMA_TRIG_REG_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_TMR2_SHIFT                    _MK_SHIFT_CONST(8)
#define APBDMA_TRIG_REG_0_TMR2_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_TRIG_REG_0_TMR2_SHIFT)
#define APBDMA_TRIG_REG_0_TMR2_RANGE                    8:8
#define APBDMA_TRIG_REG_0_TMR2_WOFFSET                  0x0
#define APBDMA_TRIG_REG_0_TMR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_TMR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_TRIG_REG_0_TMR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_TMR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_TMR2_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_TRIG_REG_0_TMR2_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_TRIG_REG_0_TMR1_SHIFT                    _MK_SHIFT_CONST(7)
#define APBDMA_TRIG_REG_0_TMR1_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_TRIG_REG_0_TMR1_SHIFT)
#define APBDMA_TRIG_REG_0_TMR1_RANGE                    7:7
#define APBDMA_TRIG_REG_0_TMR1_WOFFSET                  0x0
#define APBDMA_TRIG_REG_0_TMR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_TMR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_TRIG_REG_0_TMR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_TMR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_TMR1_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_TRIG_REG_0_TMR1_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_TRIG_REG_0_XRQ_B_SHIFT                   _MK_SHIFT_CONST(6)
#define APBDMA_TRIG_REG_0_XRQ_B_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_TRIG_REG_0_XRQ_B_SHIFT)
#define APBDMA_TRIG_REG_0_XRQ_B_RANGE                   6:6
#define APBDMA_TRIG_REG_0_XRQ_B_WOFFSET                 0x0
#define APBDMA_TRIG_REG_0_XRQ_B_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_XRQ_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_TRIG_REG_0_XRQ_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_XRQ_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_XRQ_B_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_TRIG_REG_0_XRQ_B_ACTIVE                  _MK_ENUM_CONST(1)

#define APBDMA_TRIG_REG_0_XRQ_A_SHIFT                   _MK_SHIFT_CONST(5)
#define APBDMA_TRIG_REG_0_XRQ_A_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_TRIG_REG_0_XRQ_A_SHIFT)
#define APBDMA_TRIG_REG_0_XRQ_A_RANGE                   5:5
#define APBDMA_TRIG_REG_0_XRQ_A_WOFFSET                 0x0
#define APBDMA_TRIG_REG_0_XRQ_A_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_XRQ_A_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_TRIG_REG_0_XRQ_A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_XRQ_A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_XRQ_A_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_TRIG_REG_0_XRQ_A_ACTIVE                  _MK_ENUM_CONST(1)

#define APBDMA_TRIG_REG_0_SMP_27_SHIFT                  _MK_SHIFT_CONST(4)
#define APBDMA_TRIG_REG_0_SMP_27_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_TRIG_REG_0_SMP_27_SHIFT)
#define APBDMA_TRIG_REG_0_SMP_27_RANGE                  4:4
#define APBDMA_TRIG_REG_0_SMP_27_WOFFSET                        0x0
#define APBDMA_TRIG_REG_0_SMP_27_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_27_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_TRIG_REG_0_SMP_27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_27_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_TRIG_REG_0_SMP_27_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_TRIG_REG_0_SMP_26_SHIFT                  _MK_SHIFT_CONST(3)
#define APBDMA_TRIG_REG_0_SMP_26_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_TRIG_REG_0_SMP_26_SHIFT)
#define APBDMA_TRIG_REG_0_SMP_26_RANGE                  3:3
#define APBDMA_TRIG_REG_0_SMP_26_WOFFSET                        0x0
#define APBDMA_TRIG_REG_0_SMP_26_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_26_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_TRIG_REG_0_SMP_26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_26_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_TRIG_REG_0_SMP_26_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_TRIG_REG_0_SMP_25_SHIFT                  _MK_SHIFT_CONST(2)
#define APBDMA_TRIG_REG_0_SMP_25_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_TRIG_REG_0_SMP_25_SHIFT)
#define APBDMA_TRIG_REG_0_SMP_25_RANGE                  2:2
#define APBDMA_TRIG_REG_0_SMP_25_WOFFSET                        0x0
#define APBDMA_TRIG_REG_0_SMP_25_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_25_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_TRIG_REG_0_SMP_25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_25_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_TRIG_REG_0_SMP_25_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_TRIG_REG_0_SMP_24_SHIFT                  _MK_SHIFT_CONST(1)
#define APBDMA_TRIG_REG_0_SMP_24_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_TRIG_REG_0_SMP_24_SHIFT)
#define APBDMA_TRIG_REG_0_SMP_24_RANGE                  1:1
#define APBDMA_TRIG_REG_0_SMP_24_WOFFSET                        0x0
#define APBDMA_TRIG_REG_0_SMP_24_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_24_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_TRIG_REG_0_SMP_24_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_TRIG_REG_0_SMP_24_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_TRIG_REG_0_SMP_24_ACTIVE                 _MK_ENUM_CONST(1)


// Register APBDMA_CHANNEL_TRIG_REG_0
#define APBDMA_CHANNEL_TRIG_REG_0                       _MK_ADDR_CONST(0x2c)
#define APBDMA_CHANNEL_TRIG_REG_0_SECURE                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_SCR                   0
#define APBDMA_CHANNEL_TRIG_REG_0_WORD_COUNT                    0x1
#define APBDMA_CHANNEL_TRIG_REG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHANNEL_TRIG_REG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHANNEL_TRIG_REG_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_31_SHIFT                  _MK_SHIFT_CONST(31)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_31_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_31_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_31_RANGE                  31:31
#define APBDMA_CHANNEL_TRIG_REG_0_APB_31_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_31_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_31_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_31_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_31_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_31_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_31_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_30_SHIFT                  _MK_SHIFT_CONST(30)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_30_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_30_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_30_RANGE                  30:30
#define APBDMA_CHANNEL_TRIG_REG_0_APB_30_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_30_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_30_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_30_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_30_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_30_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_30_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_29_SHIFT                  _MK_SHIFT_CONST(29)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_29_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_29_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_29_RANGE                  29:29
#define APBDMA_CHANNEL_TRIG_REG_0_APB_29_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_29_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_29_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_29_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_29_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_29_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_29_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_28_SHIFT                  _MK_SHIFT_CONST(28)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_28_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_28_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_28_RANGE                  28:28
#define APBDMA_CHANNEL_TRIG_REG_0_APB_28_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_28_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_28_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_28_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_28_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_28_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_28_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_27_SHIFT                  _MK_SHIFT_CONST(27)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_27_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_27_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_27_RANGE                  27:27
#define APBDMA_CHANNEL_TRIG_REG_0_APB_27_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_27_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_27_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_27_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_27_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_26_SHIFT                  _MK_SHIFT_CONST(26)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_26_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_26_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_26_RANGE                  26:26
#define APBDMA_CHANNEL_TRIG_REG_0_APB_26_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_26_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_26_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_26_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_26_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_25_SHIFT                  _MK_SHIFT_CONST(25)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_25_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_25_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_25_RANGE                  25:25
#define APBDMA_CHANNEL_TRIG_REG_0_APB_25_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_25_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_25_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_25_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_25_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_24_SHIFT                  _MK_SHIFT_CONST(24)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_24_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_24_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_24_RANGE                  24:24
#define APBDMA_CHANNEL_TRIG_REG_0_APB_24_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_24_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_24_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_24_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_24_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_24_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_23_SHIFT                  _MK_SHIFT_CONST(23)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_23_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_23_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_23_RANGE                  23:23
#define APBDMA_CHANNEL_TRIG_REG_0_APB_23_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_23_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_23_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_23_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_23_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_23_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_23_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_22_SHIFT                  _MK_SHIFT_CONST(22)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_22_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_22_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_22_RANGE                  22:22
#define APBDMA_CHANNEL_TRIG_REG_0_APB_22_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_22_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_22_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_22_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_22_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_22_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_22_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_21_SHIFT                  _MK_SHIFT_CONST(21)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_21_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_21_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_21_RANGE                  21:21
#define APBDMA_CHANNEL_TRIG_REG_0_APB_21_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_21_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_21_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_21_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_21_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_21_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_21_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_20_SHIFT                  _MK_SHIFT_CONST(20)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_20_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_20_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_20_RANGE                  20:20
#define APBDMA_CHANNEL_TRIG_REG_0_APB_20_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_20_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_20_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_20_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_20_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_20_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_19_SHIFT                  _MK_SHIFT_CONST(19)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_19_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_19_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_19_RANGE                  19:19
#define APBDMA_CHANNEL_TRIG_REG_0_APB_19_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_19_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_19_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_19_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_19_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_19_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_18_SHIFT                  _MK_SHIFT_CONST(18)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_18_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_18_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_18_RANGE                  18:18
#define APBDMA_CHANNEL_TRIG_REG_0_APB_18_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_18_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_18_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_18_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_18_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_18_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_17_SHIFT                  _MK_SHIFT_CONST(17)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_17_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_17_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_17_RANGE                  17:17
#define APBDMA_CHANNEL_TRIG_REG_0_APB_17_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_17_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_17_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_17_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_17_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_17_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_17_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_16_SHIFT                  _MK_SHIFT_CONST(16)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_16_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_16_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_16_RANGE                  16:16
#define APBDMA_CHANNEL_TRIG_REG_0_APB_16_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_16_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_16_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_16_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_16_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_16_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_16_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_15_SHIFT                  _MK_SHIFT_CONST(15)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_15_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_15_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_15_RANGE                  15:15
#define APBDMA_CHANNEL_TRIG_REG_0_APB_15_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_15_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_15_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_15_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_15_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_14_SHIFT                  _MK_SHIFT_CONST(14)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_14_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_14_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_14_RANGE                  14:14
#define APBDMA_CHANNEL_TRIG_REG_0_APB_14_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_14_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_14_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_14_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_14_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_13_SHIFT                  _MK_SHIFT_CONST(13)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_13_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_13_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_13_RANGE                  13:13
#define APBDMA_CHANNEL_TRIG_REG_0_APB_13_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_13_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_13_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_13_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_13_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_12_SHIFT                  _MK_SHIFT_CONST(12)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_12_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_12_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_12_RANGE                  12:12
#define APBDMA_CHANNEL_TRIG_REG_0_APB_12_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_12_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_12_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_12_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_12_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_11_SHIFT                  _MK_SHIFT_CONST(11)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_11_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_11_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_11_RANGE                  11:11
#define APBDMA_CHANNEL_TRIG_REG_0_APB_11_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_11_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_11_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_11_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_11_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_10_SHIFT                  _MK_SHIFT_CONST(10)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_10_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_10_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_10_RANGE                  10:10
#define APBDMA_CHANNEL_TRIG_REG_0_APB_10_WOFFSET                        0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_10_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_10_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_10_NOT_ACTIVE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_10_ACTIVE                 _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_9_SHIFT                   _MK_SHIFT_CONST(9)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_9_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_9_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_9_RANGE                   9:9
#define APBDMA_CHANNEL_TRIG_REG_0_APB_9_WOFFSET                 0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_9_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_9_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_9_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_9_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_9_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_9_ACTIVE                  _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_8_SHIFT                   _MK_SHIFT_CONST(8)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_8_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_8_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_8_RANGE                   8:8
#define APBDMA_CHANNEL_TRIG_REG_0_APB_8_WOFFSET                 0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_8_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_8_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_8_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_8_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_8_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_8_ACTIVE                  _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_7_SHIFT                   _MK_SHIFT_CONST(7)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_7_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_7_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_7_RANGE                   7:7
#define APBDMA_CHANNEL_TRIG_REG_0_APB_7_WOFFSET                 0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_7_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_7_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_7_ACTIVE                  _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_6_SHIFT                   _MK_SHIFT_CONST(6)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_6_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_6_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_6_RANGE                   6:6
#define APBDMA_CHANNEL_TRIG_REG_0_APB_6_WOFFSET                 0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_6_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_6_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_6_ACTIVE                  _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_5_SHIFT                   _MK_SHIFT_CONST(5)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_5_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_5_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_5_RANGE                   5:5
#define APBDMA_CHANNEL_TRIG_REG_0_APB_5_WOFFSET                 0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_5_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_5_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_5_ACTIVE                  _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_4_SHIFT                   _MK_SHIFT_CONST(4)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_4_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_4_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_4_RANGE                   4:4
#define APBDMA_CHANNEL_TRIG_REG_0_APB_4_WOFFSET                 0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_4_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_4_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_4_ACTIVE                  _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_3_SHIFT                   _MK_SHIFT_CONST(3)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_3_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_3_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_3_RANGE                   3:3
#define APBDMA_CHANNEL_TRIG_REG_0_APB_3_WOFFSET                 0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_3_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_3_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_3_ACTIVE                  _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_2_SHIFT                   _MK_SHIFT_CONST(2)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_2_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_2_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_2_RANGE                   2:2
#define APBDMA_CHANNEL_TRIG_REG_0_APB_2_WOFFSET                 0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_2_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_2_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_2_ACTIVE                  _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_1_SHIFT                   _MK_SHIFT_CONST(1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_1_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_1_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_1_RANGE                   1:1
#define APBDMA_CHANNEL_TRIG_REG_0_APB_1_WOFFSET                 0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_1_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_1_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_1_ACTIVE                  _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_TRIG_REG_0_APB_0_SHIFT                   _MK_SHIFT_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_0_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_TRIG_REG_0_APB_0_SHIFT)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_0_RANGE                   0:0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_0_WOFFSET                 0x0
#define APBDMA_CHANNEL_TRIG_REG_0_APB_0_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_0_NOT_ACTIVE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_TRIG_REG_0_APB_0_ACTIVE                  _MK_ENUM_CONST(1)


// Register APBDMA_DMA_STATUS_0
#define APBDMA_DMA_STATUS_0                     _MK_ADDR_CONST(0x30)
#define APBDMA_DMA_STATUS_0_SECURE                      0x0
#define APBDMA_DMA_STATUS_0_SCR                         0
#define APBDMA_DMA_STATUS_0_WORD_COUNT                  0x1
#define APBDMA_DMA_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define APBDMA_DMA_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define APBDMA_DMA_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_31_SHIFT                    _MK_SHIFT_CONST(31)
#define APBDMA_DMA_STATUS_0_ISE_EOC_31_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_31_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_31_RANGE                    31:31
#define APBDMA_DMA_STATUS_0_ISE_EOC_31_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_31_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_31_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_31_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_31_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_31_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_31_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_30_SHIFT                    _MK_SHIFT_CONST(30)
#define APBDMA_DMA_STATUS_0_ISE_EOC_30_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_30_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_30_RANGE                    30:30
#define APBDMA_DMA_STATUS_0_ISE_EOC_30_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_30_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_30_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_30_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_30_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_30_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_30_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_29_SHIFT                    _MK_SHIFT_CONST(29)
#define APBDMA_DMA_STATUS_0_ISE_EOC_29_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_29_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_29_RANGE                    29:29
#define APBDMA_DMA_STATUS_0_ISE_EOC_29_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_29_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_29_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_29_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_29_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_29_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_29_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_28_SHIFT                    _MK_SHIFT_CONST(28)
#define APBDMA_DMA_STATUS_0_ISE_EOC_28_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_28_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_28_RANGE                    28:28
#define APBDMA_DMA_STATUS_0_ISE_EOC_28_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_28_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_28_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_28_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_28_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_28_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_28_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_27_SHIFT                    _MK_SHIFT_CONST(27)
#define APBDMA_DMA_STATUS_0_ISE_EOC_27_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_27_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_27_RANGE                    27:27
#define APBDMA_DMA_STATUS_0_ISE_EOC_27_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_27_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_27_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_27_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_27_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_27_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_27_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_26_SHIFT                    _MK_SHIFT_CONST(26)
#define APBDMA_DMA_STATUS_0_ISE_EOC_26_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_26_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_26_RANGE                    26:26
#define APBDMA_DMA_STATUS_0_ISE_EOC_26_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_26_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_26_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_26_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_26_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_26_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_26_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_25_SHIFT                    _MK_SHIFT_CONST(25)
#define APBDMA_DMA_STATUS_0_ISE_EOC_25_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_25_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_25_RANGE                    25:25
#define APBDMA_DMA_STATUS_0_ISE_EOC_25_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_25_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_25_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_25_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_25_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_25_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_25_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_24_SHIFT                    _MK_SHIFT_CONST(24)
#define APBDMA_DMA_STATUS_0_ISE_EOC_24_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_24_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_24_RANGE                    24:24
#define APBDMA_DMA_STATUS_0_ISE_EOC_24_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_24_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_24_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_24_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_24_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_24_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_24_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_23_SHIFT                    _MK_SHIFT_CONST(23)
#define APBDMA_DMA_STATUS_0_ISE_EOC_23_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_23_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_23_RANGE                    23:23
#define APBDMA_DMA_STATUS_0_ISE_EOC_23_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_23_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_23_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_23_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_23_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_23_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_23_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_22_SHIFT                    _MK_SHIFT_CONST(22)
#define APBDMA_DMA_STATUS_0_ISE_EOC_22_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_22_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_22_RANGE                    22:22
#define APBDMA_DMA_STATUS_0_ISE_EOC_22_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_22_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_22_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_22_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_22_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_22_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_22_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_21_SHIFT                    _MK_SHIFT_CONST(21)
#define APBDMA_DMA_STATUS_0_ISE_EOC_21_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_21_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_21_RANGE                    21:21
#define APBDMA_DMA_STATUS_0_ISE_EOC_21_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_21_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_21_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_21_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_21_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_21_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_21_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_20_SHIFT                    _MK_SHIFT_CONST(20)
#define APBDMA_DMA_STATUS_0_ISE_EOC_20_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_20_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_20_RANGE                    20:20
#define APBDMA_DMA_STATUS_0_ISE_EOC_20_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_20_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_20_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_20_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_20_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_20_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_20_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_19_SHIFT                    _MK_SHIFT_CONST(19)
#define APBDMA_DMA_STATUS_0_ISE_EOC_19_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_19_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_19_RANGE                    19:19
#define APBDMA_DMA_STATUS_0_ISE_EOC_19_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_19_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_19_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_19_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_19_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_19_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_19_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_18_SHIFT                    _MK_SHIFT_CONST(18)
#define APBDMA_DMA_STATUS_0_ISE_EOC_18_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_18_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_18_RANGE                    18:18
#define APBDMA_DMA_STATUS_0_ISE_EOC_18_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_18_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_18_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_18_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_18_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_18_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_18_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_17_SHIFT                    _MK_SHIFT_CONST(17)
#define APBDMA_DMA_STATUS_0_ISE_EOC_17_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_17_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_17_RANGE                    17:17
#define APBDMA_DMA_STATUS_0_ISE_EOC_17_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_17_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_17_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_17_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_17_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_17_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_17_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_16_SHIFT                    _MK_SHIFT_CONST(16)
#define APBDMA_DMA_STATUS_0_ISE_EOC_16_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_16_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_16_RANGE                    16:16
#define APBDMA_DMA_STATUS_0_ISE_EOC_16_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_16_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_16_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_16_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_16_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_16_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_16_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_15_SHIFT                    _MK_SHIFT_CONST(15)
#define APBDMA_DMA_STATUS_0_ISE_EOC_15_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_15_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_15_RANGE                    15:15
#define APBDMA_DMA_STATUS_0_ISE_EOC_15_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_15_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_15_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_15_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_14_SHIFT                    _MK_SHIFT_CONST(14)
#define APBDMA_DMA_STATUS_0_ISE_EOC_14_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_14_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_14_RANGE                    14:14
#define APBDMA_DMA_STATUS_0_ISE_EOC_14_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_14_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_14_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_14_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_13_SHIFT                    _MK_SHIFT_CONST(13)
#define APBDMA_DMA_STATUS_0_ISE_EOC_13_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_13_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_13_RANGE                    13:13
#define APBDMA_DMA_STATUS_0_ISE_EOC_13_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_13_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_13_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_13_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_12_SHIFT                    _MK_SHIFT_CONST(12)
#define APBDMA_DMA_STATUS_0_ISE_EOC_12_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_12_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_12_RANGE                    12:12
#define APBDMA_DMA_STATUS_0_ISE_EOC_12_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_12_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_12_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_12_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_11_SHIFT                    _MK_SHIFT_CONST(11)
#define APBDMA_DMA_STATUS_0_ISE_EOC_11_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_11_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_11_RANGE                    11:11
#define APBDMA_DMA_STATUS_0_ISE_EOC_11_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_11_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_11_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_11_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_10_SHIFT                    _MK_SHIFT_CONST(10)
#define APBDMA_DMA_STATUS_0_ISE_EOC_10_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_10_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_10_RANGE                    10:10
#define APBDMA_DMA_STATUS_0_ISE_EOC_10_WOFFSET                  0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_10_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_10_NOT_ACTIVE                       _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_10_ACTIVE                   _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_9_SHIFT                     _MK_SHIFT_CONST(9)
#define APBDMA_DMA_STATUS_0_ISE_EOC_9_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_9_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_9_RANGE                     9:9
#define APBDMA_DMA_STATUS_0_ISE_EOC_9_WOFFSET                   0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_9_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_9_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_9_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_8_SHIFT                     _MK_SHIFT_CONST(8)
#define APBDMA_DMA_STATUS_0_ISE_EOC_8_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_8_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_8_RANGE                     8:8
#define APBDMA_DMA_STATUS_0_ISE_EOC_8_WOFFSET                   0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_8_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_8_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_8_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_7_SHIFT                     _MK_SHIFT_CONST(7)
#define APBDMA_DMA_STATUS_0_ISE_EOC_7_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_7_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_7_RANGE                     7:7
#define APBDMA_DMA_STATUS_0_ISE_EOC_7_WOFFSET                   0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_7_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_7_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_7_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_6_SHIFT                     _MK_SHIFT_CONST(6)
#define APBDMA_DMA_STATUS_0_ISE_EOC_6_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_6_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_6_RANGE                     6:6
#define APBDMA_DMA_STATUS_0_ISE_EOC_6_WOFFSET                   0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_6_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_6_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_6_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_5_SHIFT                     _MK_SHIFT_CONST(5)
#define APBDMA_DMA_STATUS_0_ISE_EOC_5_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_5_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_5_RANGE                     5:5
#define APBDMA_DMA_STATUS_0_ISE_EOC_5_WOFFSET                   0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_5_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_5_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_5_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_4_SHIFT                     _MK_SHIFT_CONST(4)
#define APBDMA_DMA_STATUS_0_ISE_EOC_4_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_4_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_4_RANGE                     4:4
#define APBDMA_DMA_STATUS_0_ISE_EOC_4_WOFFSET                   0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_4_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_4_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_4_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_3_SHIFT                     _MK_SHIFT_CONST(3)
#define APBDMA_DMA_STATUS_0_ISE_EOC_3_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_3_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_3_RANGE                     3:3
#define APBDMA_DMA_STATUS_0_ISE_EOC_3_WOFFSET                   0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_3_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_3_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_3_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_2_SHIFT                     _MK_SHIFT_CONST(2)
#define APBDMA_DMA_STATUS_0_ISE_EOC_2_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_2_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_2_RANGE                     2:2
#define APBDMA_DMA_STATUS_0_ISE_EOC_2_WOFFSET                   0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_2_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_2_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_2_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_1_SHIFT                     _MK_SHIFT_CONST(1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_1_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_1_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_1_RANGE                     1:1
#define APBDMA_DMA_STATUS_0_ISE_EOC_1_WOFFSET                   0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_1_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_1_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_1_ACTIVE                    _MK_ENUM_CONST(1)

#define APBDMA_DMA_STATUS_0_ISE_EOC_0_SHIFT                     _MK_SHIFT_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_0_FIELD                     _MK_FIELD_CONST(0x1, APBDMA_DMA_STATUS_0_ISE_EOC_0_SHIFT)
#define APBDMA_DMA_STATUS_0_ISE_EOC_0_RANGE                     0:0
#define APBDMA_DMA_STATUS_0_ISE_EOC_0_WOFFSET                   0x0
#define APBDMA_DMA_STATUS_0_ISE_EOC_0_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APBDMA_DMA_STATUS_0_ISE_EOC_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_0_NOT_ACTIVE                        _MK_ENUM_CONST(0)
#define APBDMA_DMA_STATUS_0_ISE_EOC_0_ACTIVE                    _MK_ENUM_CONST(1)


// Register APBDMA_CHANNEL_EN_REG_0
#define APBDMA_CHANNEL_EN_REG_0                 _MK_ADDR_CONST(0x34)
#define APBDMA_CHANNEL_EN_REG_0_SECURE                  0x0
#define APBDMA_CHANNEL_EN_REG_0_SCR                     0
#define APBDMA_CHANNEL_EN_REG_0_WORD_COUNT                      0x1
#define APBDMA_CHANNEL_EN_REG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHANNEL_EN_REG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHANNEL_EN_REG_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHANNEL_EN_REG_0_CH31_CNT_EN_SHIFT                       _MK_SHIFT_CONST(31)
#define APBDMA_CHANNEL_EN_REG_0_CH31_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH31_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH31_CNT_EN_RANGE                       31:31
#define APBDMA_CHANNEL_EN_REG_0_CH31_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH31_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH31_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH31_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH31_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH31_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH31_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH30_CNT_EN_SHIFT                       _MK_SHIFT_CONST(30)
#define APBDMA_CHANNEL_EN_REG_0_CH30_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH30_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH30_CNT_EN_RANGE                       30:30
#define APBDMA_CHANNEL_EN_REG_0_CH30_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH30_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH30_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH30_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH30_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH30_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH30_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH29_CNT_EN_SHIFT                       _MK_SHIFT_CONST(29)
#define APBDMA_CHANNEL_EN_REG_0_CH29_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH29_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH29_CNT_EN_RANGE                       29:29
#define APBDMA_CHANNEL_EN_REG_0_CH29_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH29_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH29_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH29_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH29_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH29_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH29_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH28_CNT_EN_SHIFT                       _MK_SHIFT_CONST(28)
#define APBDMA_CHANNEL_EN_REG_0_CH28_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH28_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH28_CNT_EN_RANGE                       28:28
#define APBDMA_CHANNEL_EN_REG_0_CH28_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH28_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH28_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH28_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH28_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH28_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH28_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH27_CNT_EN_SHIFT                       _MK_SHIFT_CONST(27)
#define APBDMA_CHANNEL_EN_REG_0_CH27_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH27_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH27_CNT_EN_RANGE                       27:27
#define APBDMA_CHANNEL_EN_REG_0_CH27_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH27_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH27_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH27_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH27_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH27_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH27_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH26_CNT_EN_SHIFT                       _MK_SHIFT_CONST(26)
#define APBDMA_CHANNEL_EN_REG_0_CH26_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH26_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH26_CNT_EN_RANGE                       26:26
#define APBDMA_CHANNEL_EN_REG_0_CH26_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH26_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH26_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH26_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH26_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH26_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH26_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH25_CNT_EN_SHIFT                       _MK_SHIFT_CONST(25)
#define APBDMA_CHANNEL_EN_REG_0_CH25_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH25_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH25_CNT_EN_RANGE                       25:25
#define APBDMA_CHANNEL_EN_REG_0_CH25_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH25_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH25_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH25_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH25_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH25_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH25_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH24_CNT_EN_SHIFT                       _MK_SHIFT_CONST(24)
#define APBDMA_CHANNEL_EN_REG_0_CH24_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH24_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH24_CNT_EN_RANGE                       24:24
#define APBDMA_CHANNEL_EN_REG_0_CH24_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH24_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH24_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH24_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH24_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH24_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH24_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH23_CNT_EN_SHIFT                       _MK_SHIFT_CONST(23)
#define APBDMA_CHANNEL_EN_REG_0_CH23_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH23_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH23_CNT_EN_RANGE                       23:23
#define APBDMA_CHANNEL_EN_REG_0_CH23_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH23_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH23_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH23_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH23_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH23_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH23_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH22_CNT_EN_SHIFT                       _MK_SHIFT_CONST(22)
#define APBDMA_CHANNEL_EN_REG_0_CH22_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH22_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH22_CNT_EN_RANGE                       22:22
#define APBDMA_CHANNEL_EN_REG_0_CH22_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH22_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH22_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH22_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH22_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH22_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH22_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH21_CNT_EN_SHIFT                       _MK_SHIFT_CONST(21)
#define APBDMA_CHANNEL_EN_REG_0_CH21_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH21_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH21_CNT_EN_RANGE                       21:21
#define APBDMA_CHANNEL_EN_REG_0_CH21_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH21_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH21_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH21_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH21_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH21_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH21_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH20_CNT_EN_SHIFT                       _MK_SHIFT_CONST(20)
#define APBDMA_CHANNEL_EN_REG_0_CH20_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH20_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH20_CNT_EN_RANGE                       20:20
#define APBDMA_CHANNEL_EN_REG_0_CH20_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH20_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH20_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH20_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH20_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH20_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH20_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH19_CNT_EN_SHIFT                       _MK_SHIFT_CONST(19)
#define APBDMA_CHANNEL_EN_REG_0_CH19_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH19_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH19_CNT_EN_RANGE                       19:19
#define APBDMA_CHANNEL_EN_REG_0_CH19_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH19_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH19_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH19_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH19_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH19_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH19_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH18_CNT_EN_SHIFT                       _MK_SHIFT_CONST(18)
#define APBDMA_CHANNEL_EN_REG_0_CH18_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH18_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH18_CNT_EN_RANGE                       18:18
#define APBDMA_CHANNEL_EN_REG_0_CH18_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH18_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH18_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH18_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH18_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH18_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH18_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH17_CNT_EN_SHIFT                       _MK_SHIFT_CONST(17)
#define APBDMA_CHANNEL_EN_REG_0_CH17_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH17_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH17_CNT_EN_RANGE                       17:17
#define APBDMA_CHANNEL_EN_REG_0_CH17_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH17_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH17_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH17_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH17_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH17_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH17_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH16_CNT_EN_SHIFT                       _MK_SHIFT_CONST(16)
#define APBDMA_CHANNEL_EN_REG_0_CH16_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH16_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH16_CNT_EN_RANGE                       16:16
#define APBDMA_CHANNEL_EN_REG_0_CH16_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH16_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH16_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH16_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH16_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH16_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH16_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH15_CNT_EN_SHIFT                       _MK_SHIFT_CONST(15)
#define APBDMA_CHANNEL_EN_REG_0_CH15_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH15_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH15_CNT_EN_RANGE                       15:15
#define APBDMA_CHANNEL_EN_REG_0_CH15_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH15_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH15_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH15_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH15_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH15_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH15_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH14_CNT_EN_SHIFT                       _MK_SHIFT_CONST(14)
#define APBDMA_CHANNEL_EN_REG_0_CH14_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH14_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH14_CNT_EN_RANGE                       14:14
#define APBDMA_CHANNEL_EN_REG_0_CH14_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH14_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH14_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH14_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH14_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH14_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH14_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH13_CNT_EN_SHIFT                       _MK_SHIFT_CONST(13)
#define APBDMA_CHANNEL_EN_REG_0_CH13_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH13_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH13_CNT_EN_RANGE                       13:13
#define APBDMA_CHANNEL_EN_REG_0_CH13_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH13_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH13_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH13_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH13_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH13_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH13_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH12_CNT_EN_SHIFT                       _MK_SHIFT_CONST(12)
#define APBDMA_CHANNEL_EN_REG_0_CH12_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH12_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH12_CNT_EN_RANGE                       12:12
#define APBDMA_CHANNEL_EN_REG_0_CH12_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH12_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH12_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH12_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH12_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH12_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH12_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH11_CNT_EN_SHIFT                       _MK_SHIFT_CONST(11)
#define APBDMA_CHANNEL_EN_REG_0_CH11_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH11_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH11_CNT_EN_RANGE                       11:11
#define APBDMA_CHANNEL_EN_REG_0_CH11_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH11_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH11_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH11_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH11_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH11_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH11_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH10_CNT_EN_SHIFT                       _MK_SHIFT_CONST(10)
#define APBDMA_CHANNEL_EN_REG_0_CH10_CNT_EN_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH10_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH10_CNT_EN_RANGE                       10:10
#define APBDMA_CHANNEL_EN_REG_0_CH10_CNT_EN_WOFFSET                     0x0
#define APBDMA_CHANNEL_EN_REG_0_CH10_CNT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH10_CNT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH10_CNT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH10_CNT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH10_CNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH10_CNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH9_CNT_EN_SHIFT                        _MK_SHIFT_CONST(9)
#define APBDMA_CHANNEL_EN_REG_0_CH9_CNT_EN_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH9_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH9_CNT_EN_RANGE                        9:9
#define APBDMA_CHANNEL_EN_REG_0_CH9_CNT_EN_WOFFSET                      0x0
#define APBDMA_CHANNEL_EN_REG_0_CH9_CNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH9_CNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH9_CNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH9_CNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH9_CNT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH9_CNT_EN_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH8_CNT_EN_SHIFT                        _MK_SHIFT_CONST(8)
#define APBDMA_CHANNEL_EN_REG_0_CH8_CNT_EN_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH8_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH8_CNT_EN_RANGE                        8:8
#define APBDMA_CHANNEL_EN_REG_0_CH8_CNT_EN_WOFFSET                      0x0
#define APBDMA_CHANNEL_EN_REG_0_CH8_CNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH8_CNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH8_CNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH8_CNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH8_CNT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH8_CNT_EN_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH7_CNT_EN_SHIFT                        _MK_SHIFT_CONST(7)
#define APBDMA_CHANNEL_EN_REG_0_CH7_CNT_EN_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH7_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH7_CNT_EN_RANGE                        7:7
#define APBDMA_CHANNEL_EN_REG_0_CH7_CNT_EN_WOFFSET                      0x0
#define APBDMA_CHANNEL_EN_REG_0_CH7_CNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH7_CNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH7_CNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH7_CNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH7_CNT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH7_CNT_EN_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH6_CNT_EN_SHIFT                        _MK_SHIFT_CONST(6)
#define APBDMA_CHANNEL_EN_REG_0_CH6_CNT_EN_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH6_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH6_CNT_EN_RANGE                        6:6
#define APBDMA_CHANNEL_EN_REG_0_CH6_CNT_EN_WOFFSET                      0x0
#define APBDMA_CHANNEL_EN_REG_0_CH6_CNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH6_CNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH6_CNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH6_CNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH6_CNT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH6_CNT_EN_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH5_CNT_EN_SHIFT                        _MK_SHIFT_CONST(5)
#define APBDMA_CHANNEL_EN_REG_0_CH5_CNT_EN_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH5_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH5_CNT_EN_RANGE                        5:5
#define APBDMA_CHANNEL_EN_REG_0_CH5_CNT_EN_WOFFSET                      0x0
#define APBDMA_CHANNEL_EN_REG_0_CH5_CNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH5_CNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH5_CNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH5_CNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH5_CNT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH5_CNT_EN_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH4_CNT_EN_SHIFT                        _MK_SHIFT_CONST(4)
#define APBDMA_CHANNEL_EN_REG_0_CH4_CNT_EN_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH4_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH4_CNT_EN_RANGE                        4:4
#define APBDMA_CHANNEL_EN_REG_0_CH4_CNT_EN_WOFFSET                      0x0
#define APBDMA_CHANNEL_EN_REG_0_CH4_CNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH4_CNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH4_CNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH4_CNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH4_CNT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH4_CNT_EN_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH3_CNT_EN_SHIFT                        _MK_SHIFT_CONST(3)
#define APBDMA_CHANNEL_EN_REG_0_CH3_CNT_EN_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH3_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH3_CNT_EN_RANGE                        3:3
#define APBDMA_CHANNEL_EN_REG_0_CH3_CNT_EN_WOFFSET                      0x0
#define APBDMA_CHANNEL_EN_REG_0_CH3_CNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH3_CNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH3_CNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH3_CNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH3_CNT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH3_CNT_EN_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH2_CNT_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define APBDMA_CHANNEL_EN_REG_0_CH2_CNT_EN_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH2_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH2_CNT_EN_RANGE                        2:2
#define APBDMA_CHANNEL_EN_REG_0_CH2_CNT_EN_WOFFSET                      0x0
#define APBDMA_CHANNEL_EN_REG_0_CH2_CNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH2_CNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH2_CNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH2_CNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH2_CNT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH2_CNT_EN_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH1_CNT_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define APBDMA_CHANNEL_EN_REG_0_CH1_CNT_EN_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH1_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH1_CNT_EN_RANGE                        1:1
#define APBDMA_CHANNEL_EN_REG_0_CH1_CNT_EN_WOFFSET                      0x0
#define APBDMA_CHANNEL_EN_REG_0_CH1_CNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH1_CNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH1_CNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH1_CNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH1_CNT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH1_CNT_EN_ENABLE                       _MK_ENUM_CONST(1)

#define APBDMA_CHANNEL_EN_REG_0_CH0_CNT_EN_SHIFT                        _MK_SHIFT_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH0_CNT_EN_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_EN_REG_0_CH0_CNT_EN_SHIFT)
#define APBDMA_CHANNEL_EN_REG_0_CH0_CNT_EN_RANGE                        0:0
#define APBDMA_CHANNEL_EN_REG_0_CH0_CNT_EN_WOFFSET                      0x0
#define APBDMA_CHANNEL_EN_REG_0_CH0_CNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH0_CNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_EN_REG_0_CH0_CNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH0_CNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_EN_REG_0_CH0_CNT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APBDMA_CHANNEL_EN_REG_0_CH0_CNT_EN_ENABLE                       _MK_ENUM_CONST(1)


// Register APBDMA_SECURITY_REG_0
#define APBDMA_SECURITY_REG_0                   _MK_ADDR_CONST(0x38)
#define APBDMA_SECURITY_REG_0_SECURE                    0x1
#define APBDMA_SECURITY_REG_0_SCR                       0
#define APBDMA_SECURITY_REG_0_WORD_COUNT                        0x1
#define APBDMA_SECURITY_REG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_SECURITY_REG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APBDMA_SECURITY_REG_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_SECURITY_REG_0_CH_31_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(31)
#define APBDMA_SECURITY_REG_0_CH_31_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_31_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_31_SECURITY_EN_RANGE                   31:31
#define APBDMA_SECURITY_REG_0_CH_31_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_31_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_31_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_31_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_31_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_31_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_31_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_30_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(30)
#define APBDMA_SECURITY_REG_0_CH_30_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_30_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_30_SECURITY_EN_RANGE                   30:30
#define APBDMA_SECURITY_REG_0_CH_30_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_30_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_30_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_30_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_30_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_30_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_30_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_29_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(29)
#define APBDMA_SECURITY_REG_0_CH_29_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_29_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_29_SECURITY_EN_RANGE                   29:29
#define APBDMA_SECURITY_REG_0_CH_29_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_29_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_29_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_29_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_29_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_29_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_29_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_28_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(28)
#define APBDMA_SECURITY_REG_0_CH_28_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_28_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_28_SECURITY_EN_RANGE                   28:28
#define APBDMA_SECURITY_REG_0_CH_28_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_28_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_28_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_28_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_28_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_28_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_28_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_27_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(27)
#define APBDMA_SECURITY_REG_0_CH_27_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_27_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_27_SECURITY_EN_RANGE                   27:27
#define APBDMA_SECURITY_REG_0_CH_27_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_27_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_27_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_27_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_27_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_27_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_27_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_26_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(26)
#define APBDMA_SECURITY_REG_0_CH_26_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_26_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_26_SECURITY_EN_RANGE                   26:26
#define APBDMA_SECURITY_REG_0_CH_26_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_26_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_26_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_26_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_26_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_26_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_26_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_25_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(25)
#define APBDMA_SECURITY_REG_0_CH_25_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_25_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_25_SECURITY_EN_RANGE                   25:25
#define APBDMA_SECURITY_REG_0_CH_25_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_25_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_25_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_25_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_25_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_25_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_25_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_24_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(24)
#define APBDMA_SECURITY_REG_0_CH_24_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_24_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_24_SECURITY_EN_RANGE                   24:24
#define APBDMA_SECURITY_REG_0_CH_24_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_24_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_24_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_24_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_24_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_24_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_24_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_23_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(23)
#define APBDMA_SECURITY_REG_0_CH_23_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_23_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_23_SECURITY_EN_RANGE                   23:23
#define APBDMA_SECURITY_REG_0_CH_23_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_23_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_23_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_23_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_23_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_23_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_23_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_22_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(22)
#define APBDMA_SECURITY_REG_0_CH_22_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_22_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_22_SECURITY_EN_RANGE                   22:22
#define APBDMA_SECURITY_REG_0_CH_22_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_22_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_22_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_22_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_22_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_22_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_22_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_21_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(21)
#define APBDMA_SECURITY_REG_0_CH_21_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_21_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_21_SECURITY_EN_RANGE                   21:21
#define APBDMA_SECURITY_REG_0_CH_21_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_21_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_21_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_21_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_21_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_21_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_21_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_20_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(20)
#define APBDMA_SECURITY_REG_0_CH_20_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_20_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_20_SECURITY_EN_RANGE                   20:20
#define APBDMA_SECURITY_REG_0_CH_20_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_20_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_20_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_20_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_20_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_20_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_20_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_19_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(19)
#define APBDMA_SECURITY_REG_0_CH_19_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_19_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_19_SECURITY_EN_RANGE                   19:19
#define APBDMA_SECURITY_REG_0_CH_19_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_19_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_19_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_19_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_19_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_19_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_19_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_18_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(18)
#define APBDMA_SECURITY_REG_0_CH_18_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_18_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_18_SECURITY_EN_RANGE                   18:18
#define APBDMA_SECURITY_REG_0_CH_18_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_18_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_18_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_18_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_18_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_18_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_18_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_17_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(17)
#define APBDMA_SECURITY_REG_0_CH_17_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_17_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_17_SECURITY_EN_RANGE                   17:17
#define APBDMA_SECURITY_REG_0_CH_17_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_17_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_17_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_17_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_17_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_17_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_17_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_16_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(16)
#define APBDMA_SECURITY_REG_0_CH_16_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_16_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_16_SECURITY_EN_RANGE                   16:16
#define APBDMA_SECURITY_REG_0_CH_16_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_16_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_16_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_16_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_16_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_16_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_16_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_15_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(15)
#define APBDMA_SECURITY_REG_0_CH_15_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_15_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_15_SECURITY_EN_RANGE                   15:15
#define APBDMA_SECURITY_REG_0_CH_15_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_15_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_15_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_15_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_15_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_15_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_15_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_14_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(14)
#define APBDMA_SECURITY_REG_0_CH_14_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_14_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_14_SECURITY_EN_RANGE                   14:14
#define APBDMA_SECURITY_REG_0_CH_14_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_14_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_14_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_14_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_14_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_14_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_14_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_13_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(13)
#define APBDMA_SECURITY_REG_0_CH_13_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_13_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_13_SECURITY_EN_RANGE                   13:13
#define APBDMA_SECURITY_REG_0_CH_13_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_13_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_13_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_13_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_13_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_13_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_13_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_12_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(12)
#define APBDMA_SECURITY_REG_0_CH_12_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_12_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_12_SECURITY_EN_RANGE                   12:12
#define APBDMA_SECURITY_REG_0_CH_12_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_12_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_12_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_12_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_12_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_12_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_12_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_11_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(11)
#define APBDMA_SECURITY_REG_0_CH_11_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_11_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_11_SECURITY_EN_RANGE                   11:11
#define APBDMA_SECURITY_REG_0_CH_11_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_11_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_11_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_11_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_11_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_11_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_11_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_10_SECURITY_EN_SHIFT                   _MK_SHIFT_CONST(10)
#define APBDMA_SECURITY_REG_0_CH_10_SECURITY_EN_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_10_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_10_SECURITY_EN_RANGE                   10:10
#define APBDMA_SECURITY_REG_0_CH_10_SECURITY_EN_WOFFSET                 0x0
#define APBDMA_SECURITY_REG_0_CH_10_SECURITY_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_10_SECURITY_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_10_SECURITY_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_10_SECURITY_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_10_SECURITY_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_10_SECURITY_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_9_SECURITY_EN_SHIFT                    _MK_SHIFT_CONST(9)
#define APBDMA_SECURITY_REG_0_CH_9_SECURITY_EN_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_9_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_9_SECURITY_EN_RANGE                    9:9
#define APBDMA_SECURITY_REG_0_CH_9_SECURITY_EN_WOFFSET                  0x0
#define APBDMA_SECURITY_REG_0_CH_9_SECURITY_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_9_SECURITY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_9_SECURITY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_9_SECURITY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_9_SECURITY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_9_SECURITY_EN_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_8_SECURITY_EN_SHIFT                    _MK_SHIFT_CONST(8)
#define APBDMA_SECURITY_REG_0_CH_8_SECURITY_EN_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_8_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_8_SECURITY_EN_RANGE                    8:8
#define APBDMA_SECURITY_REG_0_CH_8_SECURITY_EN_WOFFSET                  0x0
#define APBDMA_SECURITY_REG_0_CH_8_SECURITY_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_8_SECURITY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_8_SECURITY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_8_SECURITY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_8_SECURITY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_8_SECURITY_EN_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_7_SECURITY_EN_SHIFT                    _MK_SHIFT_CONST(7)
#define APBDMA_SECURITY_REG_0_CH_7_SECURITY_EN_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_7_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_7_SECURITY_EN_RANGE                    7:7
#define APBDMA_SECURITY_REG_0_CH_7_SECURITY_EN_WOFFSET                  0x0
#define APBDMA_SECURITY_REG_0_CH_7_SECURITY_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_7_SECURITY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_7_SECURITY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_7_SECURITY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_7_SECURITY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_7_SECURITY_EN_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_6_SECURITY_EN_SHIFT                    _MK_SHIFT_CONST(6)
#define APBDMA_SECURITY_REG_0_CH_6_SECURITY_EN_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_6_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_6_SECURITY_EN_RANGE                    6:6
#define APBDMA_SECURITY_REG_0_CH_6_SECURITY_EN_WOFFSET                  0x0
#define APBDMA_SECURITY_REG_0_CH_6_SECURITY_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_6_SECURITY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_6_SECURITY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_6_SECURITY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_6_SECURITY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_6_SECURITY_EN_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_5_SECURITY_EN_SHIFT                    _MK_SHIFT_CONST(5)
#define APBDMA_SECURITY_REG_0_CH_5_SECURITY_EN_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_5_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_5_SECURITY_EN_RANGE                    5:5
#define APBDMA_SECURITY_REG_0_CH_5_SECURITY_EN_WOFFSET                  0x0
#define APBDMA_SECURITY_REG_0_CH_5_SECURITY_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_5_SECURITY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_5_SECURITY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_5_SECURITY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_5_SECURITY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_5_SECURITY_EN_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_4_SECURITY_EN_SHIFT                    _MK_SHIFT_CONST(4)
#define APBDMA_SECURITY_REG_0_CH_4_SECURITY_EN_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_4_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_4_SECURITY_EN_RANGE                    4:4
#define APBDMA_SECURITY_REG_0_CH_4_SECURITY_EN_WOFFSET                  0x0
#define APBDMA_SECURITY_REG_0_CH_4_SECURITY_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_4_SECURITY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_4_SECURITY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_4_SECURITY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_4_SECURITY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_4_SECURITY_EN_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_3_SECURITY_EN_SHIFT                    _MK_SHIFT_CONST(3)
#define APBDMA_SECURITY_REG_0_CH_3_SECURITY_EN_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_3_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_3_SECURITY_EN_RANGE                    3:3
#define APBDMA_SECURITY_REG_0_CH_3_SECURITY_EN_WOFFSET                  0x0
#define APBDMA_SECURITY_REG_0_CH_3_SECURITY_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_3_SECURITY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_3_SECURITY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_3_SECURITY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_3_SECURITY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_3_SECURITY_EN_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_2_SECURITY_EN_SHIFT                    _MK_SHIFT_CONST(2)
#define APBDMA_SECURITY_REG_0_CH_2_SECURITY_EN_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_2_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_2_SECURITY_EN_RANGE                    2:2
#define APBDMA_SECURITY_REG_0_CH_2_SECURITY_EN_WOFFSET                  0x0
#define APBDMA_SECURITY_REG_0_CH_2_SECURITY_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_2_SECURITY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_2_SECURITY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_2_SECURITY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_2_SECURITY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_2_SECURITY_EN_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_1_SECURITY_EN_SHIFT                    _MK_SHIFT_CONST(1)
#define APBDMA_SECURITY_REG_0_CH_1_SECURITY_EN_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_1_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_1_SECURITY_EN_RANGE                    1:1
#define APBDMA_SECURITY_REG_0_CH_1_SECURITY_EN_WOFFSET                  0x0
#define APBDMA_SECURITY_REG_0_CH_1_SECURITY_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_1_SECURITY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_1_SECURITY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_1_SECURITY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_1_SECURITY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_1_SECURITY_EN_ENABLE                   _MK_ENUM_CONST(1)

#define APBDMA_SECURITY_REG_0_CH_0_SECURITY_EN_SHIFT                    _MK_SHIFT_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_0_SECURITY_EN_FIELD                    _MK_FIELD_CONST(0x1, APBDMA_SECURITY_REG_0_CH_0_SECURITY_EN_SHIFT)
#define APBDMA_SECURITY_REG_0_CH_0_SECURITY_EN_RANGE                    0:0
#define APBDMA_SECURITY_REG_0_CH_0_SECURITY_EN_WOFFSET                  0x0
#define APBDMA_SECURITY_REG_0_CH_0_SECURITY_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_0_SECURITY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APBDMA_SECURITY_REG_0_CH_0_SECURITY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_0_SECURITY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_SECURITY_REG_0_CH_0_SECURITY_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APBDMA_SECURITY_REG_0_CH_0_SECURITY_EN_ENABLE                   _MK_ENUM_CONST(1)


// Register APBDMA_CHANNEL_SWID_0
#define APBDMA_CHANNEL_SWID_0                   _MK_ADDR_CONST(0x3c)
#define APBDMA_CHANNEL_SWID_0_SECURE                    0x0
#define APBDMA_CHANNEL_SWID_0_SCR                       0
#define APBDMA_CHANNEL_SWID_0_WORD_COUNT                        0x1
#define APBDMA_CHANNEL_SWID_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHANNEL_SWID_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHANNEL_SWID_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHANNEL_SWID_0_CH_31_SWID_SHIFT                  _MK_SHIFT_CONST(31)
#define APBDMA_CHANNEL_SWID_0_CH_31_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_31_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_31_SWID_RANGE                  31:31
#define APBDMA_CHANNEL_SWID_0_CH_31_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_31_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_31_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_31_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_31_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_30_SWID_SHIFT                  _MK_SHIFT_CONST(30)
#define APBDMA_CHANNEL_SWID_0_CH_30_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_30_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_30_SWID_RANGE                  30:30
#define APBDMA_CHANNEL_SWID_0_CH_30_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_30_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_30_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_30_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_30_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_29_SWID_SHIFT                  _MK_SHIFT_CONST(29)
#define APBDMA_CHANNEL_SWID_0_CH_29_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_29_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_29_SWID_RANGE                  29:29
#define APBDMA_CHANNEL_SWID_0_CH_29_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_29_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_29_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_29_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_29_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_28_SWID_SHIFT                  _MK_SHIFT_CONST(28)
#define APBDMA_CHANNEL_SWID_0_CH_28_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_28_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_28_SWID_RANGE                  28:28
#define APBDMA_CHANNEL_SWID_0_CH_28_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_28_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_28_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_28_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_28_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_27_SWID_SHIFT                  _MK_SHIFT_CONST(27)
#define APBDMA_CHANNEL_SWID_0_CH_27_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_27_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_27_SWID_RANGE                  27:27
#define APBDMA_CHANNEL_SWID_0_CH_27_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_27_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_27_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_27_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_27_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_26_SWID_SHIFT                  _MK_SHIFT_CONST(26)
#define APBDMA_CHANNEL_SWID_0_CH_26_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_26_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_26_SWID_RANGE                  26:26
#define APBDMA_CHANNEL_SWID_0_CH_26_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_26_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_26_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_26_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_26_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_25_SWID_SHIFT                  _MK_SHIFT_CONST(25)
#define APBDMA_CHANNEL_SWID_0_CH_25_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_25_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_25_SWID_RANGE                  25:25
#define APBDMA_CHANNEL_SWID_0_CH_25_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_25_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_25_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_25_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_25_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_24_SWID_SHIFT                  _MK_SHIFT_CONST(24)
#define APBDMA_CHANNEL_SWID_0_CH_24_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_24_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_24_SWID_RANGE                  24:24
#define APBDMA_CHANNEL_SWID_0_CH_24_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_24_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_24_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_24_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_24_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_23_SWID_SHIFT                  _MK_SHIFT_CONST(23)
#define APBDMA_CHANNEL_SWID_0_CH_23_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_23_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_23_SWID_RANGE                  23:23
#define APBDMA_CHANNEL_SWID_0_CH_23_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_23_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_23_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_23_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_23_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_22_SWID_SHIFT                  _MK_SHIFT_CONST(22)
#define APBDMA_CHANNEL_SWID_0_CH_22_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_22_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_22_SWID_RANGE                  22:22
#define APBDMA_CHANNEL_SWID_0_CH_22_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_22_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_22_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_22_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_22_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_21_SWID_SHIFT                  _MK_SHIFT_CONST(21)
#define APBDMA_CHANNEL_SWID_0_CH_21_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_21_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_21_SWID_RANGE                  21:21
#define APBDMA_CHANNEL_SWID_0_CH_21_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_21_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_21_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_21_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_21_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_20_SWID_SHIFT                  _MK_SHIFT_CONST(20)
#define APBDMA_CHANNEL_SWID_0_CH_20_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_20_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_20_SWID_RANGE                  20:20
#define APBDMA_CHANNEL_SWID_0_CH_20_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_20_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_20_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_20_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_20_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_19_SWID_SHIFT                  _MK_SHIFT_CONST(19)
#define APBDMA_CHANNEL_SWID_0_CH_19_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_19_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_19_SWID_RANGE                  19:19
#define APBDMA_CHANNEL_SWID_0_CH_19_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_19_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_19_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_19_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_19_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_18_SWID_SHIFT                  _MK_SHIFT_CONST(18)
#define APBDMA_CHANNEL_SWID_0_CH_18_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_18_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_18_SWID_RANGE                  18:18
#define APBDMA_CHANNEL_SWID_0_CH_18_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_18_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_18_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_18_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_18_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_17_SWID_SHIFT                  _MK_SHIFT_CONST(17)
#define APBDMA_CHANNEL_SWID_0_CH_17_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_17_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_17_SWID_RANGE                  17:17
#define APBDMA_CHANNEL_SWID_0_CH_17_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_17_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_17_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_17_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_17_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_16_SWID_SHIFT                  _MK_SHIFT_CONST(16)
#define APBDMA_CHANNEL_SWID_0_CH_16_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_16_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_16_SWID_RANGE                  16:16
#define APBDMA_CHANNEL_SWID_0_CH_16_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_16_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_16_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_16_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_16_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_15_SWID_SHIFT                  _MK_SHIFT_CONST(15)
#define APBDMA_CHANNEL_SWID_0_CH_15_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_15_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_15_SWID_RANGE                  15:15
#define APBDMA_CHANNEL_SWID_0_CH_15_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_15_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_15_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_15_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_15_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_14_SWID_SHIFT                  _MK_SHIFT_CONST(14)
#define APBDMA_CHANNEL_SWID_0_CH_14_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_14_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_14_SWID_RANGE                  14:14
#define APBDMA_CHANNEL_SWID_0_CH_14_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_14_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_14_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_14_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_14_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_13_SWID_SHIFT                  _MK_SHIFT_CONST(13)
#define APBDMA_CHANNEL_SWID_0_CH_13_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_13_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_13_SWID_RANGE                  13:13
#define APBDMA_CHANNEL_SWID_0_CH_13_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_13_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_13_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_13_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_13_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_12_SWID_SHIFT                  _MK_SHIFT_CONST(12)
#define APBDMA_CHANNEL_SWID_0_CH_12_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_12_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_12_SWID_RANGE                  12:12
#define APBDMA_CHANNEL_SWID_0_CH_12_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_12_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_12_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_12_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_12_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_11_SWID_SHIFT                  _MK_SHIFT_CONST(11)
#define APBDMA_CHANNEL_SWID_0_CH_11_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_11_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_11_SWID_RANGE                  11:11
#define APBDMA_CHANNEL_SWID_0_CH_11_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_11_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_11_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_11_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_11_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_10_SWID_SHIFT                  _MK_SHIFT_CONST(10)
#define APBDMA_CHANNEL_SWID_0_CH_10_SWID_FIELD                  _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_10_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_10_SWID_RANGE                  10:10
#define APBDMA_CHANNEL_SWID_0_CH_10_SWID_WOFFSET                        0x0
#define APBDMA_CHANNEL_SWID_0_CH_10_SWID_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_10_SWID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_10_SWID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_10_SWID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_9_SWID_SHIFT                   _MK_SHIFT_CONST(9)
#define APBDMA_CHANNEL_SWID_0_CH_9_SWID_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_9_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_9_SWID_RANGE                   9:9
#define APBDMA_CHANNEL_SWID_0_CH_9_SWID_WOFFSET                 0x0
#define APBDMA_CHANNEL_SWID_0_CH_9_SWID_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_9_SWID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_9_SWID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_9_SWID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_8_SWID_SHIFT                   _MK_SHIFT_CONST(8)
#define APBDMA_CHANNEL_SWID_0_CH_8_SWID_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_8_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_8_SWID_RANGE                   8:8
#define APBDMA_CHANNEL_SWID_0_CH_8_SWID_WOFFSET                 0x0
#define APBDMA_CHANNEL_SWID_0_CH_8_SWID_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_8_SWID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_8_SWID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_8_SWID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_7_SWID_SHIFT                   _MK_SHIFT_CONST(7)
#define APBDMA_CHANNEL_SWID_0_CH_7_SWID_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_7_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_7_SWID_RANGE                   7:7
#define APBDMA_CHANNEL_SWID_0_CH_7_SWID_WOFFSET                 0x0
#define APBDMA_CHANNEL_SWID_0_CH_7_SWID_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_7_SWID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_7_SWID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_7_SWID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_6_SWID_SHIFT                   _MK_SHIFT_CONST(6)
#define APBDMA_CHANNEL_SWID_0_CH_6_SWID_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_6_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_6_SWID_RANGE                   6:6
#define APBDMA_CHANNEL_SWID_0_CH_6_SWID_WOFFSET                 0x0
#define APBDMA_CHANNEL_SWID_0_CH_6_SWID_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_6_SWID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_6_SWID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_6_SWID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_5_SWID_SHIFT                   _MK_SHIFT_CONST(5)
#define APBDMA_CHANNEL_SWID_0_CH_5_SWID_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_5_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_5_SWID_RANGE                   5:5
#define APBDMA_CHANNEL_SWID_0_CH_5_SWID_WOFFSET                 0x0
#define APBDMA_CHANNEL_SWID_0_CH_5_SWID_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_5_SWID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_5_SWID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_5_SWID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_4_SWID_SHIFT                   _MK_SHIFT_CONST(4)
#define APBDMA_CHANNEL_SWID_0_CH_4_SWID_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_4_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_4_SWID_RANGE                   4:4
#define APBDMA_CHANNEL_SWID_0_CH_4_SWID_WOFFSET                 0x0
#define APBDMA_CHANNEL_SWID_0_CH_4_SWID_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_4_SWID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_4_SWID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_4_SWID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_3_SWID_SHIFT                   _MK_SHIFT_CONST(3)
#define APBDMA_CHANNEL_SWID_0_CH_3_SWID_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_3_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_3_SWID_RANGE                   3:3
#define APBDMA_CHANNEL_SWID_0_CH_3_SWID_WOFFSET                 0x0
#define APBDMA_CHANNEL_SWID_0_CH_3_SWID_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_3_SWID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_3_SWID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_3_SWID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_2_SWID_SHIFT                   _MK_SHIFT_CONST(2)
#define APBDMA_CHANNEL_SWID_0_CH_2_SWID_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_2_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_2_SWID_RANGE                   2:2
#define APBDMA_CHANNEL_SWID_0_CH_2_SWID_WOFFSET                 0x0
#define APBDMA_CHANNEL_SWID_0_CH_2_SWID_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_2_SWID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_2_SWID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_2_SWID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_1_SWID_SHIFT                   _MK_SHIFT_CONST(1)
#define APBDMA_CHANNEL_SWID_0_CH_1_SWID_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_1_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_1_SWID_RANGE                   1:1
#define APBDMA_CHANNEL_SWID_0_CH_1_SWID_WOFFSET                 0x0
#define APBDMA_CHANNEL_SWID_0_CH_1_SWID_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_1_SWID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_1_SWID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_1_SWID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID_0_CH_0_SWID_SHIFT                   _MK_SHIFT_CONST(0)
#define APBDMA_CHANNEL_SWID_0_CH_0_SWID_FIELD                   _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID_0_CH_0_SWID_SHIFT)
#define APBDMA_CHANNEL_SWID_0_CH_0_SWID_RANGE                   0:0
#define APBDMA_CHANNEL_SWID_0_CH_0_SWID_WOFFSET                 0x0
#define APBDMA_CHANNEL_SWID_0_CH_0_SWID_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_0_SWID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID_0_CH_0_SWID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID_0_CH_0_SWID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register APBDMA_SPARE_0
#define APBDMA_SPARE_0                  _MK_ADDR_CONST(0x40)
#define APBDMA_SPARE_0_SECURE                   0x0
#define APBDMA_SPARE_0_SCR                      0
#define APBDMA_SPARE_0_WORD_COUNT                       0x1
#define APBDMA_SPARE_0_RESET_VAL                        _MK_MASK_CONST(0xffff0000)
#define APBDMA_SPARE_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define APBDMA_SPARE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APBDMA_SPARE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_SPARE_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_SPARE_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define APBDMA_SPARE_0_SPARE_HIGH_SHIFT                 _MK_SHIFT_CONST(16)
#define APBDMA_SPARE_0_SPARE_HIGH_FIELD                 _MK_FIELD_CONST(0xffff, APBDMA_SPARE_0_SPARE_HIGH_SHIFT)
#define APBDMA_SPARE_0_SPARE_HIGH_RANGE                 31:16
#define APBDMA_SPARE_0_SPARE_HIGH_WOFFSET                       0x0
#define APBDMA_SPARE_0_SPARE_HIGH_DEFAULT                       _MK_MASK_CONST(0xffff)
#define APBDMA_SPARE_0_SPARE_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define APBDMA_SPARE_0_SPARE_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APBDMA_SPARE_0_SPARE_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APBDMA_SPARE_0_SPARE_LOW_SHIFT                  _MK_SHIFT_CONST(0)
#define APBDMA_SPARE_0_SPARE_LOW_FIELD                  _MK_FIELD_CONST(0xffff, APBDMA_SPARE_0_SPARE_LOW_SHIFT)
#define APBDMA_SPARE_0_SPARE_LOW_RANGE                  15:0
#define APBDMA_SPARE_0_SPARE_LOW_WOFFSET                        0x0
#define APBDMA_SPARE_0_SPARE_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_SPARE_0_SPARE_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define APBDMA_SPARE_0_SPARE_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_SPARE_0_SPARE_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register APBDMA_CHAN_WT_REG0_0
#define APBDMA_CHAN_WT_REG0_0                   _MK_ADDR_CONST(0x44)
#define APBDMA_CHAN_WT_REG0_0_SECURE                    0x0
#define APBDMA_CHAN_WT_REG0_0_SCR                       0
#define APBDMA_CHAN_WT_REG0_0_WORD_COUNT                        0x1
#define APBDMA_CHAN_WT_REG0_0_RESET_VAL                         _MK_MASK_CONST(0x11111111)
#define APBDMA_CHAN_WT_REG0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG0_0_WT_CH31_SHIFT                     _MK_SHIFT_CONST(28)
#define APBDMA_CHAN_WT_REG0_0_WT_CH31_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG0_0_WT_CH31_SHIFT)
#define APBDMA_CHAN_WT_REG0_0_WT_CH31_RANGE                     31:28
#define APBDMA_CHAN_WT_REG0_0_WT_CH31_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG0_0_WT_CH31_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG0_0_WT_CH31_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG0_0_WT_CH31_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG0_0_WT_CH31_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG0_0_WT_CH30_SHIFT                     _MK_SHIFT_CONST(24)
#define APBDMA_CHAN_WT_REG0_0_WT_CH30_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG0_0_WT_CH30_SHIFT)
#define APBDMA_CHAN_WT_REG0_0_WT_CH30_RANGE                     27:24
#define APBDMA_CHAN_WT_REG0_0_WT_CH30_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG0_0_WT_CH30_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG0_0_WT_CH30_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG0_0_WT_CH30_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG0_0_WT_CH30_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG0_0_WT_CH29_SHIFT                     _MK_SHIFT_CONST(20)
#define APBDMA_CHAN_WT_REG0_0_WT_CH29_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG0_0_WT_CH29_SHIFT)
#define APBDMA_CHAN_WT_REG0_0_WT_CH29_RANGE                     23:20
#define APBDMA_CHAN_WT_REG0_0_WT_CH29_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG0_0_WT_CH29_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG0_0_WT_CH29_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG0_0_WT_CH29_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG0_0_WT_CH29_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG0_0_WT_CH28_SHIFT                     _MK_SHIFT_CONST(16)
#define APBDMA_CHAN_WT_REG0_0_WT_CH28_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG0_0_WT_CH28_SHIFT)
#define APBDMA_CHAN_WT_REG0_0_WT_CH28_RANGE                     19:16
#define APBDMA_CHAN_WT_REG0_0_WT_CH28_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG0_0_WT_CH28_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG0_0_WT_CH28_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG0_0_WT_CH28_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG0_0_WT_CH28_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG0_0_WT_CH27_SHIFT                     _MK_SHIFT_CONST(12)
#define APBDMA_CHAN_WT_REG0_0_WT_CH27_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG0_0_WT_CH27_SHIFT)
#define APBDMA_CHAN_WT_REG0_0_WT_CH27_RANGE                     15:12
#define APBDMA_CHAN_WT_REG0_0_WT_CH27_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG0_0_WT_CH27_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG0_0_WT_CH27_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG0_0_WT_CH27_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG0_0_WT_CH27_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG0_0_WT_CH26_SHIFT                     _MK_SHIFT_CONST(8)
#define APBDMA_CHAN_WT_REG0_0_WT_CH26_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG0_0_WT_CH26_SHIFT)
#define APBDMA_CHAN_WT_REG0_0_WT_CH26_RANGE                     11:8
#define APBDMA_CHAN_WT_REG0_0_WT_CH26_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG0_0_WT_CH26_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG0_0_WT_CH26_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG0_0_WT_CH26_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG0_0_WT_CH26_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG0_0_WT_CH25_SHIFT                     _MK_SHIFT_CONST(4)
#define APBDMA_CHAN_WT_REG0_0_WT_CH25_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG0_0_WT_CH25_SHIFT)
#define APBDMA_CHAN_WT_REG0_0_WT_CH25_RANGE                     7:4
#define APBDMA_CHAN_WT_REG0_0_WT_CH25_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG0_0_WT_CH25_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG0_0_WT_CH25_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG0_0_WT_CH25_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG0_0_WT_CH25_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG0_0_WT_CH24_SHIFT                     _MK_SHIFT_CONST(0)
#define APBDMA_CHAN_WT_REG0_0_WT_CH24_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG0_0_WT_CH24_SHIFT)
#define APBDMA_CHAN_WT_REG0_0_WT_CH24_RANGE                     3:0
#define APBDMA_CHAN_WT_REG0_0_WT_CH24_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG0_0_WT_CH24_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG0_0_WT_CH24_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG0_0_WT_CH24_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG0_0_WT_CH24_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APBDMA_CHAN_WT_REG1_0
#define APBDMA_CHAN_WT_REG1_0                   _MK_ADDR_CONST(0x48)
#define APBDMA_CHAN_WT_REG1_0_SECURE                    0x0
#define APBDMA_CHAN_WT_REG1_0_SCR                       0
#define APBDMA_CHAN_WT_REG1_0_WORD_COUNT                        0x1
#define APBDMA_CHAN_WT_REG1_0_RESET_VAL                         _MK_MASK_CONST(0x11111111)
#define APBDMA_CHAN_WT_REG1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG1_0_WT_CH23_SHIFT                     _MK_SHIFT_CONST(28)
#define APBDMA_CHAN_WT_REG1_0_WT_CH23_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG1_0_WT_CH23_SHIFT)
#define APBDMA_CHAN_WT_REG1_0_WT_CH23_RANGE                     31:28
#define APBDMA_CHAN_WT_REG1_0_WT_CH23_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG1_0_WT_CH23_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG1_0_WT_CH23_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG1_0_WT_CH23_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG1_0_WT_CH23_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG1_0_WT_CH22_SHIFT                     _MK_SHIFT_CONST(24)
#define APBDMA_CHAN_WT_REG1_0_WT_CH22_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG1_0_WT_CH22_SHIFT)
#define APBDMA_CHAN_WT_REG1_0_WT_CH22_RANGE                     27:24
#define APBDMA_CHAN_WT_REG1_0_WT_CH22_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG1_0_WT_CH22_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG1_0_WT_CH22_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG1_0_WT_CH22_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG1_0_WT_CH22_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG1_0_WT_CH21_SHIFT                     _MK_SHIFT_CONST(20)
#define APBDMA_CHAN_WT_REG1_0_WT_CH21_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG1_0_WT_CH21_SHIFT)
#define APBDMA_CHAN_WT_REG1_0_WT_CH21_RANGE                     23:20
#define APBDMA_CHAN_WT_REG1_0_WT_CH21_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG1_0_WT_CH21_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG1_0_WT_CH21_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG1_0_WT_CH21_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG1_0_WT_CH21_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG1_0_WT_CH20_SHIFT                     _MK_SHIFT_CONST(16)
#define APBDMA_CHAN_WT_REG1_0_WT_CH20_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG1_0_WT_CH20_SHIFT)
#define APBDMA_CHAN_WT_REG1_0_WT_CH20_RANGE                     19:16
#define APBDMA_CHAN_WT_REG1_0_WT_CH20_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG1_0_WT_CH20_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG1_0_WT_CH20_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG1_0_WT_CH20_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG1_0_WT_CH20_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG1_0_WT_CH19_SHIFT                     _MK_SHIFT_CONST(12)
#define APBDMA_CHAN_WT_REG1_0_WT_CH19_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG1_0_WT_CH19_SHIFT)
#define APBDMA_CHAN_WT_REG1_0_WT_CH19_RANGE                     15:12
#define APBDMA_CHAN_WT_REG1_0_WT_CH19_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG1_0_WT_CH19_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG1_0_WT_CH19_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG1_0_WT_CH19_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG1_0_WT_CH19_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG1_0_WT_CH18_SHIFT                     _MK_SHIFT_CONST(8)
#define APBDMA_CHAN_WT_REG1_0_WT_CH18_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG1_0_WT_CH18_SHIFT)
#define APBDMA_CHAN_WT_REG1_0_WT_CH18_RANGE                     11:8
#define APBDMA_CHAN_WT_REG1_0_WT_CH18_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG1_0_WT_CH18_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG1_0_WT_CH18_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG1_0_WT_CH18_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG1_0_WT_CH18_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG1_0_WT_CH17_SHIFT                     _MK_SHIFT_CONST(4)
#define APBDMA_CHAN_WT_REG1_0_WT_CH17_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG1_0_WT_CH17_SHIFT)
#define APBDMA_CHAN_WT_REG1_0_WT_CH17_RANGE                     7:4
#define APBDMA_CHAN_WT_REG1_0_WT_CH17_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG1_0_WT_CH17_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG1_0_WT_CH17_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG1_0_WT_CH17_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG1_0_WT_CH17_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG1_0_WT_CH16_SHIFT                     _MK_SHIFT_CONST(0)
#define APBDMA_CHAN_WT_REG1_0_WT_CH16_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG1_0_WT_CH16_SHIFT)
#define APBDMA_CHAN_WT_REG1_0_WT_CH16_RANGE                     3:0
#define APBDMA_CHAN_WT_REG1_0_WT_CH16_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG1_0_WT_CH16_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG1_0_WT_CH16_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG1_0_WT_CH16_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG1_0_WT_CH16_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APBDMA_CHAN_WT_REG2_0
#define APBDMA_CHAN_WT_REG2_0                   _MK_ADDR_CONST(0x4c)
#define APBDMA_CHAN_WT_REG2_0_SECURE                    0x0
#define APBDMA_CHAN_WT_REG2_0_SCR                       0
#define APBDMA_CHAN_WT_REG2_0_WORD_COUNT                        0x1
#define APBDMA_CHAN_WT_REG2_0_RESET_VAL                         _MK_MASK_CONST(0x11111111)
#define APBDMA_CHAN_WT_REG2_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG2_0_WT_CH15_SHIFT                     _MK_SHIFT_CONST(28)
#define APBDMA_CHAN_WT_REG2_0_WT_CH15_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG2_0_WT_CH15_SHIFT)
#define APBDMA_CHAN_WT_REG2_0_WT_CH15_RANGE                     31:28
#define APBDMA_CHAN_WT_REG2_0_WT_CH15_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG2_0_WT_CH15_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG2_0_WT_CH15_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG2_0_WT_CH15_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG2_0_WT_CH15_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG2_0_WT_CH14_SHIFT                     _MK_SHIFT_CONST(24)
#define APBDMA_CHAN_WT_REG2_0_WT_CH14_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG2_0_WT_CH14_SHIFT)
#define APBDMA_CHAN_WT_REG2_0_WT_CH14_RANGE                     27:24
#define APBDMA_CHAN_WT_REG2_0_WT_CH14_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG2_0_WT_CH14_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG2_0_WT_CH14_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG2_0_WT_CH14_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG2_0_WT_CH14_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG2_0_WT_CH13_SHIFT                     _MK_SHIFT_CONST(20)
#define APBDMA_CHAN_WT_REG2_0_WT_CH13_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG2_0_WT_CH13_SHIFT)
#define APBDMA_CHAN_WT_REG2_0_WT_CH13_RANGE                     23:20
#define APBDMA_CHAN_WT_REG2_0_WT_CH13_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG2_0_WT_CH13_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG2_0_WT_CH13_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG2_0_WT_CH13_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG2_0_WT_CH13_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG2_0_WT_CH12_SHIFT                     _MK_SHIFT_CONST(16)
#define APBDMA_CHAN_WT_REG2_0_WT_CH12_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG2_0_WT_CH12_SHIFT)
#define APBDMA_CHAN_WT_REG2_0_WT_CH12_RANGE                     19:16
#define APBDMA_CHAN_WT_REG2_0_WT_CH12_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG2_0_WT_CH12_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG2_0_WT_CH12_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG2_0_WT_CH12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG2_0_WT_CH12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG2_0_WT_CH11_SHIFT                     _MK_SHIFT_CONST(12)
#define APBDMA_CHAN_WT_REG2_0_WT_CH11_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG2_0_WT_CH11_SHIFT)
#define APBDMA_CHAN_WT_REG2_0_WT_CH11_RANGE                     15:12
#define APBDMA_CHAN_WT_REG2_0_WT_CH11_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG2_0_WT_CH11_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG2_0_WT_CH11_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG2_0_WT_CH11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG2_0_WT_CH11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG2_0_WT_CH10_SHIFT                     _MK_SHIFT_CONST(8)
#define APBDMA_CHAN_WT_REG2_0_WT_CH10_FIELD                     _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG2_0_WT_CH10_SHIFT)
#define APBDMA_CHAN_WT_REG2_0_WT_CH10_RANGE                     11:8
#define APBDMA_CHAN_WT_REG2_0_WT_CH10_WOFFSET                   0x0
#define APBDMA_CHAN_WT_REG2_0_WT_CH10_DEFAULT                   _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG2_0_WT_CH10_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG2_0_WT_CH10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG2_0_WT_CH10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG2_0_WT_CH9_SHIFT                      _MK_SHIFT_CONST(4)
#define APBDMA_CHAN_WT_REG2_0_WT_CH9_FIELD                      _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG2_0_WT_CH9_SHIFT)
#define APBDMA_CHAN_WT_REG2_0_WT_CH9_RANGE                      7:4
#define APBDMA_CHAN_WT_REG2_0_WT_CH9_WOFFSET                    0x0
#define APBDMA_CHAN_WT_REG2_0_WT_CH9_DEFAULT                    _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG2_0_WT_CH9_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG2_0_WT_CH9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG2_0_WT_CH9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG2_0_WT_CH8_SHIFT                      _MK_SHIFT_CONST(0)
#define APBDMA_CHAN_WT_REG2_0_WT_CH8_FIELD                      _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG2_0_WT_CH8_SHIFT)
#define APBDMA_CHAN_WT_REG2_0_WT_CH8_RANGE                      3:0
#define APBDMA_CHAN_WT_REG2_0_WT_CH8_WOFFSET                    0x0
#define APBDMA_CHAN_WT_REG2_0_WT_CH8_DEFAULT                    _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG2_0_WT_CH8_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG2_0_WT_CH8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG2_0_WT_CH8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register APBDMA_CHAN_WT_REG3_0
#define APBDMA_CHAN_WT_REG3_0                   _MK_ADDR_CONST(0x50)
#define APBDMA_CHAN_WT_REG3_0_SECURE                    0x0
#define APBDMA_CHAN_WT_REG3_0_SCR                       0
#define APBDMA_CHAN_WT_REG3_0_WORD_COUNT                        0x1
#define APBDMA_CHAN_WT_REG3_0_RESET_VAL                         _MK_MASK_CONST(0x11111111)
#define APBDMA_CHAN_WT_REG3_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHAN_WT_REG3_0_WT_CH7_SHIFT                      _MK_SHIFT_CONST(28)
#define APBDMA_CHAN_WT_REG3_0_WT_CH7_FIELD                      _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG3_0_WT_CH7_SHIFT)
#define APBDMA_CHAN_WT_REG3_0_WT_CH7_RANGE                      31:28
#define APBDMA_CHAN_WT_REG3_0_WT_CH7_WOFFSET                    0x0
#define APBDMA_CHAN_WT_REG3_0_WT_CH7_DEFAULT                    _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG3_0_WT_CH7_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG3_0_WT_CH7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG3_0_WT_CH7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG3_0_WT_CH6_SHIFT                      _MK_SHIFT_CONST(24)
#define APBDMA_CHAN_WT_REG3_0_WT_CH6_FIELD                      _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG3_0_WT_CH6_SHIFT)
#define APBDMA_CHAN_WT_REG3_0_WT_CH6_RANGE                      27:24
#define APBDMA_CHAN_WT_REG3_0_WT_CH6_WOFFSET                    0x0
#define APBDMA_CHAN_WT_REG3_0_WT_CH6_DEFAULT                    _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG3_0_WT_CH6_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG3_0_WT_CH6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG3_0_WT_CH6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG3_0_WT_CH5_SHIFT                      _MK_SHIFT_CONST(20)
#define APBDMA_CHAN_WT_REG3_0_WT_CH5_FIELD                      _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG3_0_WT_CH5_SHIFT)
#define APBDMA_CHAN_WT_REG3_0_WT_CH5_RANGE                      23:20
#define APBDMA_CHAN_WT_REG3_0_WT_CH5_WOFFSET                    0x0
#define APBDMA_CHAN_WT_REG3_0_WT_CH5_DEFAULT                    _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG3_0_WT_CH5_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG3_0_WT_CH5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG3_0_WT_CH5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG3_0_WT_CH4_SHIFT                      _MK_SHIFT_CONST(16)
#define APBDMA_CHAN_WT_REG3_0_WT_CH4_FIELD                      _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG3_0_WT_CH4_SHIFT)
#define APBDMA_CHAN_WT_REG3_0_WT_CH4_RANGE                      19:16
#define APBDMA_CHAN_WT_REG3_0_WT_CH4_WOFFSET                    0x0
#define APBDMA_CHAN_WT_REG3_0_WT_CH4_DEFAULT                    _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG3_0_WT_CH4_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG3_0_WT_CH4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG3_0_WT_CH4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG3_0_WT_CH3_SHIFT                      _MK_SHIFT_CONST(12)
#define APBDMA_CHAN_WT_REG3_0_WT_CH3_FIELD                      _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG3_0_WT_CH3_SHIFT)
#define APBDMA_CHAN_WT_REG3_0_WT_CH3_RANGE                      15:12
#define APBDMA_CHAN_WT_REG3_0_WT_CH3_WOFFSET                    0x0
#define APBDMA_CHAN_WT_REG3_0_WT_CH3_DEFAULT                    _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG3_0_WT_CH3_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG3_0_WT_CH3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG3_0_WT_CH3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG3_0_WT_CH2_SHIFT                      _MK_SHIFT_CONST(8)
#define APBDMA_CHAN_WT_REG3_0_WT_CH2_FIELD                      _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG3_0_WT_CH2_SHIFT)
#define APBDMA_CHAN_WT_REG3_0_WT_CH2_RANGE                      11:8
#define APBDMA_CHAN_WT_REG3_0_WT_CH2_WOFFSET                    0x0
#define APBDMA_CHAN_WT_REG3_0_WT_CH2_DEFAULT                    _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG3_0_WT_CH2_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG3_0_WT_CH2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG3_0_WT_CH2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG3_0_WT_CH1_SHIFT                      _MK_SHIFT_CONST(4)
#define APBDMA_CHAN_WT_REG3_0_WT_CH1_FIELD                      _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG3_0_WT_CH1_SHIFT)
#define APBDMA_CHAN_WT_REG3_0_WT_CH1_RANGE                      7:4
#define APBDMA_CHAN_WT_REG3_0_WT_CH1_WOFFSET                    0x0
#define APBDMA_CHAN_WT_REG3_0_WT_CH1_DEFAULT                    _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG3_0_WT_CH1_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG3_0_WT_CH1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG3_0_WT_CH1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APBDMA_CHAN_WT_REG3_0_WT_CH0_SHIFT                      _MK_SHIFT_CONST(0)
#define APBDMA_CHAN_WT_REG3_0_WT_CH0_FIELD                      _MK_FIELD_CONST(0xf, APBDMA_CHAN_WT_REG3_0_WT_CH0_SHIFT)
#define APBDMA_CHAN_WT_REG3_0_WT_CH0_RANGE                      3:0
#define APBDMA_CHAN_WT_REG3_0_WT_CH0_WOFFSET                    0x0
#define APBDMA_CHAN_WT_REG3_0_WT_CH0_DEFAULT                    _MK_MASK_CONST(0x1)
#define APBDMA_CHAN_WT_REG3_0_WT_CH0_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APBDMA_CHAN_WT_REG3_0_WT_CH0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APBDMA_CHAN_WT_REG3_0_WT_CH0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register APBDMA_CHANNEL_SWID1_0
#define APBDMA_CHANNEL_SWID1_0                  _MK_ADDR_CONST(0x54)
#define APBDMA_CHANNEL_SWID1_0_SECURE                   0x0
#define APBDMA_CHANNEL_SWID1_0_SCR                      0
#define APBDMA_CHANNEL_SWID1_0_WORD_COUNT                       0x1
#define APBDMA_CHANNEL_SWID1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHANNEL_SWID1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHANNEL_SWID1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define APBDMA_CHANNEL_SWID1_0_CH_31_SWID_1_SHIFT                       _MK_SHIFT_CONST(31)
#define APBDMA_CHANNEL_SWID1_0_CH_31_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_31_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_31_SWID_1_RANGE                       31:31
#define APBDMA_CHANNEL_SWID1_0_CH_31_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_31_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_31_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_31_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_31_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_30_SWID_1_SHIFT                       _MK_SHIFT_CONST(30)
#define APBDMA_CHANNEL_SWID1_0_CH_30_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_30_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_30_SWID_1_RANGE                       30:30
#define APBDMA_CHANNEL_SWID1_0_CH_30_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_30_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_30_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_30_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_30_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_29_SWID_1_SHIFT                       _MK_SHIFT_CONST(29)
#define APBDMA_CHANNEL_SWID1_0_CH_29_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_29_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_29_SWID_1_RANGE                       29:29
#define APBDMA_CHANNEL_SWID1_0_CH_29_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_29_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_29_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_29_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_29_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_28_SWID_1_SHIFT                       _MK_SHIFT_CONST(28)
#define APBDMA_CHANNEL_SWID1_0_CH_28_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_28_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_28_SWID_1_RANGE                       28:28
#define APBDMA_CHANNEL_SWID1_0_CH_28_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_28_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_28_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_28_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_28_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_27_SWID_1_SHIFT                       _MK_SHIFT_CONST(27)
#define APBDMA_CHANNEL_SWID1_0_CH_27_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_27_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_27_SWID_1_RANGE                       27:27
#define APBDMA_CHANNEL_SWID1_0_CH_27_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_27_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_27_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_27_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_27_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_26_SWID_1_SHIFT                       _MK_SHIFT_CONST(26)
#define APBDMA_CHANNEL_SWID1_0_CH_26_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_26_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_26_SWID_1_RANGE                       26:26
#define APBDMA_CHANNEL_SWID1_0_CH_26_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_26_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_26_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_26_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_26_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_25_SWID_1_SHIFT                       _MK_SHIFT_CONST(25)
#define APBDMA_CHANNEL_SWID1_0_CH_25_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_25_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_25_SWID_1_RANGE                       25:25
#define APBDMA_CHANNEL_SWID1_0_CH_25_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_25_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_25_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_25_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_25_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_24_SWID_1_SHIFT                       _MK_SHIFT_CONST(24)
#define APBDMA_CHANNEL_SWID1_0_CH_24_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_24_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_24_SWID_1_RANGE                       24:24
#define APBDMA_CHANNEL_SWID1_0_CH_24_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_24_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_24_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_24_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_24_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_23_SWID_1_SHIFT                       _MK_SHIFT_CONST(23)
#define APBDMA_CHANNEL_SWID1_0_CH_23_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_23_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_23_SWID_1_RANGE                       23:23
#define APBDMA_CHANNEL_SWID1_0_CH_23_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_23_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_23_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_23_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_23_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_22_SWID_1_SHIFT                       _MK_SHIFT_CONST(22)
#define APBDMA_CHANNEL_SWID1_0_CH_22_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_22_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_22_SWID_1_RANGE                       22:22
#define APBDMA_CHANNEL_SWID1_0_CH_22_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_22_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_22_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_22_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_22_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_21_SWID_1_SHIFT                       _MK_SHIFT_CONST(21)
#define APBDMA_CHANNEL_SWID1_0_CH_21_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_21_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_21_SWID_1_RANGE                       21:21
#define APBDMA_CHANNEL_SWID1_0_CH_21_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_21_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_21_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_21_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_21_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_20_SWID_1_SHIFT                       _MK_SHIFT_CONST(20)
#define APBDMA_CHANNEL_SWID1_0_CH_20_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_20_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_20_SWID_1_RANGE                       20:20
#define APBDMA_CHANNEL_SWID1_0_CH_20_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_20_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_20_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_20_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_20_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_19_SWID_1_SHIFT                       _MK_SHIFT_CONST(19)
#define APBDMA_CHANNEL_SWID1_0_CH_19_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_19_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_19_SWID_1_RANGE                       19:19
#define APBDMA_CHANNEL_SWID1_0_CH_19_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_19_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_19_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_19_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_19_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_18_SWID_1_SHIFT                       _MK_SHIFT_CONST(18)
#define APBDMA_CHANNEL_SWID1_0_CH_18_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_18_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_18_SWID_1_RANGE                       18:18
#define APBDMA_CHANNEL_SWID1_0_CH_18_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_18_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_18_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_18_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_18_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_17_SWID_1_SHIFT                       _MK_SHIFT_CONST(17)
#define APBDMA_CHANNEL_SWID1_0_CH_17_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_17_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_17_SWID_1_RANGE                       17:17
#define APBDMA_CHANNEL_SWID1_0_CH_17_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_17_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_17_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_17_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_17_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_16_SWID_1_SHIFT                       _MK_SHIFT_CONST(16)
#define APBDMA_CHANNEL_SWID1_0_CH_16_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_16_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_16_SWID_1_RANGE                       16:16
#define APBDMA_CHANNEL_SWID1_0_CH_16_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_16_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_16_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_16_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_16_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_15_SWID_1_SHIFT                       _MK_SHIFT_CONST(15)
#define APBDMA_CHANNEL_SWID1_0_CH_15_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_15_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_15_SWID_1_RANGE                       15:15
#define APBDMA_CHANNEL_SWID1_0_CH_15_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_15_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_15_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_15_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_15_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_14_SWID_1_SHIFT                       _MK_SHIFT_CONST(14)
#define APBDMA_CHANNEL_SWID1_0_CH_14_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_14_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_14_SWID_1_RANGE                       14:14
#define APBDMA_CHANNEL_SWID1_0_CH_14_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_14_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_14_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_14_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_14_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_13_SWID_1_SHIFT                       _MK_SHIFT_CONST(13)
#define APBDMA_CHANNEL_SWID1_0_CH_13_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_13_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_13_SWID_1_RANGE                       13:13
#define APBDMA_CHANNEL_SWID1_0_CH_13_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_13_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_13_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_13_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_13_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_12_SWID_1_SHIFT                       _MK_SHIFT_CONST(12)
#define APBDMA_CHANNEL_SWID1_0_CH_12_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_12_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_12_SWID_1_RANGE                       12:12
#define APBDMA_CHANNEL_SWID1_0_CH_12_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_12_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_12_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_12_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_12_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_11_SWID_1_SHIFT                       _MK_SHIFT_CONST(11)
#define APBDMA_CHANNEL_SWID1_0_CH_11_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_11_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_11_SWID_1_RANGE                       11:11
#define APBDMA_CHANNEL_SWID1_0_CH_11_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_11_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_11_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_11_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_11_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_10_SWID_1_SHIFT                       _MK_SHIFT_CONST(10)
#define APBDMA_CHANNEL_SWID1_0_CH_10_SWID_1_FIELD                       _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_10_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_10_SWID_1_RANGE                       10:10
#define APBDMA_CHANNEL_SWID1_0_CH_10_SWID_1_WOFFSET                     0x0
#define APBDMA_CHANNEL_SWID1_0_CH_10_SWID_1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_10_SWID_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_10_SWID_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_10_SWID_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_9_SWID_1_SHIFT                        _MK_SHIFT_CONST(9)
#define APBDMA_CHANNEL_SWID1_0_CH_9_SWID_1_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_9_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_9_SWID_1_RANGE                        9:9
#define APBDMA_CHANNEL_SWID1_0_CH_9_SWID_1_WOFFSET                      0x0
#define APBDMA_CHANNEL_SWID1_0_CH_9_SWID_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_9_SWID_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_9_SWID_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_9_SWID_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_8_SWID_1_SHIFT                        _MK_SHIFT_CONST(8)
#define APBDMA_CHANNEL_SWID1_0_CH_8_SWID_1_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_8_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_8_SWID_1_RANGE                        8:8
#define APBDMA_CHANNEL_SWID1_0_CH_8_SWID_1_WOFFSET                      0x0
#define APBDMA_CHANNEL_SWID1_0_CH_8_SWID_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_8_SWID_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_8_SWID_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_8_SWID_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_7_SWID_1_SHIFT                        _MK_SHIFT_CONST(7)
#define APBDMA_CHANNEL_SWID1_0_CH_7_SWID_1_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_7_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_7_SWID_1_RANGE                        7:7
#define APBDMA_CHANNEL_SWID1_0_CH_7_SWID_1_WOFFSET                      0x0
#define APBDMA_CHANNEL_SWID1_0_CH_7_SWID_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_7_SWID_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_7_SWID_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_7_SWID_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_6_SWID_1_SHIFT                        _MK_SHIFT_CONST(6)
#define APBDMA_CHANNEL_SWID1_0_CH_6_SWID_1_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_6_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_6_SWID_1_RANGE                        6:6
#define APBDMA_CHANNEL_SWID1_0_CH_6_SWID_1_WOFFSET                      0x0
#define APBDMA_CHANNEL_SWID1_0_CH_6_SWID_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_6_SWID_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_6_SWID_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_6_SWID_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_5_SWID_1_SHIFT                        _MK_SHIFT_CONST(5)
#define APBDMA_CHANNEL_SWID1_0_CH_5_SWID_1_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_5_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_5_SWID_1_RANGE                        5:5
#define APBDMA_CHANNEL_SWID1_0_CH_5_SWID_1_WOFFSET                      0x0
#define APBDMA_CHANNEL_SWID1_0_CH_5_SWID_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_5_SWID_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_5_SWID_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_5_SWID_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_4_SWID_1_SHIFT                        _MK_SHIFT_CONST(4)
#define APBDMA_CHANNEL_SWID1_0_CH_4_SWID_1_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_4_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_4_SWID_1_RANGE                        4:4
#define APBDMA_CHANNEL_SWID1_0_CH_4_SWID_1_WOFFSET                      0x0
#define APBDMA_CHANNEL_SWID1_0_CH_4_SWID_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_4_SWID_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_4_SWID_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_4_SWID_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_3_SWID_1_SHIFT                        _MK_SHIFT_CONST(3)
#define APBDMA_CHANNEL_SWID1_0_CH_3_SWID_1_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_3_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_3_SWID_1_RANGE                        3:3
#define APBDMA_CHANNEL_SWID1_0_CH_3_SWID_1_WOFFSET                      0x0
#define APBDMA_CHANNEL_SWID1_0_CH_3_SWID_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_3_SWID_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_3_SWID_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_3_SWID_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_2_SWID_1_SHIFT                        _MK_SHIFT_CONST(2)
#define APBDMA_CHANNEL_SWID1_0_CH_2_SWID_1_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_2_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_2_SWID_1_RANGE                        2:2
#define APBDMA_CHANNEL_SWID1_0_CH_2_SWID_1_WOFFSET                      0x0
#define APBDMA_CHANNEL_SWID1_0_CH_2_SWID_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_2_SWID_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_2_SWID_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_2_SWID_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_1_SWID_1_SHIFT                        _MK_SHIFT_CONST(1)
#define APBDMA_CHANNEL_SWID1_0_CH_1_SWID_1_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_1_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_1_SWID_1_RANGE                        1:1
#define APBDMA_CHANNEL_SWID1_0_CH_1_SWID_1_WOFFSET                      0x0
#define APBDMA_CHANNEL_SWID1_0_CH_1_SWID_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_1_SWID_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_1_SWID_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_1_SWID_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APBDMA_CHANNEL_SWID1_0_CH_0_SWID_1_SHIFT                        _MK_SHIFT_CONST(0)
#define APBDMA_CHANNEL_SWID1_0_CH_0_SWID_1_FIELD                        _MK_FIELD_CONST(0x1, APBDMA_CHANNEL_SWID1_0_CH_0_SWID_1_SHIFT)
#define APBDMA_CHANNEL_SWID1_0_CH_0_SWID_1_RANGE                        0:0
#define APBDMA_CHANNEL_SWID1_0_CH_0_SWID_1_WOFFSET                      0x0
#define APBDMA_CHANNEL_SWID1_0_CH_0_SWID_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_0_SWID_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APBDMA_CHANNEL_SWID1_0_CH_0_SWID_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APBDMA_CHANNEL_SWID1_0_CH_0_SWID_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


//
// REGISTER LIST
//
#define LIST_ARAPBDMA_REGS(_op_) \
_op_(APBDMA_COMMAND_0) \
_op_(APBDMA_STATUS_0) \
_op_(APBDMA_REQUESTORS_TX_0) \
_op_(APBDMA_REQUESTORS_RX_0) \
_op_(APBDMA_CNTRL_REG_0) \
_op_(APBDMA_IRQ_STA_CPU_0) \
_op_(APBDMA_IRQ_STA_COP_0) \
_op_(APBDMA_IRQ_MASK_0) \
_op_(APBDMA_IRQ_MASK_SET_0) \
_op_(APBDMA_IRQ_MASK_CLR_0) \
_op_(APBDMA_TRIG_REG_0) \
_op_(APBDMA_CHANNEL_TRIG_REG_0) \
_op_(APBDMA_DMA_STATUS_0) \
_op_(APBDMA_CHANNEL_EN_REG_0) \
_op_(APBDMA_SECURITY_REG_0) \
_op_(APBDMA_CHANNEL_SWID_0) \
_op_(APBDMA_SPARE_0) \
_op_(APBDMA_CHAN_WT_REG0_0) \
_op_(APBDMA_CHAN_WT_REG1_0) \
_op_(APBDMA_CHAN_WT_REG2_0) \
_op_(APBDMA_CHAN_WT_REG3_0) \
_op_(APBDMA_CHANNEL_SWID1_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_APBDMA     0x00000000

//
// ARAPBDMA REGISTER BANKS
//

#define APBDMA0_FIRST_REG 0x0000 // APBDMA_COMMAND_0
#define APBDMA0_LAST_REG 0x0054 // APBDMA_CHANNEL_SWID1_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARAPBDMA_H_INC_
