//
// Copyright (c) 2015 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//  * Redistributions of source code must retain the above copyright
//    notice, this list of conditions and the following disclaimer.
//  * Redistributions in binary form must reproduce the above copyright
//    notice, this list of conditions and the following disclaimer in the
//    documentation and/or other materials provided with the distribution.
//  * Neither the name of NVIDIA CORPORATION nor the names of its
//    contributors may be used to endorse or promote products derived
//    from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARDISPLAY_H_INC_
#define ___ARDISPLAY_H_INC_
#define NV_DISP_HEAD_RANGE_SIZE_WORDS   16384
#define NV_DISPLAY_GENERAL_INCR_SYNCPT_NB_CONDS 8

// Register DC_CMD_GENERAL_INCR_SYNCPT_0
#define DC_CMD_GENERAL_INCR_SYNCPT_0                    _MK_ADDR_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_SECURE                     0x0
#define DC_CMD_GENERAL_INCR_SYNCPT_0_SCR                        0
#define DC_CMD_GENERAL_INCR_SYNCPT_0_WORD_COUNT                         0x1
#define DC_CMD_GENERAL_INCR_SYNCPT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_RESET_MASK                         _MK_MASK_CONST(0x3ffff)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_READ_MASK                  _MK_MASK_CONST(0x3ffff)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_WRITE_MASK                         _MK_MASK_CONST(0x3ffff)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_SHIFT                 _MK_SHIFT_CONST(10)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_FIELD                 _MK_FIELD_CONST(0xff, DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_SHIFT)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_RANGE                 17:10
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_WOFFSET                       0x0
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_IMMEDIATE                     _MK_ENUM_CONST(0)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_OP_DONE                       _MK_ENUM_CONST(1)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_RD_DONE                       _MK_ENUM_CONST(2)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_REG_WR_SAFE                   _MK_ENUM_CONST(3)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_ENGINE_IDLE                   _MK_ENUM_CONST(4)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_FRAME_DONE                    _MK_ENUM_CONST(5)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_VPULSE3                       _MK_ENUM_CONST(6)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_FRAME_START                   _MK_ENUM_CONST(7)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_8                        _MK_ENUM_CONST(8)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_9                        _MK_ENUM_CONST(9)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_10                       _MK_ENUM_CONST(10)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_11                       _MK_ENUM_CONST(11)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_12                       _MK_ENUM_CONST(12)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_13                       _MK_ENUM_CONST(13)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_14                       _MK_ENUM_CONST(14)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_15                       _MK_ENUM_CONST(15)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_16                       _MK_ENUM_CONST(16)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_17                       _MK_ENUM_CONST(17)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_18                       _MK_ENUM_CONST(18)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_19                       _MK_ENUM_CONST(19)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_20                       _MK_ENUM_CONST(20)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_21                       _MK_ENUM_CONST(21)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_22                       _MK_ENUM_CONST(22)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_23                       _MK_ENUM_CONST(23)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_24                       _MK_ENUM_CONST(24)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_25                       _MK_ENUM_CONST(25)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_26                       _MK_ENUM_CONST(26)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_27                       _MK_ENUM_CONST(27)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_28                       _MK_ENUM_CONST(28)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_29                       _MK_ENUM_CONST(29)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_30                       _MK_ENUM_CONST(30)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_31                       _MK_ENUM_CONST(31)

#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_FIELD                 _MK_FIELD_CONST(0x3ff, DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_SHIFT)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_RANGE                 9:0
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_WOFFSET                       0x0
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0                      _MK_ADDR_CONST(0x1)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_SECURE                       0x0
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_SCR                  0
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_WORD_COUNT                   0x1
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_RESET_MASK                   _MK_MASK_CONST(0x101)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_READ_MASK                    _MK_MASK_CONST(0x101)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x101)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_SHIFT                   _MK_SHIFT_CONST(8)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_SHIFT)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_RANGE                   8:8
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_WOFFSET                 0x0
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_SHIFT)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_RANGE                 0:0
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_WOFFSET                       0x0
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0                      _MK_ADDR_CONST(0x2)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_SECURE                       0x0
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_SCR                  0
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_WORD_COUNT                   0x1
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_FIELD                    _MK_FIELD_CONST(0xffffffff, DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_SHIFT)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_RANGE                    31:0
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_WOFFSET                  0x0
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 3 [0x3]

// Reserved address 4 [0x4]

// Reserved address 5 [0x5]

// Reserved address 6 [0x6]

// Reserved address 7 [0x7]
#define NV_DISPLAY_WIN_A_INCR_SYNCPT_NB_CONDS   6

// Register DC_CMD_WIN_A_INCR_SYNCPT_0
#define DC_CMD_WIN_A_INCR_SYNCPT_0                      _MK_ADDR_CONST(0x8)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_SECURE                       0x0
#define DC_CMD_WIN_A_INCR_SYNCPT_0_SCR                  0
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WORD_COUNT                   0x1
#define DC_CMD_WIN_A_INCR_SYNCPT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_RESET_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_READ_MASK                    _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WRITE_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_SHIFT                     _MK_SHIFT_CONST(10)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_FIELD                     _MK_FIELD_CONST(0xff, DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_SHIFT)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_RANGE                     17:10
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_WOFFSET                   0x0
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_IMMEDIATE                 _MK_ENUM_CONST(0)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_OP_DONE                   _MK_ENUM_CONST(1)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_RD_DONE                   _MK_ENUM_CONST(2)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_REG_WR_SAFE                       _MK_ENUM_CONST(3)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_ENGINE_IDLE                       _MK_ENUM_CONST(4)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_LINE_FLIPPED                      _MK_ENUM_CONST(5)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_6                    _MK_ENUM_CONST(6)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_7                    _MK_ENUM_CONST(7)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_8                    _MK_ENUM_CONST(8)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_9                    _MK_ENUM_CONST(9)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_10                   _MK_ENUM_CONST(10)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_11                   _MK_ENUM_CONST(11)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_12                   _MK_ENUM_CONST(12)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_13                   _MK_ENUM_CONST(13)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_14                   _MK_ENUM_CONST(14)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_15                   _MK_ENUM_CONST(15)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_16                   _MK_ENUM_CONST(16)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_17                   _MK_ENUM_CONST(17)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_18                   _MK_ENUM_CONST(18)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_19                   _MK_ENUM_CONST(19)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_20                   _MK_ENUM_CONST(20)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_21                   _MK_ENUM_CONST(21)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_22                   _MK_ENUM_CONST(22)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_23                   _MK_ENUM_CONST(23)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_24                   _MK_ENUM_CONST(24)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_25                   _MK_ENUM_CONST(25)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_26                   _MK_ENUM_CONST(26)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_27                   _MK_ENUM_CONST(27)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_28                   _MK_ENUM_CONST(28)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_29                   _MK_ENUM_CONST(29)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_30                   _MK_ENUM_CONST(30)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_31                   _MK_ENUM_CONST(31)

#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_FIELD                     _MK_FIELD_CONST(0x3ff, DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_SHIFT)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_RANGE                     9:0
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_WOFFSET                   0x0
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0                        _MK_ADDR_CONST(0x9)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_SECURE                         0x0
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_SCR                    0
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_RESET_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_READ_MASK                      _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_SHIFT                       _MK_SHIFT_CONST(8)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_SHIFT)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_RANGE                       8:8
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_WOFFSET                     0x0
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_SHIFT)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_RANGE                     0:0
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_WOFFSET                   0x0
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0                        _MK_ADDR_CONST(0xa)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_SECURE                         0x0
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_SCR                    0
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_SHIFT)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_RANGE                        31:0
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_WOFFSET                      0x0
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 11 [0xb]

// Reserved address 12 [0xc]

// Reserved address 13 [0xd]

// Reserved address 14 [0xe]

// Reserved address 15 [0xf]
#define NV_DISPLAY_WIN_B_INCR_SYNCPT_NB_CONDS   6

// Register DC_CMD_WIN_B_INCR_SYNCPT_0
#define DC_CMD_WIN_B_INCR_SYNCPT_0                      _MK_ADDR_CONST(0x10)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_SECURE                       0x0
#define DC_CMD_WIN_B_INCR_SYNCPT_0_SCR                  0
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WORD_COUNT                   0x1
#define DC_CMD_WIN_B_INCR_SYNCPT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_RESET_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_READ_MASK                    _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WRITE_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_SHIFT                     _MK_SHIFT_CONST(10)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_FIELD                     _MK_FIELD_CONST(0xff, DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_SHIFT)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_RANGE                     17:10
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_WOFFSET                   0x0
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_IMMEDIATE                 _MK_ENUM_CONST(0)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_OP_DONE                   _MK_ENUM_CONST(1)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_RD_DONE                   _MK_ENUM_CONST(2)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_REG_WR_SAFE                       _MK_ENUM_CONST(3)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_ENGINE_IDLE                       _MK_ENUM_CONST(4)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_LINE_FLIPPED                      _MK_ENUM_CONST(5)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_6                    _MK_ENUM_CONST(6)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_7                    _MK_ENUM_CONST(7)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_8                    _MK_ENUM_CONST(8)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_9                    _MK_ENUM_CONST(9)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_10                   _MK_ENUM_CONST(10)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_11                   _MK_ENUM_CONST(11)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_12                   _MK_ENUM_CONST(12)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_13                   _MK_ENUM_CONST(13)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_14                   _MK_ENUM_CONST(14)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_15                   _MK_ENUM_CONST(15)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_16                   _MK_ENUM_CONST(16)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_17                   _MK_ENUM_CONST(17)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_18                   _MK_ENUM_CONST(18)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_19                   _MK_ENUM_CONST(19)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_20                   _MK_ENUM_CONST(20)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_21                   _MK_ENUM_CONST(21)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_22                   _MK_ENUM_CONST(22)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_23                   _MK_ENUM_CONST(23)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_24                   _MK_ENUM_CONST(24)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_25                   _MK_ENUM_CONST(25)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_26                   _MK_ENUM_CONST(26)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_27                   _MK_ENUM_CONST(27)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_28                   _MK_ENUM_CONST(28)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_29                   _MK_ENUM_CONST(29)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_30                   _MK_ENUM_CONST(30)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_31                   _MK_ENUM_CONST(31)

#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_FIELD                     _MK_FIELD_CONST(0x3ff, DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_SHIFT)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_RANGE                     9:0
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_WOFFSET                   0x0
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0                        _MK_ADDR_CONST(0x11)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_SECURE                         0x0
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_SCR                    0
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_RESET_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_READ_MASK                      _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_SHIFT                       _MK_SHIFT_CONST(8)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_SHIFT)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_RANGE                       8:8
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_WOFFSET                     0x0
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_SHIFT)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_RANGE                     0:0
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_WOFFSET                   0x0
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0                        _MK_ADDR_CONST(0x12)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_SECURE                         0x0
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_SCR                    0
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_SHIFT)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_RANGE                        31:0
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_WOFFSET                      0x0
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 19 [0x13]

// Reserved address 20 [0x14]

// Reserved address 21 [0x15]

// Reserved address 22 [0x16]

// Reserved address 23 [0x17]
#define NV_DISPLAY_WIN_C_INCR_SYNCPT_NB_CONDS   6

// Register DC_CMD_WIN_C_INCR_SYNCPT_0
#define DC_CMD_WIN_C_INCR_SYNCPT_0                      _MK_ADDR_CONST(0x18)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_SECURE                       0x0
#define DC_CMD_WIN_C_INCR_SYNCPT_0_SCR                  0
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WORD_COUNT                   0x1
#define DC_CMD_WIN_C_INCR_SYNCPT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_RESET_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_READ_MASK                    _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WRITE_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_SHIFT                     _MK_SHIFT_CONST(10)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_FIELD                     _MK_FIELD_CONST(0xff, DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_SHIFT)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_RANGE                     17:10
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_WOFFSET                   0x0
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_IMMEDIATE                 _MK_ENUM_CONST(0)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_OP_DONE                   _MK_ENUM_CONST(1)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_RD_DONE                   _MK_ENUM_CONST(2)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_REG_WR_SAFE                       _MK_ENUM_CONST(3)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_ENGINE_IDLE                       _MK_ENUM_CONST(4)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_LINE_FLIPPED                      _MK_ENUM_CONST(5)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_6                    _MK_ENUM_CONST(6)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_7                    _MK_ENUM_CONST(7)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_8                    _MK_ENUM_CONST(8)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_9                    _MK_ENUM_CONST(9)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_10                   _MK_ENUM_CONST(10)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_11                   _MK_ENUM_CONST(11)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_12                   _MK_ENUM_CONST(12)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_13                   _MK_ENUM_CONST(13)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_14                   _MK_ENUM_CONST(14)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_15                   _MK_ENUM_CONST(15)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_16                   _MK_ENUM_CONST(16)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_17                   _MK_ENUM_CONST(17)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_18                   _MK_ENUM_CONST(18)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_19                   _MK_ENUM_CONST(19)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_20                   _MK_ENUM_CONST(20)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_21                   _MK_ENUM_CONST(21)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_22                   _MK_ENUM_CONST(22)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_23                   _MK_ENUM_CONST(23)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_24                   _MK_ENUM_CONST(24)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_25                   _MK_ENUM_CONST(25)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_26                   _MK_ENUM_CONST(26)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_27                   _MK_ENUM_CONST(27)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_28                   _MK_ENUM_CONST(28)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_29                   _MK_ENUM_CONST(29)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_30                   _MK_ENUM_CONST(30)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_31                   _MK_ENUM_CONST(31)

#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_FIELD                     _MK_FIELD_CONST(0x3ff, DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_SHIFT)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_RANGE                     9:0
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_WOFFSET                   0x0
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0                        _MK_ADDR_CONST(0x19)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_SECURE                         0x0
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_SCR                    0
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_RESET_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_READ_MASK                      _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_SHIFT                       _MK_SHIFT_CONST(8)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_SHIFT)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_RANGE                       8:8
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_WOFFSET                     0x0
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_SHIFT)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_RANGE                     0:0
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_WOFFSET                   0x0
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0                        _MK_ADDR_CONST(0x1a)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_SECURE                         0x0
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_SCR                    0
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_SHIFT)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_RANGE                        31:0
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_WOFFSET                      0x0
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 27 [0x1b]

// Reserved address 28 [0x1c]

// Reserved address 29 [0x1d]

// Reserved address 30 [0x1e]

// Reserved address 31 [0x1f]

// Register DC_CMD_CONT_SYNCPT_VSYNC_0
#define DC_CMD_CONT_SYNCPT_VSYNC_0                      _MK_ADDR_CONST(0x28)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_SECURE                       0x0
#define DC_CMD_CONT_SYNCPT_VSYNC_0_SCR                  0
#define DC_CMD_CONT_SYNCPT_VSYNC_0_WORD_COUNT                   0x1
#define DC_CMD_CONT_SYNCPT_VSYNC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_RESET_MASK                   _MK_MASK_CONST(0x800003ff)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_READ_MASK                    _MK_MASK_CONST(0x800003ff)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_WRITE_MASK                   _MK_MASK_CONST(0x800003ff)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_FIELD                     _MK_FIELD_CONST(0x3ff, DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_SHIFT)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_RANGE                     9:0
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_WOFFSET                   0x0
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_SHIFT                       _MK_SHIFT_CONST(31)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_SHIFT)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_RANGE                       31:31
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_WOFFSET                     0x0
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_ENABLE                      _MK_ENUM_CONST(1)


// Register DC_CMD_CTXSW_NEXT_0
#define DC_CMD_CTXSW_NEXT_0                     _MK_ADDR_CONST(0x2f)
#define DC_CMD_CTXSW_NEXT_0_SECURE                      0x0
#define DC_CMD_CTXSW_NEXT_0_SCR                         0
#define DC_CMD_CTXSW_NEXT_0_WORD_COUNT                  0x1
#define DC_CMD_CTXSW_NEXT_0_RESET_VAL                   _MK_MASK_CONST(0xfc00)
#define DC_CMD_CTXSW_NEXT_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
#define DC_CMD_CTXSW_NEXT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_NEXT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_NEXT_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
#define DC_CMD_CTXSW_NEXT_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_NEXT_0_NEXT_CLASS_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_CTXSW_NEXT_0_NEXT_CLASS_FIELD                    _MK_FIELD_CONST(0x3ff, DC_CMD_CTXSW_NEXT_0_NEXT_CLASS_SHIFT)
#define DC_CMD_CTXSW_NEXT_0_NEXT_CLASS_RANGE                    9:0
#define DC_CMD_CTXSW_NEXT_0_NEXT_CLASS_WOFFSET                  0x0
#define DC_CMD_CTXSW_NEXT_0_NEXT_CLASS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_NEXT_0_NEXT_CLASS_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define DC_CMD_CTXSW_NEXT_0_NEXT_CLASS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_NEXT_0_NEXT_CLASS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_CTXSW_NEXT_0_NEXT_CHANNEL_SHIFT                  _MK_SHIFT_CONST(10)
#define DC_CMD_CTXSW_NEXT_0_NEXT_CHANNEL_FIELD                  _MK_FIELD_CONST(0x3ff, DC_CMD_CTXSW_NEXT_0_NEXT_CHANNEL_SHIFT)
#define DC_CMD_CTXSW_NEXT_0_NEXT_CHANNEL_RANGE                  19:10
#define DC_CMD_CTXSW_NEXT_0_NEXT_CHANNEL_WOFFSET                        0x0
#define DC_CMD_CTXSW_NEXT_0_NEXT_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x3f)
#define DC_CMD_CTXSW_NEXT_0_NEXT_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
#define DC_CMD_CTXSW_NEXT_0_NEXT_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_NEXT_0_NEXT_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_CMD_CTXSW_0
#define DC_CMD_CTXSW_0                  _MK_ADDR_CONST(0x30)
#define DC_CMD_CTXSW_0_SECURE                   0x0
#define DC_CMD_CTXSW_0_SCR                      0
#define DC_CMD_CTXSW_0_WORD_COUNT                       0x1
#define DC_CMD_CTXSW_0_RESET_VAL                        _MK_MASK_CONST(0x1fc00)
#define DC_CMD_CTXSW_0_RESET_MASK                       _MK_MASK_CONST(0x1fffff)
#define DC_CMD_CTXSW_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_0_READ_MASK                        _MK_MASK_CONST(0x1fffff)
#define DC_CMD_CTXSW_0_WRITE_MASK                       _MK_MASK_CONST(0x1fffff)
#define DC_CMD_CTXSW_0_CURR_CLASS_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_CMD_CTXSW_0_CURR_CLASS_FIELD                 _MK_FIELD_CONST(0x3ff, DC_CMD_CTXSW_0_CURR_CLASS_SHIFT)
#define DC_CMD_CTXSW_0_CURR_CLASS_RANGE                 9:0
#define DC_CMD_CTXSW_0_CURR_CLASS_WOFFSET                       0x0
#define DC_CMD_CTXSW_0_CURR_CLASS_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_0_CURR_CLASS_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
#define DC_CMD_CTXSW_0_CURR_CLASS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_0_CURR_CLASS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_CMD_CTXSW_0_AUTO_ACK_SHIFT                   _MK_SHIFT_CONST(10)
#define DC_CMD_CTXSW_0_AUTO_ACK_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_CTXSW_0_AUTO_ACK_SHIFT)
#define DC_CMD_CTXSW_0_AUTO_ACK_RANGE                   10:10
#define DC_CMD_CTXSW_0_AUTO_ACK_WOFFSET                 0x0
#define DC_CMD_CTXSW_0_AUTO_ACK_DEFAULT                 _MK_MASK_CONST(0x1)
#define DC_CMD_CTXSW_0_AUTO_ACK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_CTXSW_0_AUTO_ACK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_0_AUTO_ACK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_0_AUTO_ACK_MANUAL                  _MK_ENUM_CONST(0)
#define DC_CMD_CTXSW_0_AUTO_ACK_AUTOACK                 _MK_ENUM_CONST(1)

#define DC_CMD_CTXSW_0_CURR_CHANNEL_SHIFT                       _MK_SHIFT_CONST(11)
#define DC_CMD_CTXSW_0_CURR_CHANNEL_FIELD                       _MK_FIELD_CONST(0x3ff, DC_CMD_CTXSW_0_CURR_CHANNEL_SHIFT)
#define DC_CMD_CTXSW_0_CURR_CHANNEL_RANGE                       20:11
#define DC_CMD_CTXSW_0_CURR_CHANNEL_WOFFSET                     0x0
#define DC_CMD_CTXSW_0_CURR_CHANNEL_DEFAULT                     _MK_MASK_CONST(0x3f)
#define DC_CMD_CTXSW_0_CURR_CHANNEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
#define DC_CMD_CTXSW_0_CURR_CHANNEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_CTXSW_0_CURR_CHANNEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_CMD_DISPLAY_COMMAND_OPTION0_0
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0                        _MK_ADDR_CONST(0x31)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SECURE                         0x0
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SCR                    0
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WORD_COUNT                     0x1
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_SHIFT)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_RANGE                     0:0
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_WOFFSET                   0x0
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_SHIFT                       _MK_SHIFT_CONST(1)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_SHIFT)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_RANGE                       1:1
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_WOFFSET                     0x0
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_ENABLE                      _MK_ENUM_CONST(1)


// Register DC_CMD_DISPLAY_COMMAND_0
#define DC_CMD_DISPLAY_COMMAND_0                        _MK_ADDR_CONST(0x32)
#define DC_CMD_DISPLAY_COMMAND_0_SECURE                         0x0
#define DC_CMD_DISPLAY_COMMAND_0_SCR                    0
#define DC_CMD_DISPLAY_COMMAND_0_WORD_COUNT                     0x1
#define DC_CMD_DISPLAY_COMMAND_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_0_RESET_MASK                     _MK_MASK_CONST(0x60)
#define DC_CMD_DISPLAY_COMMAND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_0_READ_MASK                      _MK_MASK_CONST(0x60)
#define DC_CMD_DISPLAY_COMMAND_0_WRITE_MASK                     _MK_MASK_CONST(0x60)
#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_SHIFT                        _MK_SHIFT_CONST(5)
#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_FIELD                        _MK_FIELD_CONST(0x3, DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_SHIFT)
#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_RANGE                        6:5
#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_WOFFSET                      0x0
#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_STOP                 _MK_ENUM_CONST(0)
#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_C_DISPLAY                    _MK_ENUM_CONST(1)
#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_NC_DISPLAY                   _MK_ENUM_CONST(2)


// Register DC_CMD_REG_PFE_HEAD_DEBUG_0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0                     _MK_ADDR_CONST(0x33)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SECURE                      0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SCR                         0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_WORD_COUNT                  0x1
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_RANGE                        0:0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_WOFFSET                      0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_NO                   _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_YES                  _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_LAST_SHIFT                   _MK_SHIFT_CONST(1)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_LAST_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_LAST_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_LAST_RANGE                   1:1
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_LAST_WOFFSET                 0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_LAST_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_LAST_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_LAST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_LAST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_LAST_NO                      _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_ALIVE_LAST_YES                     _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_REQFIFO_WR_BUSY_SHIFT                      _MK_SHIFT_CONST(2)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_REQFIFO_WR_BUSY_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_REQFIFO_WR_BUSY_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_REQFIFO_WR_BUSY_RANGE                      2:2
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_REQFIFO_WR_BUSY_WOFFSET                    0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_REQFIFO_WR_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_REQFIFO_WR_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_REQFIFO_WR_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_REQFIFO_WR_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_REQFIFO_WR_BUSY_NO                 _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_REQFIFO_WR_BUSY_YES                        _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_RESPFIFO_RD_REQ_SHIFT                      _MK_SHIFT_CONST(3)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_RESPFIFO_RD_REQ_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_RESPFIFO_RD_REQ_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_RESPFIFO_RD_REQ_RANGE                      3:3
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_RESPFIFO_RD_REQ_WOFFSET                    0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_RESPFIFO_RD_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_RESPFIFO_RD_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_RESPFIFO_RD_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_RESPFIFO_RD_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_RESPFIFO_RD_REQ_NO                 _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_POSTCOMP_RESPFIFO_RD_REQ_YES                        _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_SHIFT                  _MK_SHIFT_CONST(4)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_RANGE                  4:4
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_WOFFSET                        0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_YES                    _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_LAST_SHIFT                     _MK_SHIFT_CONST(5)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_LAST_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_LAST_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_LAST_RANGE                     5:5
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_LAST_WOFFSET                   0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_LAST_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_LAST_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_LAST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_LAST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_LAST_NO                        _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_ALIVE_LAST_YES                       _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_REQFIFO_WR_BUSY_SHIFT                        _MK_SHIFT_CONST(6)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_REQFIFO_WR_BUSY_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_REQFIFO_WR_BUSY_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_REQFIFO_WR_BUSY_RANGE                        6:6
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_REQFIFO_WR_BUSY_WOFFSET                      0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_REQFIFO_WR_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_REQFIFO_WR_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_REQFIFO_WR_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_REQFIFO_WR_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_REQFIFO_WR_BUSY_NO                   _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_REQFIFO_WR_BUSY_YES                  _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_RESPFIFO_RD_REQ_SHIFT                        _MK_SHIFT_CONST(7)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_RESPFIFO_RD_REQ_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_RESPFIFO_RD_REQ_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_RESPFIFO_RD_REQ_RANGE                        7:7
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_RESPFIFO_RD_REQ_WOFFSET                      0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_RESPFIFO_RD_REQ_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_RESPFIFO_RD_REQ_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_RESPFIFO_RD_REQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_RESPFIFO_RD_REQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_RESPFIFO_RD_REQ_NO                   _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_CURSOR_PRECOMP_RESPFIFO_RD_REQ_YES                  _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_SHIFT                      _MK_SHIFT_CONST(8)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_RANGE                      8:8
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_WOFFSET                    0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_NO                 _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_YES                        _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_LAST_SHIFT                 _MK_SHIFT_CONST(9)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_LAST_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_LAST_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_LAST_RANGE                 9:9
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_LAST_WOFFSET                       0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_LAST_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_LAST_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_LAST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_LAST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_LAST_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_ALIVE_LAST_YES                   _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_REQFIFO_WR_BUSY_SHIFT                    _MK_SHIFT_CONST(10)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_REQFIFO_WR_BUSY_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_REQFIFO_WR_BUSY_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_REQFIFO_WR_BUSY_RANGE                    10:10
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_REQFIFO_WR_BUSY_WOFFSET                  0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_REQFIFO_WR_BUSY_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_REQFIFO_WR_BUSY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_REQFIFO_WR_BUSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_REQFIFO_WR_BUSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_REQFIFO_WR_BUSY_NO                       _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_REQFIFO_WR_BUSY_YES                      _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_RESPFIFO_RD_REQ_SHIFT                    _MK_SHIFT_CONST(11)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_RESPFIFO_RD_REQ_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_RESPFIFO_RD_REQ_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_RESPFIFO_RD_REQ_RANGE                    11:11
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_RESPFIFO_RD_REQ_WOFFSET                  0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_RESPFIFO_RD_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_RESPFIFO_RD_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_RESPFIFO_RD_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_RESPFIFO_RD_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_RESPFIFO_RD_REQ_NO                       _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_RG_RESPFIFO_RD_REQ_YES                      _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_SHIFT                        _MK_SHIFT_CONST(12)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_FIELD                        _MK_FIELD_CONST(0x7, DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_RANGE                        14:12
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_WOFFSET                      0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_IDLE                 _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_WAIT_LVRET                   _MK_ENUM_CONST(1)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_WAIT_SUSP                    _MK_ENUM_CONST(2)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_WAIT_ACK                     _MK_ENUM_CONST(3)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM1_UNSUSP_ACK                   _MK_ENUM_CONST(4)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_SHIFT                        _MK_SHIFT_CONST(15)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_FIELD                        _MK_FIELD_CONST(0x7, DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_RANGE                        17:15
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_WOFFSET                      0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_IDLE                 _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_WAIT_SEQSM1                  _MK_ENUM_CONST(1)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_WAIT_LOADV_ACK                       _MK_ENUM_CONST(2)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_CALC_FD                      _MK_ENUM_CONST(3)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_WAIT_FD                      _MK_ENUM_CONST(4)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SEQSM2_WAIT_SF_ACK                  _MK_ENUM_CONST(5)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_ACT_REQ_MASK_SHIFT                  _MK_SHIFT_CONST(18)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_ACT_REQ_MASK_FIELD                  _MK_FIELD_CONST(0x1ff, DC_CMD_REG_PFE_HEAD_DEBUG_0_ACT_REQ_MASK_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_ACT_REQ_MASK_RANGE                  26:18
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_ACT_REQ_MASK_WOFFSET                        0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_ACT_REQ_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_ACT_REQ_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_ACT_REQ_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_ACT_REQ_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_HEAD_EN_SHIFT                  _MK_SHIFT_CONST(27)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_HEAD_EN_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_HEAD_EN_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_HEAD_EN_RANGE                  27:27
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_HEAD_EN_WOFFSET                        0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_HEAD_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_HEAD_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_HEAD_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_HEAD_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_HEAD_EN_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_HEAD_EN_YES                    _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_RG_EN_SHIFT                    _MK_SHIFT_CONST(28)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_RG_EN_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_RG_EN_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_RG_EN_RANGE                    28:28
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_RG_EN_WOFFSET                  0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_RG_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_RG_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_RG_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_RG_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_RG_EN_NO                       _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_DISPCLK_RG_EN_YES                      _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_RG_PCLK_EN_SHIFT                       _MK_SHIFT_CONST(29)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_RG_PCLK_EN_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_RG_PCLK_EN_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_RG_PCLK_EN_RANGE                       29:29
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_RG_PCLK_EN_WOFFSET                     0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_RG_PCLK_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_RG_PCLK_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_RG_PCLK_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_RG_PCLK_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_RG_PCLK_EN_NO                  _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_SLCG_RG_PCLK_EN_YES                 _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_AWAKE_SHIFT                    _MK_SHIFT_CONST(30)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_AWAKE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_AWAKE_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_AWAKE_RANGE                    30:30
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_AWAKE_WOFFSET                  0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_AWAKE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_AWAKE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_AWAKE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_AWAKE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_AWAKE_NO                       _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_AWAKE_YES                      _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_STALLED_SHIFT                  _MK_SHIFT_CONST(31)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_STALLED_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_STALLED_SHIFT)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_STALLED_RANGE                  31:31
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_STALLED_WOFFSET                        0x0
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_STALLED_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_STALLED_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_STALLED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_STALLED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_STALLED_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_HEAD_DEBUG_0_HEAD_STALLED_YES                    _MK_ENUM_CONST(1)


// Register DC_CMD_INT_STATUS_0
#define DC_CMD_INT_STATUS_0                     _MK_ADDR_CONST(0x37)
#define DC_CMD_INT_STATUS_0_SECURE                      0x0
#define DC_CMD_INT_STATUS_0_SCR                         0
#define DC_CMD_INT_STATUS_0_WORD_COUNT                  0x1
#define DC_CMD_INT_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_STATUS_0_FRAME_END_INT_SHIFT                 _MK_SHIFT_CONST(1)
#define DC_CMD_INT_STATUS_0_FRAME_END_INT_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_FRAME_END_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_FRAME_END_INT_RANGE                 1:1
#define DC_CMD_INT_STATUS_0_FRAME_END_INT_WOFFSET                       0x0
#define DC_CMD_INT_STATUS_0_FRAME_END_INT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_FRAME_END_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_FRAME_END_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_FRAME_END_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_V_BLANK_INT_SHIFT                   _MK_SHIFT_CONST(2)
#define DC_CMD_INT_STATUS_0_V_BLANK_INT_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_V_BLANK_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_V_BLANK_INT_RANGE                   2:2
#define DC_CMD_INT_STATUS_0_V_BLANK_INT_WOFFSET                 0x0
#define DC_CMD_INT_STATUS_0_V_BLANK_INT_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_V_BLANK_INT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_V_BLANK_INT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_V_BLANK_INT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_SHIFT                  _MK_SHIFT_CONST(4)
#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_V_PULSE3_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_RANGE                  4:4
#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_WOFFSET                        0x0
#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_SHIFT                  _MK_SHIFT_CONST(5)
#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_V_PULSE2_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_RANGE                  5:5
#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_WOFFSET                        0x0
#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_REGION_CRC_INT_SHIFT                        _MK_SHIFT_CONST(6)
#define DC_CMD_INT_STATUS_0_REGION_CRC_INT_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_REGION_CRC_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_REGION_CRC_INT_RANGE                        6:6
#define DC_CMD_INT_STATUS_0_REGION_CRC_INT_WOFFSET                      0x0
#define DC_CMD_INT_STATUS_0_REGION_CRC_INT_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_REGION_CRC_INT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_REGION_CRC_INT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_REGION_CRC_INT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_REG_TMOUT_INT_SHIFT                 _MK_SHIFT_CONST(7)
#define DC_CMD_INT_STATUS_0_REG_TMOUT_INT_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_REG_TMOUT_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_REG_TMOUT_INT_RANGE                 7:7
#define DC_CMD_INT_STATUS_0_REG_TMOUT_INT_WOFFSET                       0x0
#define DC_CMD_INT_STATUS_0_REG_TMOUT_INT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_REG_TMOUT_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_REG_TMOUT_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_REG_TMOUT_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_MSF_INT_SHIFT                       _MK_SHIFT_CONST(12)
#define DC_CMD_INT_STATUS_0_MSF_INT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_MSF_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_MSF_INT_RANGE                       12:12
#define DC_CMD_INT_STATUS_0_MSF_INT_WOFFSET                     0x0
#define DC_CMD_INT_STATUS_0_MSF_INT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_MSF_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_MSF_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_MSF_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_HEAD_UF_INT_SHIFT                   _MK_SHIFT_CONST(23)
#define DC_CMD_INT_STATUS_0_HEAD_UF_INT_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_HEAD_UF_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_HEAD_UF_INT_RANGE                   23:23
#define DC_CMD_INT_STATUS_0_HEAD_UF_INT_WOFFSET                 0x0
#define DC_CMD_INT_STATUS_0_HEAD_UF_INT_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_HEAD_UF_INT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_HEAD_UF_INT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_HEAD_UF_INT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_SHIFT                      _MK_SHIFT_CONST(24)
#define DC_CMD_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_RANGE                      24:24
#define DC_CMD_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_WOFFSET                    0x0
#define DC_CMD_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_DSC_OBUF_UF_INT_SHIFT                       _MK_SHIFT_CONST(26)
#define DC_CMD_INT_STATUS_0_DSC_OBUF_UF_INT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_DSC_OBUF_UF_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_DSC_OBUF_UF_INT_RANGE                       26:26
#define DC_CMD_INT_STATUS_0_DSC_OBUF_UF_INT_WOFFSET                     0x0
#define DC_CMD_INT_STATUS_0_DSC_OBUF_UF_INT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_OBUF_UF_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_OBUF_UF_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_OBUF_UF_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_DSC_RBUF_UF_INT_SHIFT                       _MK_SHIFT_CONST(27)
#define DC_CMD_INT_STATUS_0_DSC_RBUF_UF_INT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_DSC_RBUF_UF_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_DSC_RBUF_UF_INT_RANGE                       27:27
#define DC_CMD_INT_STATUS_0_DSC_RBUF_UF_INT_WOFFSET                     0x0
#define DC_CMD_INT_STATUS_0_DSC_RBUF_UF_INT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_RBUF_UF_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_RBUF_UF_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_RBUF_UF_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_DSC_BBUF_UF_INT_SHIFT                       _MK_SHIFT_CONST(28)
#define DC_CMD_INT_STATUS_0_DSC_BBUF_UF_INT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_DSC_BBUF_UF_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_DSC_BBUF_UF_INT_RANGE                       28:28
#define DC_CMD_INT_STATUS_0_DSC_BBUF_UF_INT_WOFFSET                     0x0
#define DC_CMD_INT_STATUS_0_DSC_BBUF_UF_INT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_BBUF_UF_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_BBUF_UF_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_BBUF_UF_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_INT_STATUS_0_DSC_TO_UF_INT_SHIFT                 _MK_SHIFT_CONST(29)
#define DC_CMD_INT_STATUS_0_DSC_TO_UF_INT_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_DSC_TO_UF_INT_SHIFT)
#define DC_CMD_INT_STATUS_0_DSC_TO_UF_INT_RANGE                 29:29
#define DC_CMD_INT_STATUS_0_DSC_TO_UF_INT_WOFFSET                       0x0
#define DC_CMD_INT_STATUS_0_DSC_TO_UF_INT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_TO_UF_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_TO_UF_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_STATUS_0_DSC_TO_UF_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_CMD_INT_MASK_0
#define DC_CMD_INT_MASK_0                       _MK_ADDR_CONST(0x38)
#define DC_CMD_INT_MASK_0_SECURE                        0x0
#define DC_CMD_INT_MASK_0_SCR                   0
#define DC_CMD_INT_MASK_0_WORD_COUNT                    0x1
#define DC_CMD_INT_MASK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_RESET_MASK                    _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_READ_MASK                     _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_SHIFT                      _MK_SHIFT_CONST(1)
#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_RANGE                      1:1
#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_WOFFSET                    0x0
#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_MASKED                     _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_NOTMASKED                  _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_SHIFT                        _MK_SHIFT_CONST(2)
#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_RANGE                        2:2
#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_WOFFSET                      0x0
#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_MASKED                       _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_NOTMASKED                    _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_SHIFT                       _MK_SHIFT_CONST(4)
#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_RANGE                       4:4
#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_WOFFSET                     0x0
#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_MASKED                      _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_SHIFT                       _MK_SHIFT_CONST(5)
#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_RANGE                       5:5
#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_WOFFSET                     0x0
#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_MASKED                      _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_REGION_CRC_INT_MASK_SHIFT                     _MK_SHIFT_CONST(6)
#define DC_CMD_INT_MASK_0_REGION_CRC_INT_MASK_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_REGION_CRC_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_REGION_CRC_INT_MASK_RANGE                     6:6
#define DC_CMD_INT_MASK_0_REGION_CRC_INT_MASK_WOFFSET                   0x0
#define DC_CMD_INT_MASK_0_REGION_CRC_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_REGION_CRC_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_REGION_CRC_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_REGION_CRC_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_REGION_CRC_INT_MASK_MASKED                    _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_REGION_CRC_INT_MASK_NOTMASKED                 _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_REG_TMOUT_INT_MASK_SHIFT                      _MK_SHIFT_CONST(7)
#define DC_CMD_INT_MASK_0_REG_TMOUT_INT_MASK_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_REG_TMOUT_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_REG_TMOUT_INT_MASK_RANGE                      7:7
#define DC_CMD_INT_MASK_0_REG_TMOUT_INT_MASK_WOFFSET                    0x0
#define DC_CMD_INT_MASK_0_REG_TMOUT_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_REG_TMOUT_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_REG_TMOUT_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_REG_TMOUT_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_REG_TMOUT_INT_MASK_MASKED                     _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_REG_TMOUT_INT_MASK_NOTMASKED                  _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_MSF_INT_MASK_SHIFT                    _MK_SHIFT_CONST(12)
#define DC_CMD_INT_MASK_0_MSF_INT_MASK_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_MSF_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_MSF_INT_MASK_RANGE                    12:12
#define DC_CMD_INT_MASK_0_MSF_INT_MASK_WOFFSET                  0x0
#define DC_CMD_INT_MASK_0_MSF_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_MSF_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_MSF_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_MSF_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_MSF_INT_MASK_MASKED                   _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_MSF_INT_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_HEAD_UF_INT_MASK_SHIFT                        _MK_SHIFT_CONST(23)
#define DC_CMD_INT_MASK_0_HEAD_UF_INT_MASK_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_HEAD_UF_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_HEAD_UF_INT_MASK_RANGE                        23:23
#define DC_CMD_INT_MASK_0_HEAD_UF_INT_MASK_WOFFSET                      0x0
#define DC_CMD_INT_MASK_0_HEAD_UF_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_HEAD_UF_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_HEAD_UF_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_HEAD_UF_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_HEAD_UF_INT_MASK_MASKED                       _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_HEAD_UF_INT_MASK_NOTMASKED                    _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_SHIFT                   _MK_SHIFT_CONST(24)
#define DC_CMD_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_RANGE                   24:24
#define DC_CMD_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_WOFFSET                 0x0
#define DC_CMD_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_DSC_OBUF_UF_INT_MASK_SHIFT                    _MK_SHIFT_CONST(26)
#define DC_CMD_INT_MASK_0_DSC_OBUF_UF_INT_MASK_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_DSC_OBUF_UF_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_DSC_OBUF_UF_INT_MASK_RANGE                    26:26
#define DC_CMD_INT_MASK_0_DSC_OBUF_UF_INT_MASK_WOFFSET                  0x0
#define DC_CMD_INT_MASK_0_DSC_OBUF_UF_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_OBUF_UF_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_DSC_OBUF_UF_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_OBUF_UF_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_OBUF_UF_INT_MASK_MASKED                   _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_DSC_OBUF_UF_INT_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_DSC_RBUF_UF_INT_MASK_SHIFT                    _MK_SHIFT_CONST(27)
#define DC_CMD_INT_MASK_0_DSC_RBUF_UF_INT_MASK_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_DSC_RBUF_UF_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_DSC_RBUF_UF_INT_MASK_RANGE                    27:27
#define DC_CMD_INT_MASK_0_DSC_RBUF_UF_INT_MASK_WOFFSET                  0x0
#define DC_CMD_INT_MASK_0_DSC_RBUF_UF_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_RBUF_UF_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_DSC_RBUF_UF_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_RBUF_UF_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_RBUF_UF_INT_MASK_MASKED                   _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_DSC_RBUF_UF_INT_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_DSC_BBUF_UF_INT_MASK_SHIFT                    _MK_SHIFT_CONST(28)
#define DC_CMD_INT_MASK_0_DSC_BBUF_UF_INT_MASK_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_DSC_BBUF_UF_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_DSC_BBUF_UF_INT_MASK_RANGE                    28:28
#define DC_CMD_INT_MASK_0_DSC_BBUF_UF_INT_MASK_WOFFSET                  0x0
#define DC_CMD_INT_MASK_0_DSC_BBUF_UF_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_BBUF_UF_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_DSC_BBUF_UF_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_BBUF_UF_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_BBUF_UF_INT_MASK_MASKED                   _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_DSC_BBUF_UF_INT_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define DC_CMD_INT_MASK_0_DSC_TO_UF_INT_MASK_SHIFT                      _MK_SHIFT_CONST(29)
#define DC_CMD_INT_MASK_0_DSC_TO_UF_INT_MASK_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_DSC_TO_UF_INT_MASK_SHIFT)
#define DC_CMD_INT_MASK_0_DSC_TO_UF_INT_MASK_RANGE                      29:29
#define DC_CMD_INT_MASK_0_DSC_TO_UF_INT_MASK_WOFFSET                    0x0
#define DC_CMD_INT_MASK_0_DSC_TO_UF_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_TO_UF_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_INT_MASK_0_DSC_TO_UF_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_TO_UF_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_MASK_0_DSC_TO_UF_INT_MASK_MASKED                     _MK_ENUM_CONST(0)
#define DC_CMD_INT_MASK_0_DSC_TO_UF_INT_MASK_NOTMASKED                  _MK_ENUM_CONST(1)


// Register DC_CMD_INT_ENABLE_0
#define DC_CMD_INT_ENABLE_0                     _MK_ADDR_CONST(0x39)
#define DC_CMD_INT_ENABLE_0_SECURE                      0x0
#define DC_CMD_INT_ENABLE_0_SCR                         0
#define DC_CMD_INT_ENABLE_0_WORD_COUNT                  0x1
#define DC_CMD_INT_ENABLE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_RESET_MASK                  _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_ENABLE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_READ_MASK                   _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_ENABLE_0_WRITE_MASK                  _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_RANGE                  1:1
#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_WOFFSET                        0x0
#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_SHIFT                    _MK_SHIFT_CONST(2)
#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_RANGE                    2:2
#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_WOFFSET                  0x0
#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SHIFT                   _MK_SHIFT_CONST(4)
#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_RANGE                   4:4
#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_WOFFSET                 0x0
#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SHIFT                   _MK_SHIFT_CONST(5)
#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_RANGE                   5:5
#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_WOFFSET                 0x0
#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_REGION_CRC_INT_ENABLE_SHIFT                 _MK_SHIFT_CONST(6)
#define DC_CMD_INT_ENABLE_0_REGION_CRC_INT_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_REGION_CRC_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_REGION_CRC_INT_ENABLE_RANGE                 6:6
#define DC_CMD_INT_ENABLE_0_REGION_CRC_INT_ENABLE_WOFFSET                       0x0
#define DC_CMD_INT_ENABLE_0_REGION_CRC_INT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_REGION_CRC_INT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_REGION_CRC_INT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_REGION_CRC_INT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_REGION_CRC_INT_ENABLE_DISABLE                       _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_REGION_CRC_INT_ENABLE_ENABLE                        _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
#define DC_CMD_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_RANGE                  7:7
#define DC_CMD_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_WOFFSET                        0x0
#define DC_CMD_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_SHIFT                        _MK_SHIFT_CONST(12)
#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_RANGE                        12:12
#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_WOFFSET                      0x0
#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_HEAD_UF_INT_ENABLE_SHIFT                    _MK_SHIFT_CONST(23)
#define DC_CMD_INT_ENABLE_0_HEAD_UF_INT_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_HEAD_UF_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_HEAD_UF_INT_ENABLE_RANGE                    23:23
#define DC_CMD_INT_ENABLE_0_HEAD_UF_INT_ENABLE_WOFFSET                  0x0
#define DC_CMD_INT_ENABLE_0_HEAD_UF_INT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_HEAD_UF_INT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_HEAD_UF_INT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_HEAD_UF_INT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_HEAD_UF_INT_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_HEAD_UF_INT_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_SHIFT                       _MK_SHIFT_CONST(24)
#define DC_CMD_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_RANGE                       24:24
#define DC_CMD_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_WOFFSET                     0x0
#define DC_CMD_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_SHIFT                        _MK_SHIFT_CONST(26)
#define DC_CMD_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_RANGE                        26:26
#define DC_CMD_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_WOFFSET                      0x0
#define DC_CMD_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_SHIFT                        _MK_SHIFT_CONST(27)
#define DC_CMD_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_RANGE                        27:27
#define DC_CMD_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_WOFFSET                      0x0
#define DC_CMD_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_SHIFT                        _MK_SHIFT_CONST(28)
#define DC_CMD_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_RANGE                        28:28
#define DC_CMD_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_WOFFSET                      0x0
#define DC_CMD_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define DC_CMD_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_SHIFT                  _MK_SHIFT_CONST(29)
#define DC_CMD_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_SHIFT)
#define DC_CMD_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_RANGE                  29:29
#define DC_CMD_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_WOFFSET                        0x0
#define DC_CMD_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define DC_CMD_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_ENABLE                 _MK_ENUM_CONST(1)


// Register DC_CMD_INT_TYPE_0
#define DC_CMD_INT_TYPE_0                       _MK_ADDR_CONST(0x3a)
#define DC_CMD_INT_TYPE_0_SECURE                        0x0
#define DC_CMD_INT_TYPE_0_SCR                   0
#define DC_CMD_INT_TYPE_0_WORD_COUNT                    0x1
#define DC_CMD_INT_TYPE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_RESET_MASK                    _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_TYPE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_READ_MASK                     _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_TYPE_0_WRITE_MASK                    _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_SHIFT                      _MK_SHIFT_CONST(1)
#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_RANGE                      1:1
#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_WOFFSET                    0x0
#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_EDGE                       _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_LEVEL                      _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_SHIFT                        _MK_SHIFT_CONST(2)
#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_RANGE                        2:2
#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_WOFFSET                      0x0
#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_EDGE                 _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_LEVEL                        _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_SHIFT                       _MK_SHIFT_CONST(4)
#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_RANGE                       4:4
#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_WOFFSET                     0x0
#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_EDGE                        _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_LEVEL                       _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_SHIFT                       _MK_SHIFT_CONST(5)
#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_RANGE                       5:5
#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_WOFFSET                     0x0
#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_EDGE                        _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_LEVEL                       _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_REGION_CRC_INT_TYPE_SHIFT                     _MK_SHIFT_CONST(6)
#define DC_CMD_INT_TYPE_0_REGION_CRC_INT_TYPE_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_REGION_CRC_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_REGION_CRC_INT_TYPE_RANGE                     6:6
#define DC_CMD_INT_TYPE_0_REGION_CRC_INT_TYPE_WOFFSET                   0x0
#define DC_CMD_INT_TYPE_0_REGION_CRC_INT_TYPE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_REGION_CRC_INT_TYPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_REGION_CRC_INT_TYPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_REGION_CRC_INT_TYPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_REGION_CRC_INT_TYPE_EDGE                      _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_REGION_CRC_INT_TYPE_LEVEL                     _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_REG_TMOUT_INT_TYPE_SHIFT                      _MK_SHIFT_CONST(7)
#define DC_CMD_INT_TYPE_0_REG_TMOUT_INT_TYPE_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_REG_TMOUT_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_REG_TMOUT_INT_TYPE_RANGE                      7:7
#define DC_CMD_INT_TYPE_0_REG_TMOUT_INT_TYPE_WOFFSET                    0x0
#define DC_CMD_INT_TYPE_0_REG_TMOUT_INT_TYPE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_REG_TMOUT_INT_TYPE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_REG_TMOUT_INT_TYPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_REG_TMOUT_INT_TYPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_REG_TMOUT_INT_TYPE_EDGE                       _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_REG_TMOUT_INT_TYPE_LEVEL                      _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(12)
#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_MSF_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_RANGE                    12:12
#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_WOFFSET                  0x0
#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_HEAD_UF_INT_TYPE_SHIFT                        _MK_SHIFT_CONST(23)
#define DC_CMD_INT_TYPE_0_HEAD_UF_INT_TYPE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_HEAD_UF_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_HEAD_UF_INT_TYPE_RANGE                        23:23
#define DC_CMD_INT_TYPE_0_HEAD_UF_INT_TYPE_WOFFSET                      0x0
#define DC_CMD_INT_TYPE_0_HEAD_UF_INT_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_HEAD_UF_INT_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_HEAD_UF_INT_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_HEAD_UF_INT_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_HEAD_UF_INT_TYPE_EDGE                 _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_HEAD_UF_INT_TYPE_LEVEL                        _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(24)
#define DC_CMD_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_RANGE                   24:24
#define DC_CMD_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_WOFFSET                 0x0
#define DC_CMD_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(26)
#define DC_CMD_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_RANGE                    26:26
#define DC_CMD_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_WOFFSET                  0x0
#define DC_CMD_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(27)
#define DC_CMD_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_RANGE                    27:27
#define DC_CMD_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_WOFFSET                  0x0
#define DC_CMD_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(28)
#define DC_CMD_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_RANGE                    28:28
#define DC_CMD_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_WOFFSET                  0x0
#define DC_CMD_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)

#define DC_CMD_INT_TYPE_0_DSC_TO_UF_INT_TYPE_SHIFT                      _MK_SHIFT_CONST(29)
#define DC_CMD_INT_TYPE_0_DSC_TO_UF_INT_TYPE_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_DSC_TO_UF_INT_TYPE_SHIFT)
#define DC_CMD_INT_TYPE_0_DSC_TO_UF_INT_TYPE_RANGE                      29:29
#define DC_CMD_INT_TYPE_0_DSC_TO_UF_INT_TYPE_WOFFSET                    0x0
#define DC_CMD_INT_TYPE_0_DSC_TO_UF_INT_TYPE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_TO_UF_INT_TYPE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_INT_TYPE_0_DSC_TO_UF_INT_TYPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_TO_UF_INT_TYPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_TYPE_0_DSC_TO_UF_INT_TYPE_EDGE                       _MK_ENUM_CONST(0)
#define DC_CMD_INT_TYPE_0_DSC_TO_UF_INT_TYPE_LEVEL                      _MK_ENUM_CONST(1)


// Register DC_CMD_INT_POLARITY_0
#define DC_CMD_INT_POLARITY_0                   _MK_ADDR_CONST(0x3b)
#define DC_CMD_INT_POLARITY_0_SECURE                    0x0
#define DC_CMD_INT_POLARITY_0_SCR                       0
#define DC_CMD_INT_POLARITY_0_WORD_COUNT                        0x1
#define DC_CMD_INT_POLARITY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_RESET_MASK                        _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_POLARITY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_READ_MASK                         _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_POLARITY_0_WRITE_MASK                        _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_SHIFT                      _MK_SHIFT_CONST(1)
#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_RANGE                      1:1
#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_WOFFSET                    0x0
#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_LOW                        _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_HIGH                       _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_SHIFT                        _MK_SHIFT_CONST(2)
#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_RANGE                        2:2
#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_WOFFSET                      0x0
#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_LOW                  _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_HIGH                 _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SHIFT                       _MK_SHIFT_CONST(4)
#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_RANGE                       4:4
#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_WOFFSET                     0x0
#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_LOW                 _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_HIGH                        _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SHIFT                       _MK_SHIFT_CONST(5)
#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_RANGE                       5:5
#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_WOFFSET                     0x0
#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_LOW                 _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_HIGH                        _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_REGION_CRC_INT_POLARITY_SHIFT                     _MK_SHIFT_CONST(6)
#define DC_CMD_INT_POLARITY_0_REGION_CRC_INT_POLARITY_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_REGION_CRC_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_REGION_CRC_INT_POLARITY_RANGE                     6:6
#define DC_CMD_INT_POLARITY_0_REGION_CRC_INT_POLARITY_WOFFSET                   0x0
#define DC_CMD_INT_POLARITY_0_REGION_CRC_INT_POLARITY_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_REGION_CRC_INT_POLARITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_REGION_CRC_INT_POLARITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_REGION_CRC_INT_POLARITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_REGION_CRC_INT_POLARITY_LOW                       _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_REGION_CRC_INT_POLARITY_HIGH                      _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_SHIFT                      _MK_SHIFT_CONST(7)
#define DC_CMD_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_RANGE                      7:7
#define DC_CMD_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_WOFFSET                    0x0
#define DC_CMD_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_LOW                        _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_HIGH                       _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_SHIFT                    _MK_SHIFT_CONST(12)
#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_RANGE                    12:12
#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_WOFFSET                  0x0
#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_LOW                      _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_HIGH                     _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_HEAD_UF_INT_POLARITY_SHIFT                        _MK_SHIFT_CONST(23)
#define DC_CMD_INT_POLARITY_0_HEAD_UF_INT_POLARITY_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_HEAD_UF_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_HEAD_UF_INT_POLARITY_RANGE                        23:23
#define DC_CMD_INT_POLARITY_0_HEAD_UF_INT_POLARITY_WOFFSET                      0x0
#define DC_CMD_INT_POLARITY_0_HEAD_UF_INT_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_HEAD_UF_INT_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_HEAD_UF_INT_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_HEAD_UF_INT_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_HEAD_UF_INT_POLARITY_LOW                  _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_HEAD_UF_INT_POLARITY_HIGH                 _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(24)
#define DC_CMD_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_RANGE                   24:24
#define DC_CMD_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_WOFFSET                 0x0
#define DC_CMD_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_SHIFT                    _MK_SHIFT_CONST(26)
#define DC_CMD_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_RANGE                    26:26
#define DC_CMD_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_WOFFSET                  0x0
#define DC_CMD_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_LOW                      _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_HIGH                     _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_SHIFT                    _MK_SHIFT_CONST(27)
#define DC_CMD_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_RANGE                    27:27
#define DC_CMD_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_WOFFSET                  0x0
#define DC_CMD_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_LOW                      _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_HIGH                     _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_SHIFT                    _MK_SHIFT_CONST(28)
#define DC_CMD_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_RANGE                    28:28
#define DC_CMD_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_WOFFSET                  0x0
#define DC_CMD_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_LOW                      _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_HIGH                     _MK_ENUM_CONST(1)

#define DC_CMD_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_SHIFT                      _MK_SHIFT_CONST(29)
#define DC_CMD_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_SHIFT)
#define DC_CMD_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_RANGE                      29:29
#define DC_CMD_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_WOFFSET                    0x0
#define DC_CMD_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_LOW                        _MK_ENUM_CONST(0)
#define DC_CMD_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_HIGH                       _MK_ENUM_CONST(1)


// Register DC_CMD_STATE_ACCESS_0
#define DC_CMD_STATE_ACCESS_0                   _MK_ADDR_CONST(0x40)
#define DC_CMD_STATE_ACCESS_0_SECURE                    0x0
#define DC_CMD_STATE_ACCESS_0_SCR                       0
#define DC_CMD_STATE_ACCESS_0_WORD_COUNT                        0x1
#define DC_CMD_STATE_ACCESS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_ACCESS_0_RESET_MASK                        _MK_MASK_CONST(0x5)
#define DC_CMD_STATE_ACCESS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_ACCESS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_ACCESS_0_READ_MASK                         _MK_MASK_CONST(0x5)
#define DC_CMD_STATE_ACCESS_0_WRITE_MASK                        _MK_MASK_CONST(0x5)
#define DC_CMD_STATE_ACCESS_0_READ_MUX_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_STATE_ACCESS_0_READ_MUX_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_STATE_ACCESS_0_READ_MUX_SHIFT)
#define DC_CMD_STATE_ACCESS_0_READ_MUX_RANGE                    0:0
#define DC_CMD_STATE_ACCESS_0_READ_MUX_WOFFSET                  0x0
#define DC_CMD_STATE_ACCESS_0_READ_MUX_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_ACCESS_0_READ_MUX_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_ACCESS_0_READ_MUX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_ACCESS_0_READ_MUX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_ACCESS_0_READ_MUX_ASSEMBLY                 _MK_ENUM_CONST(0)
#define DC_CMD_STATE_ACCESS_0_READ_MUX_ACTIVE                   _MK_ENUM_CONST(1)

#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_SHIFT                   _MK_SHIFT_CONST(2)
#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_STATE_ACCESS_0_WRITE_MUX_SHIFT)
#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_RANGE                   2:2
#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_WOFFSET                 0x0
#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_ASSEMBLY                        _MK_ENUM_CONST(0)
#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_ACTIVE                  _MK_ENUM_CONST(1)


// Register DC_CMD_STATE_CONTROL_0
#define DC_CMD_STATE_CONTROL_0                  _MK_ADDR_CONST(0x41)
#define DC_CMD_STATE_CONTROL_0_SECURE                   0x0
#define DC_CMD_STATE_CONTROL_0_SCR                      0
#define DC_CMD_STATE_CONTROL_0_WORD_COUNT                       0x1
#define DC_CMD_STATE_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x103ffff)
#define DC_CMD_STATE_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x103ffff)
#define DC_CMD_STATE_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x103ffff)
#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_SHIFT)
#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_RANGE                    0:0
#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_WOFFSET                  0x0
#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_SHIFT                      _MK_SHIFT_CONST(1)
#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_RANGE                      1:1
#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_WOFFSET                    0x0
#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_ENABLE                     _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_SHIFT                      _MK_SHIFT_CONST(2)
#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_RANGE                      2:2
#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_WOFFSET                    0x0
#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_ENABLE                     _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_SHIFT                      _MK_SHIFT_CONST(3)
#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_RANGE                      3:3
#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_WOFFSET                    0x0
#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_ENABLE                     _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_SHIFT                      _MK_SHIFT_CONST(4)
#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_RANGE                      4:4
#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_WOFFSET                    0x0
#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_ENABLE                     _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_E_ACT_REQ_SHIFT                      _MK_SHIFT_CONST(5)
#define DC_CMD_STATE_CONTROL_0_WIN_E_ACT_REQ_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_E_ACT_REQ_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_E_ACT_REQ_RANGE                      5:5
#define DC_CMD_STATE_CONTROL_0_WIN_E_ACT_REQ_WOFFSET                    0x0
#define DC_CMD_STATE_CONTROL_0_WIN_E_ACT_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_E_ACT_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_E_ACT_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_E_ACT_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_E_ACT_REQ_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_E_ACT_REQ_ENABLE                     _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_F_ACT_REQ_SHIFT                      _MK_SHIFT_CONST(6)
#define DC_CMD_STATE_CONTROL_0_WIN_F_ACT_REQ_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_F_ACT_REQ_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_F_ACT_REQ_RANGE                      6:6
#define DC_CMD_STATE_CONTROL_0_WIN_F_ACT_REQ_WOFFSET                    0x0
#define DC_CMD_STATE_CONTROL_0_WIN_F_ACT_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_F_ACT_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_F_ACT_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_F_ACT_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_F_ACT_REQ_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_F_ACT_REQ_ENABLE                     _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_SHIFT                     _MK_SHIFT_CONST(7)
#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_SHIFT)
#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_RANGE                     7:7
#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_WOFFSET                   0x0
#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_DISABLE                   _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_ENABLE                    _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_SHIFT                     _MK_SHIFT_CONST(8)
#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_SHIFT)
#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_RANGE                     8:8
#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_WOFFSET                   0x0
#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_DISABLE                   _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_ENABLE                    _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_SHIFT                       _MK_SHIFT_CONST(9)
#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_RANGE                       9:9
#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_WOFFSET                     0x0
#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_SHIFT                       _MK_SHIFT_CONST(10)
#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_RANGE                       10:10
#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_WOFFSET                     0x0
#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_SHIFT                       _MK_SHIFT_CONST(11)
#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_RANGE                       11:11
#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_WOFFSET                     0x0
#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_SHIFT                       _MK_SHIFT_CONST(12)
#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_RANGE                       12:12
#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_WOFFSET                     0x0
#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_E_UPDATE_SHIFT                       _MK_SHIFT_CONST(13)
#define DC_CMD_STATE_CONTROL_0_WIN_E_UPDATE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_E_UPDATE_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_E_UPDATE_RANGE                       13:13
#define DC_CMD_STATE_CONTROL_0_WIN_E_UPDATE_WOFFSET                     0x0
#define DC_CMD_STATE_CONTROL_0_WIN_E_UPDATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_E_UPDATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_E_UPDATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_E_UPDATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_E_UPDATE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_E_UPDATE_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_WIN_F_UPDATE_SHIFT                       _MK_SHIFT_CONST(14)
#define DC_CMD_STATE_CONTROL_0_WIN_F_UPDATE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_F_UPDATE_SHIFT)
#define DC_CMD_STATE_CONTROL_0_WIN_F_UPDATE_RANGE                       14:14
#define DC_CMD_STATE_CONTROL_0_WIN_F_UPDATE_WOFFSET                     0x0
#define DC_CMD_STATE_CONTROL_0_WIN_F_UPDATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_F_UPDATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_WIN_F_UPDATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_F_UPDATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_WIN_F_UPDATE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_WIN_F_UPDATE_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_SHIFT                      _MK_SHIFT_CONST(15)
#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_SHIFT)
#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_RANGE                      15:15
#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_WOFFSET                    0x0
#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_ENABLE                     _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_COMMON_ACT_REQ_SHIFT                     _MK_SHIFT_CONST(16)
#define DC_CMD_STATE_CONTROL_0_COMMON_ACT_REQ_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_COMMON_ACT_REQ_SHIFT)
#define DC_CMD_STATE_CONTROL_0_COMMON_ACT_REQ_RANGE                     16:16
#define DC_CMD_STATE_CONTROL_0_COMMON_ACT_REQ_WOFFSET                   0x0
#define DC_CMD_STATE_CONTROL_0_COMMON_ACT_REQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_COMMON_ACT_REQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_COMMON_ACT_REQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_COMMON_ACT_REQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_COMMON_ACT_REQ_DISABLE                   _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_COMMON_ACT_REQ_ENABLE                    _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_COMMON_UPDATE_SHIFT                      _MK_SHIFT_CONST(17)
#define DC_CMD_STATE_CONTROL_0_COMMON_UPDATE_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_COMMON_UPDATE_SHIFT)
#define DC_CMD_STATE_CONTROL_0_COMMON_UPDATE_RANGE                      17:17
#define DC_CMD_STATE_CONTROL_0_COMMON_UPDATE_WOFFSET                    0x0
#define DC_CMD_STATE_CONTROL_0_COMMON_UPDATE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_COMMON_UPDATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_COMMON_UPDATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_COMMON_UPDATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_COMMON_UPDATE_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_COMMON_UPDATE_ENABLE                     _MK_ENUM_CONST(1)

#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_SHIFT                        _MK_SHIFT_CONST(24)
#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_SHIFT)
#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_RANGE                        24:24
#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_WOFFSET                      0x0
#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_ENABLE                       _MK_ENUM_CONST(1)


// Register DC_CMD_DISPLAY_WINDOW_HEADER_0
#define DC_CMD_DISPLAY_WINDOW_HEADER_0                  _MK_ADDR_CONST(0x42)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_SECURE                   0x0
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_SCR                      0
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WORD_COUNT                       0x1
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_RESET_MASK                       _MK_MASK_CONST(0x3f0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_READ_MASK                        _MK_MASK_CONST(0x3f0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WRITE_MASK                       _MK_MASK_CONST(0x3f0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_SHIFT                    _MK_SHIFT_CONST(4)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_SHIFT)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_RANGE                    4:4
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_WOFFSET                  0x0
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_SHIFT                    _MK_SHIFT_CONST(5)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_SHIFT)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_RANGE                    5:5
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_WOFFSET                  0x0
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_SHIFT                    _MK_SHIFT_CONST(6)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_SHIFT)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_RANGE                    6:6
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_WOFFSET                  0x0
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_SHIFT                    _MK_SHIFT_CONST(7)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_SHIFT)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_RANGE                    7:7
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_WOFFSET                  0x0
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_E_SELECT_SHIFT                    _MK_SHIFT_CONST(8)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_E_SELECT_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_E_SELECT_SHIFT)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_E_SELECT_RANGE                    8:8
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_E_SELECT_WOFFSET                  0x0
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_E_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_E_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_E_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_E_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_E_SELECT_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_E_SELECT_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_F_SELECT_SHIFT                    _MK_SHIFT_CONST(9)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_F_SELECT_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_F_SELECT_SHIFT)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_F_SELECT_RANGE                    9:9
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_F_SELECT_WOFFSET                  0x0
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_F_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_F_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_F_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_F_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_F_SELECT_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_F_SELECT_ENABLE                   _MK_ENUM_CONST(1)


// Register DC_CMD_WIN_T_STATE_CONTROL_0
#define DC_CMD_WIN_T_STATE_CONTROL_0                    _MK_ADDR_CONST(0x44)
#define DC_CMD_WIN_T_STATE_CONTROL_0_SECURE                     0x0
#define DC_CMD_WIN_T_STATE_CONTROL_0_SCR                        0
#define DC_CMD_WIN_T_STATE_CONTROL_0_WORD_COUNT                         0x1
#define DC_CMD_WIN_T_STATE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_T_STATE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_SHIFT)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_RANGE                        0:0
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_WOFFSET                      0x0
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_ENABLE                       _MK_ENUM_CONST(1)

#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_SHIFT                 _MK_SHIFT_CONST(8)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_SHIFT)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_RANGE                 8:8
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_WOFFSET                       0x0
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_DISABLE                       _MK_ENUM_CONST(0)
#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_ENABLE                        _MK_ENUM_CONST(1)


// Register DC_CMD_SECURE_CONTROL_0
#define DC_CMD_SECURE_CONTROL_0                 _MK_ADDR_CONST(0x45)
#define DC_CMD_SECURE_CONTROL_0_SECURE                  0x0
#define DC_CMD_SECURE_CONTROL_0_SCR                     0
#define DC_CMD_SECURE_CONTROL_0_WORD_COUNT                      0x1
#define DC_CMD_SECURE_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1fb06)
#define DC_CMD_SECURE_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1fb06)
#define DC_CMD_SECURE_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1fb06)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_SHIFT                        _MK_SHIFT_CONST(1)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_SHIFT)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_RANGE                        1:1
#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_WOFFSET                      0x0
#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_INIT_ENUM                    DISABLE
#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_ENABLE                       _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_SHIFT                        _MK_SHIFT_CONST(2)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_SHIFT)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_RANGE                        2:2
#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_WOFFSET                      0x0
#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_INIT_ENUM                    DISABLE
#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_ENABLE                       _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_SHIFT                  _MK_SHIFT_CONST(8)
#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_SHIFT)
#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_RANGE                  8:8
#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_WOFFSET                        0x0
#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_INIT_ENUM                      ASSEMBLY
#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_ASSEMBLY                       _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_ACTIVE                 _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_SHIFT                   _MK_SHIFT_CONST(9)
#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_SHIFT)
#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_RANGE                   9:9
#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_WOFFSET                 0x0
#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_INIT_ENUM                       ASSEMBLY
#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_ASSEMBLY                        _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_ACTIVE                  _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_SHIFT                       _MK_SHIFT_CONST(11)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_SHIFT)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_RANGE                       11:11
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_WOFFSET                     0x0
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_INIT_ENUM                   DISABLE
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_SHIFT                       _MK_SHIFT_CONST(12)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_SHIFT)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_RANGE                       12:12
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_WOFFSET                     0x0
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_INIT_ENUM                   DISABLE
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_SHIFT                       _MK_SHIFT_CONST(13)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_SHIFT)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_RANGE                       13:13
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_WOFFSET                     0x0
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_INIT_ENUM                   DISABLE
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIC_PROTECT_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_SHIFT                       _MK_SHIFT_CONST(14)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_SHIFT)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_RANGE                       14:14
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_WOFFSET                     0x0
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_INIT_ENUM                   DISABLE
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_DSID_PROTECT_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_SHIFT                        _MK_SHIFT_CONST(15)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_SHIFT)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_RANGE                        15:15
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_WOFFSET                      0x0
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_INIT_ENUM                    DISABLE
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_ENABLE                       _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_SHIFT                       _MK_SHIFT_CONST(16)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_SHIFT)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_RANGE                       16:16
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_WOFFSET                     0x0
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_INIT_ENUM                   DISABLE
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR1_PROTECT_ENABLE                      _MK_ENUM_CONST(1)


// Register DC_CMD_REG_ACCESS_CONTROL_0
#define DC_CMD_REG_ACCESS_CONTROL_0                     _MK_ADDR_CONST(0x46)
#define DC_CMD_REG_ACCESS_CONTROL_0_SECURE                      0x0
#define DC_CMD_REG_ACCESS_CONTROL_0_SCR                         0
#define DC_CMD_REG_ACCESS_CONTROL_0_WORD_COUNT                  0x1
#define DC_CMD_REG_ACCESS_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x7fff)
#define DC_CMD_REG_ACCESS_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x8000ffff)
#define DC_CMD_REG_ACCESS_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_ACCESS_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_ACCESS_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x8000ffff)
#define DC_CMD_REG_ACCESS_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x8000ffff)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_VAL_FIELD                     _MK_FIELD_CONST(0x7fff, DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_VAL_SHIFT)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_VAL_RANGE                     14:0
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_VAL_WOFFSET                   0x0
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_VAL_DEFAULT                   _MK_MASK_CONST(0x7fff)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_SHIFT                 _MK_SHIFT_CONST(15)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_SHIFT)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_RANGE                 15:15
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_WOFFSET                       0x0
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_INIT_ENUM                     NONE
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_NONE                  _MK_ENUM_CONST(0)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_PENDING                       _MK_ENUM_CONST(1)
#define DC_CMD_REG_ACCESS_CONTROL_0_TMOUT_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_SHIFT                       _MK_SHIFT_CONST(31)
#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_SHIFT)
#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_RANGE                       31:31
#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_WOFFSET                     0x0
#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_INIT_ENUM                   NONE
#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_NONE                        _MK_ENUM_CONST(0)
#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_PENDING                     _MK_ENUM_CONST(1)
#define DC_CMD_REG_ACCESS_CONTROL_0_WINDOW_ACCESS_VIOLATION_CLEAR                       _MK_ENUM_CONST(1)


// Register DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0                       _MK_ADDR_CONST(0x47)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_SECURE                        0x0
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_SCR                   0
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_WORD_COUNT                    0x1
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_READ_MASK                     _MK_MASK_CONST(0x30fffff)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_OFFSET_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_OFFSET_FIELD                  _MK_FIELD_CONST(0xfffff, DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_OFFSET_SHIFT)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_OFFSET_RANGE                  19:0
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_OFFSET_WOFFSET                        0x0
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_OFFSET_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_OFFSET_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_OFFSET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_OFFSET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_COR_SHIFT                     _MK_SHIFT_CONST(24)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_COR_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_COR_SHIFT)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_COR_RANGE                     24:24
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_COR_WOFFSET                   0x0
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_COR_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_COR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_COR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_COR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_COR_CLASS                     _MK_ENUM_CONST(0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_COR_REGISTER                  _MK_ENUM_CONST(1)

#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RWN_SHIFT                     _MK_SHIFT_CONST(25)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RWN_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RWN_SHIFT)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RWN_RANGE                     25:25
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RWN_WOFFSET                   0x0
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RWN_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RWN_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RWN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RWN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RWN_WRITE                     _MK_ENUM_CONST(0)
#define DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0_RWN_READ                      _MK_ENUM_CONST(1)


// Register DC_CMD_REG_PFE_DEBUG_0
#define DC_CMD_REG_PFE_DEBUG_0                  _MK_ADDR_CONST(0x48)
#define DC_CMD_REG_PFE_DEBUG_0_SECURE                   0x0
#define DC_CMD_REG_PFE_DEBUG_0_SCR                      0
#define DC_CMD_REG_PFE_DEBUG_0_WORD_COUNT                       0x1
#define DC_CMD_REG_PFE_DEBUG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_READ_MASK                        _MK_MASK_CONST(0xffffeff)
#define DC_CMD_REG_PFE_DEBUG_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_FIELD                    _MK_FIELD_CONST(0x7, DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_RANGE                    2:0
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_WOFFSET                  0x0
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_IDLE                     _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_CLRFIFO                  _MK_ENUM_CONST(1)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_REQ                      _MK_ENUM_CONST(2)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_WAIT_REQRST                      _MK_ENUM_CONST(3)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_WAIT_RESP                        _MK_ENUM_CONST(4)
#define DC_CMD_REG_PFE_DEBUG_0_HCOUTSM_WAIT_REQ                 _MK_ENUM_CONST(5)

#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_SHIFT                     _MK_SHIFT_CONST(3)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_FIELD                     _MK_FIELD_CONST(0xf, DC_CMD_REG_PFE_DEBUG_0_HCTLSM_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_RANGE                     6:3
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_WOFFSET                   0x0
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_IDLE                      _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_CTXACK                    _MK_ENUM_CONST(1)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_REGRD                     _MK_ENUM_CONST(2)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_RDRESP                    _MK_ENUM_CONST(3)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_REGWR                     _MK_ENUM_CONST(4)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_UPD                       _MK_ENUM_CONST(5)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_UPD_ACK                   _MK_ENUM_CONST(6)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_ACT                       _MK_ENUM_CONST(7)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_HACT_ACK                  _MK_ENUM_CONST(8)
#define DC_CMD_REG_PFE_DEBUG_0_HCTLSM_VACT                      _MK_ENUM_CONST(9)

#define DC_CMD_REG_PFE_DEBUG_0_RESPFIFO_SPACE_AVAIL_SHIFT                       _MK_SHIFT_CONST(7)
#define DC_CMD_REG_PFE_DEBUG_0_RESPFIFO_SPACE_AVAIL_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_RESPFIFO_SPACE_AVAIL_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_RESPFIFO_SPACE_AVAIL_RANGE                       7:7
#define DC_CMD_REG_PFE_DEBUG_0_RESPFIFO_SPACE_AVAIL_WOFFSET                     0x0
#define DC_CMD_REG_PFE_DEBUG_0_RESPFIFO_SPACE_AVAIL_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_RESPFIFO_SPACE_AVAIL_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_RESPFIFO_SPACE_AVAIL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_RESPFIFO_SPACE_AVAIL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_RESPFIFO_SPACE_AVAIL_NO                  _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_RESPFIFO_SPACE_AVAIL_YES                 _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_RESP_READY_SHIFT                 _MK_SHIFT_CONST(9)
#define DC_CMD_REG_PFE_DEBUG_0_RESP_READY_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_RESP_READY_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_RESP_READY_RANGE                 9:9
#define DC_CMD_REG_PFE_DEBUG_0_RESP_READY_WOFFSET                       0x0
#define DC_CMD_REG_PFE_DEBUG_0_RESP_READY_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_RESP_READY_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_RESP_READY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_RESP_READY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_RESP_READY_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_RESP_READY_YES                   _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_SHIFT                 _MK_SHIFT_CONST(10)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_RANGE                 10:10
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_WOFFSET                       0x0
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_YES                   _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_LAST_SHIFT                    _MK_SHIFT_CONST(11)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_LAST_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_LAST_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_LAST_RANGE                    11:11
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_LAST_WOFFSET                  0x0
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_LAST_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_LAST_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_LAST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_LAST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_LAST_NO                       _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_ALIVE_LAST_YES                      _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_IHUB_REQFIFO_WR_BUSY_SHIFT                       _MK_SHIFT_CONST(12)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_REQFIFO_WR_BUSY_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_IHUB_REQFIFO_WR_BUSY_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_REQFIFO_WR_BUSY_RANGE                       12:12
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_REQFIFO_WR_BUSY_WOFFSET                     0x0
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_REQFIFO_WR_BUSY_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_REQFIFO_WR_BUSY_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_REQFIFO_WR_BUSY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_REQFIFO_WR_BUSY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_REQFIFO_WR_BUSY_NO                  _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_REQFIFO_WR_BUSY_YES                 _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_IHUB_RESPFIFO_RD_REQ_SHIFT                       _MK_SHIFT_CONST(13)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_RESPFIFO_RD_REQ_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_IHUB_RESPFIFO_RD_REQ_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_RESPFIFO_RD_REQ_RANGE                       13:13
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_RESPFIFO_RD_REQ_WOFFSET                     0x0
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_RESPFIFO_RD_REQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_RESPFIFO_RD_REQ_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_RESPFIFO_RD_REQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_RESPFIFO_RD_REQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_RESPFIFO_RD_REQ_NO                  _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_IHUB_RESPFIFO_RD_REQ_YES                 _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_SHIFT                 _MK_SHIFT_CONST(14)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_RANGE                 14:14
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_WOFFSET                       0x0
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_YES                   _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_LAST_SHIFT                    _MK_SHIFT_CONST(15)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_LAST_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_LAST_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_LAST_RANGE                    15:15
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_LAST_WOFFSET                  0x0
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_LAST_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_LAST_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_LAST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_LAST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_LAST_NO                       _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_ALIVE_LAST_YES                      _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_COMP_REQFIFO_WR_BUSY_SHIFT                       _MK_SHIFT_CONST(16)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_REQFIFO_WR_BUSY_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_COMP_REQFIFO_WR_BUSY_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_REQFIFO_WR_BUSY_RANGE                       16:16
#define DC_CMD_REG_PFE_DEBUG_0_COMP_REQFIFO_WR_BUSY_WOFFSET                     0x0
#define DC_CMD_REG_PFE_DEBUG_0_COMP_REQFIFO_WR_BUSY_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_REQFIFO_WR_BUSY_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_REQFIFO_WR_BUSY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_REQFIFO_WR_BUSY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_REQFIFO_WR_BUSY_NO                  _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_REQFIFO_WR_BUSY_YES                 _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_COMP_RESPFIFO_RD_REQ_SHIFT                       _MK_SHIFT_CONST(17)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_RESPFIFO_RD_REQ_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_COMP_RESPFIFO_RD_REQ_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_RESPFIFO_RD_REQ_RANGE                       17:17
#define DC_CMD_REG_PFE_DEBUG_0_COMP_RESPFIFO_RD_REQ_WOFFSET                     0x0
#define DC_CMD_REG_PFE_DEBUG_0_COMP_RESPFIFO_RD_REQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_RESPFIFO_RD_REQ_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_RESPFIFO_RD_REQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_RESPFIFO_RD_REQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_RESPFIFO_RD_REQ_NO                  _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_COMP_RESPFIFO_RD_REQ_YES                 _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_SHIFT                 _MK_SHIFT_CONST(18)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_RANGE                 18:18
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_WOFFSET                       0x0
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_YES                   _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_LAST_SHIFT                    _MK_SHIFT_CONST(19)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_LAST_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_LAST_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_LAST_RANGE                    19:19
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_LAST_WOFFSET                  0x0
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_LAST_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_LAST_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_LAST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_LAST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_LAST_NO                       _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_ALIVE_LAST_YES                      _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_DSC0_REQFIFO_WR_BUSY_SHIFT                       _MK_SHIFT_CONST(20)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_REQFIFO_WR_BUSY_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_DSC0_REQFIFO_WR_BUSY_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_REQFIFO_WR_BUSY_RANGE                       20:20
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_REQFIFO_WR_BUSY_WOFFSET                     0x0
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_REQFIFO_WR_BUSY_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_REQFIFO_WR_BUSY_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_REQFIFO_WR_BUSY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_REQFIFO_WR_BUSY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_REQFIFO_WR_BUSY_NO                  _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_REQFIFO_WR_BUSY_YES                 _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_DSC0_RESPFIFO_RD_REQ_SHIFT                       _MK_SHIFT_CONST(21)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_RESPFIFO_RD_REQ_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_0_DSC0_RESPFIFO_RD_REQ_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_RESPFIFO_RD_REQ_RANGE                       21:21
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_RESPFIFO_RD_REQ_WOFFSET                     0x0
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_RESPFIFO_RD_REQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_RESPFIFO_RD_REQ_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_RESPFIFO_RD_REQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_RESPFIFO_RD_REQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_RESPFIFO_RD_REQ_NO                  _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_0_DSC0_RESPFIFO_RD_REQ_YES                 _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_0_HFLIP_CHN_MASK_SHIFT                     _MK_SHIFT_CONST(22)
#define DC_CMD_REG_PFE_DEBUG_0_HFLIP_CHN_MASK_FIELD                     _MK_FIELD_CONST(0x3f, DC_CMD_REG_PFE_DEBUG_0_HFLIP_CHN_MASK_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_0_HFLIP_CHN_MASK_RANGE                     27:22
#define DC_CMD_REG_PFE_DEBUG_0_HFLIP_CHN_MASK_WOFFSET                   0x0
#define DC_CMD_REG_PFE_DEBUG_0_HFLIP_CHN_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HFLIP_CHN_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HFLIP_CHN_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_0_HFLIP_CHN_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_REG_PFE_DEBUG_CHN_MASK_0
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0                 _MK_ADDR_CONST(0x49)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SECURE                  0x0
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SCR                     0
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_WORD_COUNT                      0x1
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_RESET_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_READ_MASK                       _MK_MASK_CONST(0x7fffffff)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_CHN_MASK_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_CHN_MASK_FIELD                       _MK_FIELD_CONST(0x3fff, DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_CHN_MASK_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_CHN_MASK_RANGE                       13:0
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_CHN_MASK_WOFFSET                     0x0
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_CHN_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_CHN_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_CHN_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_CHN_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_REQ_MASK_SHIFT                       _MK_SHIFT_CONST(14)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_REQ_MASK_FIELD                       _MK_FIELD_CONST(0x3fff, DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_REQ_MASK_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_REQ_MASK_RANGE                       27:14
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_REQ_MASK_WOFFSET                     0x0
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_REQ_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_REQ_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_REQ_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_CURR_VFLIP_REQ_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SUSP_REQ_SHIFT                  _MK_SHIFT_CONST(28)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SUSP_REQ_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SUSP_REQ_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SUSP_REQ_RANGE                  28:28
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SUSP_REQ_WOFFSET                        0x0
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SUSP_REQ_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SUSP_REQ_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SUSP_REQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SUSP_REQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SUSP_REQ_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SUSP_REQ_YES                    _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_HUBCLK_EN_SHIFT                    _MK_SHIFT_CONST(29)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_HUBCLK_EN_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_HUBCLK_EN_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_HUBCLK_EN_RANGE                    29:29
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_HUBCLK_EN_WOFFSET                  0x0
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_HUBCLK_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_HUBCLK_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_HUBCLK_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_HUBCLK_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_HUBCLK_EN_NO                       _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_HUBCLK_EN_YES                      _MK_ENUM_CONST(1)

#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_DISPCLK_COMP_EN_SHIFT                      _MK_SHIFT_CONST(30)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_DISPCLK_COMP_EN_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_DISPCLK_COMP_EN_SHIFT)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_DISPCLK_COMP_EN_RANGE                      30:30
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_DISPCLK_COMP_EN_WOFFSET                    0x0
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_DISPCLK_COMP_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_DISPCLK_COMP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_DISPCLK_COMP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_DISPCLK_COMP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_DISPCLK_COMP_EN_NO                 _MK_ENUM_CONST(0)
#define DC_CMD_REG_PFE_DEBUG_CHN_MASK_0_SLCG_DISPCLK_COMP_EN_YES                        _MK_ENUM_CONST(1)

#define NV_DISPLAY_WIN_D_INCR_SYNCPT_NB_CONDS   6

// Register DC_CMD_WIN_D_INCR_SYNCPT_0
#define DC_CMD_WIN_D_INCR_SYNCPT_0                      _MK_ADDR_CONST(0x4c)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_SECURE                       0x0
#define DC_CMD_WIN_D_INCR_SYNCPT_0_SCR                  0
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WORD_COUNT                   0x1
#define DC_CMD_WIN_D_INCR_SYNCPT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_RESET_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_READ_MASK                    _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WRITE_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_SHIFT                     _MK_SHIFT_CONST(10)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_FIELD                     _MK_FIELD_CONST(0xff, DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_SHIFT)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_RANGE                     17:10
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_WOFFSET                   0x0
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_IMMEDIATE                 _MK_ENUM_CONST(0)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_OP_DONE                   _MK_ENUM_CONST(1)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_RD_DONE                   _MK_ENUM_CONST(2)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_REG_WR_SAFE                       _MK_ENUM_CONST(3)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_ENGINE_IDLE                       _MK_ENUM_CONST(4)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_LINE_FLIPPED                      _MK_ENUM_CONST(5)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_6                    _MK_ENUM_CONST(6)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_7                    _MK_ENUM_CONST(7)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_8                    _MK_ENUM_CONST(8)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_9                    _MK_ENUM_CONST(9)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_10                   _MK_ENUM_CONST(10)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_11                   _MK_ENUM_CONST(11)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_12                   _MK_ENUM_CONST(12)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_13                   _MK_ENUM_CONST(13)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_14                   _MK_ENUM_CONST(14)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_15                   _MK_ENUM_CONST(15)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_16                   _MK_ENUM_CONST(16)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_17                   _MK_ENUM_CONST(17)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_18                   _MK_ENUM_CONST(18)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_19                   _MK_ENUM_CONST(19)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_20                   _MK_ENUM_CONST(20)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_21                   _MK_ENUM_CONST(21)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_22                   _MK_ENUM_CONST(22)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_23                   _MK_ENUM_CONST(23)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_24                   _MK_ENUM_CONST(24)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_25                   _MK_ENUM_CONST(25)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_26                   _MK_ENUM_CONST(26)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_27                   _MK_ENUM_CONST(27)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_28                   _MK_ENUM_CONST(28)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_29                   _MK_ENUM_CONST(29)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_30                   _MK_ENUM_CONST(30)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_31                   _MK_ENUM_CONST(31)

#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_FIELD                     _MK_FIELD_CONST(0x3ff, DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_SHIFT)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_RANGE                     9:0
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_WOFFSET                   0x0
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0                        _MK_ADDR_CONST(0x4d)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_SECURE                         0x0
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_SCR                    0
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_RESET_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_READ_MASK                      _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_SHIFT                       _MK_SHIFT_CONST(8)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_SHIFT)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_RANGE                       8:8
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_WOFFSET                     0x0
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_SHIFT)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_RANGE                     0:0
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_WOFFSET                   0x0
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0                        _MK_ADDR_CONST(0x4e)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_SECURE                         0x0
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_SCR                    0
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_SHIFT)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_RANGE                        31:0
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_WOFFSET                      0x0
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 79 [0x4f]

// Reserved address 80 [0x50]

// Reserved address 81 [0x51]

// Reserved address 82 [0x52]

// Reserved address 83 [0x53]

// Register DC_CMD_POSTCOMP_HEAD_CAPA_0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0                     _MK_ADDR_CONST(0x50)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SECURE                      0x0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCR                         0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_WORD_COUNT                  0x1
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_RESET_MASK                  _MK_MASK_CONST(0x1ff)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_READ_MASK                   _MK_MASK_CONST(0x1ff)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_RANGE                        0:0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_WOFFSET                      0x0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_FALSE                        _MK_ENUM_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_TRUE                 _MK_ENUM_CONST(1)

#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_HAS_YUV422_SHIFT                     _MK_SHIFT_CONST(1)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_HAS_YUV422_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_HAS_YUV422_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_HAS_YUV422_RANGE                     1:1
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_HAS_YUV422_WOFFSET                   0x0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_HAS_YUV422_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_HAS_YUV422_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_HAS_YUV422_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_HAS_YUV422_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_HAS_YUV422_FALSE                     _MK_ENUM_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_SCALER_HAS_YUV422_TRUE                      _MK_ENUM_CONST(1)

#define DC_CMD_POSTCOMP_HEAD_CAPA_0_HSAT_SHIFT                  _MK_SHIFT_CONST(2)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_HSAT_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_POSTCOMP_HEAD_CAPA_0_HSAT_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_HSAT_RANGE                  2:2
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_HSAT_WOFFSET                        0x0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_HSAT_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_HSAT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_HSAT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_HSAT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_HSAT_FALSE                  _MK_ENUM_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_HSAT_TRUE                   _MK_ENUM_CONST(1)

#define DC_CMD_POSTCOMP_HEAD_CAPA_0_OCSC_SHIFT                  _MK_SHIFT_CONST(3)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_OCSC_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_POSTCOMP_HEAD_CAPA_0_OCSC_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_OCSC_RANGE                  3:3
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_OCSC_WOFFSET                        0x0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_OCSC_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_OCSC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_OCSC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_OCSC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_OCSC_FALSE                  _MK_ENUM_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_OCSC_TRUE                   _MK_ENUM_CONST(1)

#define DC_CMD_POSTCOMP_HEAD_CAPA_0_YUV422_SHIFT                        _MK_SHIFT_CONST(4)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_YUV422_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_POSTCOMP_HEAD_CAPA_0_YUV422_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_YUV422_RANGE                        4:4
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_YUV422_WOFFSET                      0x0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_YUV422_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_YUV422_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_YUV422_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_YUV422_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_YUV422_FALSE                        _MK_ENUM_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_YUV422_TRUE                 _MK_ENUM_CONST(1)

#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_SHIFT                      _MK_SHIFT_CONST(5)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_FIELD                      _MK_FIELD_CONST(0x3, DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_RANGE                      6:5
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_WOFFSET                    0x0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_NONE                       _MK_ENUM_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_SIZE_257                   _MK_ENUM_CONST(1)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_TYPE_SIZE_1025                  _MK_ENUM_CONST(2)

#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_LOCATION_SHIFT                  _MK_SHIFT_CONST(7)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_LOCATION_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_LOCATION_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_LOCATION_RANGE                  7:7
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_LOCATION_WOFFSET                        0x0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_LOCATION_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_LOCATION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_LOCATION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_LOCATION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_LOCATION_EARLY                  _MK_ENUM_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_LUT_LOCATION_LATE                   _MK_ENUM_CONST(1)

#define DC_CMD_POSTCOMP_HEAD_CAPA_0_TZ_SHIFT                    _MK_SHIFT_CONST(8)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_TZ_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_POSTCOMP_HEAD_CAPA_0_TZ_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_TZ_RANGE                    8:8
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_TZ_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_TZ_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_TZ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_TZ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_TZ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_TZ_FALSE                    _MK_ENUM_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPA_0_TZ_TRUE                     _MK_ENUM_CONST(1)


// Register DC_CMD_POSTCOMP_HEAD_CAPB_0
#define DC_CMD_POSTCOMP_HEAD_CAPB_0                     _MK_ADDR_CONST(0x51)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_SECURE                      0x0
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_SCR                         0
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_WORD_COUNT                  0x1
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP444_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP444_FIELD                    _MK_FIELD_CONST(0xffff, DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP444_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP444_RANGE                    15:0
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP444_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP444_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP444_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP444_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP444_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP422_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP422_FIELD                    _MK_FIELD_CONST(0xffff, DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP422_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP422_RANGE                    31:16
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP422_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP422_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP422_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP422_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPB_0_MAX_PIXELS_5TAP422_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_CMD_POSTCOMP_HEAD_CAPC_0
#define DC_CMD_POSTCOMP_HEAD_CAPC_0                     _MK_ADDR_CONST(0x52)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_SECURE                      0x0
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_SCR                         0
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_WORD_COUNT                  0x1
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP444_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP444_FIELD                    _MK_FIELD_CONST(0xffff, DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP444_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP444_RANGE                    15:0
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP444_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP444_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP444_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP444_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP444_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP422_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP422_FIELD                    _MK_FIELD_CONST(0xffff, DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP422_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP422_RANGE                    31:16
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP422_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP422_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP422_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP422_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPC_0_MAX_PIXELS_3TAP422_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_CMD_POSTCOMP_HEAD_CAPD_0
#define DC_CMD_POSTCOMP_HEAD_CAPD_0                     _MK_ADDR_CONST(0x53)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_SECURE                      0x0
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_SCR                         0
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_WORD_COUNT                  0x1
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP444_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP444_FIELD                    _MK_FIELD_CONST(0xffff, DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP444_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP444_RANGE                    15:0
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP444_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP444_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP444_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP444_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP444_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP422_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP422_FIELD                    _MK_FIELD_CONST(0xffff, DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP422_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP422_RANGE                    31:16
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP422_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP422_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP422_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP422_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPD_0_MAX_PIXELS_2TAP422_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_CMD_POSTCOMP_HEAD_CAPE_0
#define DC_CMD_POSTCOMP_HEAD_CAPE_0                     _MK_ADDR_CONST(0x54)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_SECURE                      0x0
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_SCR                         0
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_WORD_COUNT                  0x1
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP444_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP444_FIELD                    _MK_FIELD_CONST(0xffff, DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP444_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP444_RANGE                    15:0
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP444_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP444_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP444_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP444_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP444_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP422_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP422_FIELD                    _MK_FIELD_CONST(0xffff, DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP422_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP422_RANGE                    31:16
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP422_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP422_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP422_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP422_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPE_0_MAX_PIXELS_1TAP422_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_CMD_POSTCOMP_HEAD_CAPF_0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0                     _MK_ADDR_CONST(0x55)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SECURE                      0x0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SCR                         0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_WORD_COUNT                  0x1
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_FULL_WIDTH_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_FULL_WIDTH_FIELD                    _MK_FIELD_CONST(0xf, DC_CMD_POSTCOMP_HEAD_CAPF_0_FULL_WIDTH_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_FULL_WIDTH_RANGE                    3:0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_FULL_WIDTH_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_FULL_WIDTH_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_FULL_WIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_FULL_WIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_FULL_WIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_POSTCOMP_HEAD_CAPF_0_UNIT_WIDTH_SHIFT                    _MK_SHIFT_CONST(4)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_UNIT_WIDTH_FIELD                    _MK_FIELD_CONST(0xf, DC_CMD_POSTCOMP_HEAD_CAPF_0_UNIT_WIDTH_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_UNIT_WIDTH_RANGE                    7:4
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_UNIT_WIDTH_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_UNIT_WIDTH_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_UNIT_WIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_UNIT_WIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_UNIT_WIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SCLR_WIDTH_SHIFT                    _MK_SHIFT_CONST(8)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SCLR_WIDTH_FIELD                    _MK_FIELD_CONST(0xf, DC_CMD_POSTCOMP_HEAD_CAPF_0_SCLR_WIDTH_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SCLR_WIDTH_RANGE                    11:8
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SCLR_WIDTH_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SCLR_WIDTH_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SCLR_WIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SCLR_WIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_SCLR_WIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_POSTCOMP_HEAD_CAPF_0_HSAT_WIDTH_SHIFT                    _MK_SHIFT_CONST(12)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_HSAT_WIDTH_FIELD                    _MK_FIELD_CONST(0xf, DC_CMD_POSTCOMP_HEAD_CAPF_0_HSAT_WIDTH_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_HSAT_WIDTH_RANGE                    15:12
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_HSAT_WIDTH_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_HSAT_WIDTH_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_HSAT_WIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_HSAT_WIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_HSAT_WIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_POSTCOMP_HEAD_CAPF_0_LUT_WIDTH_SHIFT                     _MK_SHIFT_CONST(16)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_LUT_WIDTH_FIELD                     _MK_FIELD_CONST(0xf, DC_CMD_POSTCOMP_HEAD_CAPF_0_LUT_WIDTH_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_LUT_WIDTH_RANGE                     19:16
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_LUT_WIDTH_WOFFSET                   0x0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_LUT_WIDTH_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_LUT_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_LUT_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_LUT_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OCSC_WIDTH_SHIFT                    _MK_SHIFT_CONST(20)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OCSC_WIDTH_FIELD                    _MK_FIELD_CONST(0xf, DC_CMD_POSTCOMP_HEAD_CAPF_0_OCSC_WIDTH_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OCSC_WIDTH_RANGE                    23:20
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OCSC_WIDTH_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OCSC_WIDTH_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OCSC_WIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OCSC_WIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OCSC_WIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OLPF_WIDTH_SHIFT                    _MK_SHIFT_CONST(24)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OLPF_WIDTH_FIELD                    _MK_FIELD_CONST(0xf, DC_CMD_POSTCOMP_HEAD_CAPF_0_OLPF_WIDTH_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OLPF_WIDTH_RANGE                    27:24
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OLPF_WIDTH_WOFFSET                  0x0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OLPF_WIDTH_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OLPF_WIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OLPF_WIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_OLPF_WIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_POSTCOMP_HEAD_CAPF_0_TZ_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_TZ_WIDTH_FIELD                      _MK_FIELD_CONST(0xf, DC_CMD_POSTCOMP_HEAD_CAPF_0_TZ_WIDTH_SHIFT)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_TZ_WIDTH_RANGE                      31:28
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_TZ_WIDTH_WOFFSET                    0x0
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_TZ_WIDTH_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_TZ_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_TZ_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_POSTCOMP_HEAD_CAPF_0_TZ_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_CMD_IHUB_COMMON_CAPA_0
#define DC_CMD_IHUB_COMMON_CAPA_0                       _MK_ADDR_CONST(0x60)
#define DC_CMD_IHUB_COMMON_CAPA_0_SECURE                        0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_SCR                   0
#define DC_CMD_IHUB_COMMON_CAPA_0_WORD_COUNT                    0x1
#define DC_CMD_IHUB_COMMON_CAPA_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_READ_MASK                     _MK_MASK_CONST(0xfdffffff)
#define DC_CMD_IHUB_COMMON_CAPA_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRIES_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRIES_FIELD                 _MK_FIELD_CONST(0xffff, DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRIES_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRIES_RANGE                 15:0
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRIES_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRIES_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRIES_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRIES_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRIES_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_SHIFT                     _MK_SHIFT_CONST(16)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_FIELD                     _MK_FIELD_CONST(0x3, DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_RANGE                     17:16
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_WOFFSET                   0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_SIZE_32B                  _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_SIZE_64B                  _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_SIZE_128B                 _MK_ENUM_CONST(2)
#define DC_CMD_IHUB_COMMON_CAPA_0_MEMPOOL_ENTRY_WIDTH_SIZE_256B                 _MK_ENUM_CONST(3)

#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ROTATION_SHIFT                        _MK_SHIFT_CONST(18)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ROTATION_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ROTATION_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ROTATION_RANGE                        18:18
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ROTATION_WOFFSET                      0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ROTATION_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ROTATION_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ROTATION_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ROTATION_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ROTATION_FALSE                        _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ROTATION_TRUE                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_PLANAR_SHIFT                  _MK_SHIFT_CONST(19)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_PLANAR_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_PLANAR_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_PLANAR_RANGE                  19:19
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_PLANAR_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_PLANAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_PLANAR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_PLANAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_PLANAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_PLANAR_FALSE                  _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_PLANAR_TRUE                   _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_VGA_SHIFT                     _MK_SHIFT_CONST(20)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_VGA_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_VGA_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_VGA_RANGE                     20:20
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_VGA_WOFFSET                   0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_VGA_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_VGA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_VGA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_VGA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_VGA_FALSE                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_VGA_TRUE                      _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MEMPOOL_COMPRESSION_SHIFT                     _MK_SHIFT_CONST(21)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MEMPOOL_COMPRESSION_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MEMPOOL_COMPRESSION_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MEMPOOL_COMPRESSION_RANGE                     21:21
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MEMPOOL_COMPRESSION_WOFFSET                   0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MEMPOOL_COMPRESSION_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MEMPOOL_COMPRESSION_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MEMPOOL_COMPRESSION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MEMPOOL_COMPRESSION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MEMPOOL_COMPRESSION_FALSE                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MEMPOOL_COMPRESSION_TRUE                      _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MSPG_SHIFT                    _MK_SHIFT_CONST(22)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MSPG_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MSPG_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MSPG_RANGE                    22:22
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MSPG_WOFFSET                  0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MSPG_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MSPG_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MSPG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MSPG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MSPG_FALSE                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MSPG_TRUE                     _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MCLK_SWITCH_SHIFT                     _MK_SHIFT_CONST(23)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MCLK_SWITCH_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MCLK_SWITCH_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MCLK_SWITCH_RANGE                     23:23
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MCLK_SWITCH_WOFFSET                   0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MCLK_SWITCH_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MCLK_SWITCH_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MCLK_SWITCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MCLK_SWITCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MCLK_SWITCH_FALSE                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_MCLK_SWITCH_TRUE                      _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ASR_SHIFT                     _MK_SHIFT_CONST(24)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ASR_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ASR_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ASR_RANGE                     24:24
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ASR_WOFFSET                   0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ASR_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ASR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ASR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ASR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ASR_FALSE                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_ASR_TRUE                      _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_LATENCY_EVENT_SHIFT                   _MK_SHIFT_CONST(26)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_LATENCY_EVENT_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_LATENCY_EVENT_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_LATENCY_EVENT_RANGE                   26:26
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_LATENCY_EVENT_WOFFSET                 0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_LATENCY_EVENT_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_LATENCY_EVENT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_LATENCY_EVENT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_LATENCY_EVENT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_LATENCY_EVENT_FALSE                   _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_LATENCY_EVENT_TRUE                    _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_TRUSTZONE_WINDOW_SHIFT                        _MK_SHIFT_CONST(27)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_TRUSTZONE_WINDOW_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_TRUSTZONE_WINDOW_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_TRUSTZONE_WINDOW_RANGE                        27:27
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_TRUSTZONE_WINDOW_WOFFSET                      0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_TRUSTZONE_WINDOW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_TRUSTZONE_WINDOW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_TRUSTZONE_WINDOW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_TRUSTZONE_WINDOW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_TRUSTZONE_WINDOW_FALSE                        _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_SUPPORT_TRUSTZONE_WINDOW_TRUE                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_SHIFT                  _MK_SHIFT_CONST(28)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_FIELD                  _MK_FIELD_CONST(0x3, DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_RANGE                  29:28
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_SIZE_16B                       _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_SIZE_32B                       _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_SIZE_64B                       _MK_ENUM_CONST(2)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_ROTATION_SIZE_128B                      _MK_ENUM_CONST(3)

#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_SHIFT                      _MK_SHIFT_CONST(30)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_FIELD                      _MK_FIELD_CONST(0x3, DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_RANGE                      31:30
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_WOFFSET                    0x0
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_SIZE_32B                   _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_SIZE_64B                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_SIZE_128B                  _MK_ENUM_CONST(2)
#define DC_CMD_IHUB_COMMON_CAPA_0_REQUEST_SIZE_PER_LINE_NON_ROTATION_SIZE_256B                  _MK_ENUM_CONST(3)


// Register DC_CMD_IHUB_COMMON_CAPB_0
#define DC_CMD_IHUB_COMMON_CAPB_0                       _MK_ADDR_CONST(0x61)
#define DC_CMD_IHUB_COMMON_CAPB_0_SECURE                        0x0
#define DC_CMD_IHUB_COMMON_CAPB_0_SCR                   0
#define DC_CMD_IHUB_COMMON_CAPB_0_WORD_COUNT                    0x1
#define DC_CMD_IHUB_COMMON_CAPB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define DC_CMD_IHUB_COMMON_CAPB_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PLANAR_ROTATION_THREAD_GROUPS_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PLANAR_ROTATION_THREAD_GROUPS_FIELD                       _MK_FIELD_CONST(0x3f, DC_CMD_IHUB_COMMON_CAPB_0_MAX_PLANAR_ROTATION_THREAD_GROUPS_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PLANAR_ROTATION_THREAD_GROUPS_RANGE                       5:0
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PLANAR_ROTATION_THREAD_GROUPS_WOFFSET                     0x0
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PLANAR_ROTATION_THREAD_GROUPS_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PLANAR_ROTATION_THREAD_GROUPS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PLANAR_ROTATION_THREAD_GROUPS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PLANAR_ROTATION_THREAD_GROUPS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_SEMI_PLANAR_ROTATION_THREAD_GROUPS_SHIFT                  _MK_SHIFT_CONST(6)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_SEMI_PLANAR_ROTATION_THREAD_GROUPS_FIELD                  _MK_FIELD_CONST(0x3f, DC_CMD_IHUB_COMMON_CAPB_0_MAX_SEMI_PLANAR_ROTATION_THREAD_GROUPS_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_SEMI_PLANAR_ROTATION_THREAD_GROUPS_RANGE                  11:6
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_SEMI_PLANAR_ROTATION_THREAD_GROUPS_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_SEMI_PLANAR_ROTATION_THREAD_GROUPS_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_SEMI_PLANAR_ROTATION_THREAD_GROUPS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_SEMI_PLANAR_ROTATION_THREAD_GROUPS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_SEMI_PLANAR_ROTATION_THREAD_GROUPS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS_SHIFT                  _MK_SHIFT_CONST(12)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS_FIELD                  _MK_FIELD_CONST(0x3f, DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS_RANGE                  17:12
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS_SHIFT                  _MK_SHIFT_CONST(18)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS_FIELD                  _MK_FIELD_CONST(0x3f, DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS_RANGE                  23:18
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_422_ROTATION_THREAD_GROUPS_SHIFT                   _MK_SHIFT_CONST(24)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_422_ROTATION_THREAD_GROUPS_FIELD                   _MK_FIELD_CONST(0x3f, DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_422_ROTATION_THREAD_GROUPS_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_422_ROTATION_THREAD_GROUPS_RANGE                   29:24
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_422_ROTATION_THREAD_GROUPS_WOFFSET                 0x0
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_422_ROTATION_THREAD_GROUPS_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_422_ROTATION_THREAD_GROUPS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_422_ROTATION_THREAD_GROUPS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPB_0_MAX_PACKED_422_ROTATION_THREAD_GROUPS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register DC_CMD_IHUB_COMMON_CAPC_0
#define DC_CMD_IHUB_COMMON_CAPC_0                       _MK_ADDR_CONST(0x62)
#define DC_CMD_IHUB_COMMON_CAPC_0_SECURE                        0x0
#define DC_CMD_IHUB_COMMON_CAPC_0_SCR                   0
#define DC_CMD_IHUB_COMMON_CAPC_0_WORD_COUNT                    0x1
#define DC_CMD_IHUB_COMMON_CAPC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_READ_MASK                     _MK_MASK_CONST(0x773)
#define DC_CMD_IHUB_COMMON_CAPC_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_FIELD                      _MK_FIELD_CONST(0x3, DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_RANGE                      1:0
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_WOFFSET                    0x0
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_SIZE_32B                   _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_SIZE_64B                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_SIZE_128B                  _MK_ENUM_CONST(2)
#define DC_CMD_IHUB_COMMON_CAPC_0_PITCH_REQUEST_SIZE_SIZE_256B                  _MK_ENUM_CONST(3)

#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_SHIFT                      _MK_SHIFT_CONST(4)
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_FIELD                      _MK_FIELD_CONST(0x7, DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_RANGE                      6:4
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_WOFFSET                    0x0
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_NONE                       _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_TWO                        _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_FOUR                       _MK_ENUM_CONST(2)
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_EIGHT                      _MK_ENUM_CONST(3)
#define DC_CMD_IHUB_COMMON_CAPC_0_MAX_LINES_BUFFERED_SIXTEEN                    _MK_ENUM_CONST(4)

#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_SHIFT                    _MK_SHIFT_CONST(8)
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_FIELD                    _MK_FIELD_CONST(0x7, DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_RANGE                    10:8
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_WOFFSET                  0x0
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_NONE                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_ONE                      _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_TWO                      _MK_ENUM_CONST(2)
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_THREE                    _MK_ENUM_CONST(3)
#define DC_CMD_IHUB_COMMON_CAPC_0_CLEAR_RECTANGLES_PER_SURFACE_FOUR                     _MK_ENUM_CONST(4)


// Register DC_CMD_IHUB_COMMON_CAPD_0
#define DC_CMD_IHUB_COMMON_CAPD_0                       _MK_ADDR_CONST(0x63)
#define DC_CMD_IHUB_COMMON_CAPD_0_SECURE                        0x0
#define DC_CMD_IHUB_COMMON_CAPD_0_SCR                   0
#define DC_CMD_IHUB_COMMON_CAPD_0_WORD_COUNT                    0x1
#define DC_CMD_IHUB_COMMON_CAPD_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPD_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPD_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPD_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPD_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_CAPD_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPD_0_REORDER_BUFFER_DEPTH_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_CAPD_0_REORDER_BUFFER_DEPTH_FIELD                    _MK_FIELD_CONST(0xffff, DC_CMD_IHUB_COMMON_CAPD_0_REORDER_BUFFER_DEPTH_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPD_0_REORDER_BUFFER_DEPTH_RANGE                    15:0
#define DC_CMD_IHUB_COMMON_CAPD_0_REORDER_BUFFER_DEPTH_WOFFSET                  0x0
#define DC_CMD_IHUB_COMMON_CAPD_0_REORDER_BUFFER_DEPTH_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPD_0_REORDER_BUFFER_DEPTH_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPD_0_REORDER_BUFFER_DEPTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPD_0_REORDER_BUFFER_DEPTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_IHUB_COMMON_CAPD_0_RDOUT_BUFFER_SIZE_SHIFT                       _MK_SHIFT_CONST(16)
#define DC_CMD_IHUB_COMMON_CAPD_0_RDOUT_BUFFER_SIZE_FIELD                       _MK_FIELD_CONST(0xffff, DC_CMD_IHUB_COMMON_CAPD_0_RDOUT_BUFFER_SIZE_SHIFT)
#define DC_CMD_IHUB_COMMON_CAPD_0_RDOUT_BUFFER_SIZE_RANGE                       31:16
#define DC_CMD_IHUB_COMMON_CAPD_0_RDOUT_BUFFER_SIZE_WOFFSET                     0x0
#define DC_CMD_IHUB_COMMON_CAPD_0_RDOUT_BUFFER_SIZE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPD_0_RDOUT_BUFFER_SIZE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPD_0_RDOUT_BUFFER_SIZE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CAPD_0_RDOUT_BUFFER_SIZE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_CMD_IHUB_COMMON_CONFIG_0
#define DC_CMD_IHUB_COMMON_CONFIG_0                     _MK_ADDR_CONST(0x67)
#define DC_CMD_IHUB_COMMON_CONFIG_0_SECURE                      0x0
#define DC_CMD_IHUB_COMMON_CONFIG_0_SCR                         0
#define DC_CMD_IHUB_COMMON_CONFIG_0_WORD_COUNT                  0x1
#define DC_CMD_IHUB_COMMON_CONFIG_0_RESET_VAL                   _MK_MASK_CONST(0x5)
#define DC_CMD_IHUB_COMMON_CONFIG_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define DC_CMD_IHUB_COMMON_CONFIG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CONFIG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CONFIG_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define DC_CMD_IHUB_COMMON_CONFIG_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_FIELD                    _MK_FIELD_CONST(0x7, DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_SHIFT)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_RANGE                    2:0
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_WOFFSET                  0x0
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_DEFAULT                  _MK_MASK_CONST(0x5)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_SIZE_1                   _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_SIZE_2                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_SIZE_4                   _MK_ENUM_CONST(2)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_SIZE_8                   _MK_ENUM_CONST(3)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_SIZE_16                  _MK_ENUM_CONST(4)
#define DC_CMD_IHUB_COMMON_CONFIG_0_REQUEST_BATCH_SIZE_SIZE_32                  _MK_ENUM_CONST(5)


// Register DC_CMD_IHUB_COMMON_MISC_CTL_0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0                   _MK_ADDR_CONST(0x68)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SECURE                    0x0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SCR                       0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_WORD_COUNT                        0x1
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_RESET_VAL                         _MK_MASK_CONST(0xc0000008)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_RESET_MASK                        _MK_MASK_CONST(0xc001002f)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_READ_MASK                         _MK_MASK_CONST(0xc001002f)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_WRITE_MASK                        _MK_MASK_CONST(0xc001002f)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_ASR_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_ASR_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_MISC_CTL_0_ASR_SHIFT)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_ASR_RANGE                 0:0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_ASR_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_ASR_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_ASR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_ASR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_ASR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_ASR_DISABLE                       _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_ASR_ENABLE                        _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SWITCH_SHIFT                      _MK_SHIFT_CONST(1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SWITCH_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_MISC_CTL_0_SWITCH_SHIFT)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SWITCH_RANGE                      1:1
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SWITCH_WOFFSET                    0x0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SWITCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SWITCH_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SWITCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SWITCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SWITCH_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_SWITCH_ENABLE                     _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_MISC_CTL_0_MSPG_SHIFT                        _MK_SHIFT_CONST(2)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_MSPG_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_MISC_CTL_0_MSPG_SHIFT)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_MSPG_RANGE                        2:2
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_MSPG_WOFFSET                      0x0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_MSPG_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_MSPG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_MSPG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_MSPG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_MSPG_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_MSPG_ENABLE                       _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_MISC_CTL_0_LATENCY_EVENT_SHIFT                       _MK_SHIFT_CONST(3)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_LATENCY_EVENT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_MISC_CTL_0_LATENCY_EVENT_SHIFT)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_LATENCY_EVENT_RANGE                       3:3
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_LATENCY_EVENT_WOFFSET                     0x0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_LATENCY_EVENT_DEFAULT                     _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_LATENCY_EVENT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_LATENCY_EVENT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_LATENCY_EVENT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_LATENCY_EVENT_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_LATENCY_EVENT_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_MISC_CTL_0_CRITICAL_SHIFT                    _MK_SHIFT_CONST(5)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_CRITICAL_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_MISC_CTL_0_CRITICAL_SHIFT)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_CRITICAL_RANGE                    5:5
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_CRITICAL_WOFFSET                  0x0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_CRITICAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_CRITICAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_CRITICAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_CRITICAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_CRITICAL_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_CRITICAL_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_MISC_CTL_0_NO_COMPRESS_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_NO_COMPRESS_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_MISC_CTL_0_NO_COMPRESS_SHIFT)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_NO_COMPRESS_RANGE                 16:16
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_NO_COMPRESS_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_NO_COMPRESS_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_NO_COMPRESS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_NO_COMPRESS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_NO_COMPRESS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_NO_COMPRESS_FALSE                 _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_NO_COMPRESS_TRUE                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_MISC_CTL_0_REQ_LIMIT_SHIFT                   _MK_SHIFT_CONST(30)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_REQ_LIMIT_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_MISC_CTL_0_REQ_LIMIT_SHIFT)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_REQ_LIMIT_RANGE                   30:30
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_REQ_LIMIT_WOFFSET                 0x0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_REQ_LIMIT_DEFAULT                 _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_REQ_LIMIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_REQ_LIMIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_REQ_LIMIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_REQ_LIMIT_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_REQ_LIMIT_ENABLE                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_MISC_CTL_0_FETCH_METER_SHIFT                 _MK_SHIFT_CONST(31)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_FETCH_METER_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_MISC_CTL_0_FETCH_METER_SHIFT)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_FETCH_METER_RANGE                 31:31
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_FETCH_METER_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_FETCH_METER_DEFAULT                       _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_FETCH_METER_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_FETCH_METER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_FETCH_METER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_FETCH_METER_DISABLE                       _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_CTL_0_FETCH_METER_ENABLE                        _MK_ENUM_CONST(1)


// Register DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0                     _MK_ADDR_CONST(0x69)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_SECURE                      0x0
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_SCR                         0
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_WORD_COUNT                  0x1
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOP_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOP_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOP_SHIFT)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOP_RANGE                  0:0
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOP_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOP_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOP_DISABLE                        _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOP_ENABLE                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOPPED_SHIFT                       _MK_SHIFT_CONST(1)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOPPED_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOPPED_SHIFT)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOPPED_RANGE                       1:1
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOPPED_WOFFSET                     0x0
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOPPED_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOPPED_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOPPED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOPPED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOPPED_NO                  _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0_STOPPED_YES                 _MK_ENUM_CONST(1)


// Register DC_CMD_IHUB_COMMON_SPARE_0_0
#define DC_CMD_IHUB_COMMON_SPARE_0_0                    _MK_ADDR_CONST(0x70)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_SECURE                     0x0
#define DC_CMD_IHUB_COMMON_SPARE_0_0_SCR                        0
#define DC_CMD_IHUB_COMMON_SPARE_0_0_WORD_COUNT                         0x1
#define DC_CMD_IHUB_COMMON_SPARE_0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_REG_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_REG_FIELD                  _MK_FIELD_CONST(0xffffffff, DC_CMD_IHUB_COMMON_SPARE_0_0_REG_SHIFT)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_REG_RANGE                  31:0
#define DC_CMD_IHUB_COMMON_SPARE_0_0_REG_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_SPARE_0_0_REG_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_REG_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_REG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_SPARE_0_0_REG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_CMD_IHUB_COMMON_SPARE_1_0
#define DC_CMD_IHUB_COMMON_SPARE_1_0                    _MK_ADDR_CONST(0x71)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_SECURE                     0x0
#define DC_CMD_IHUB_COMMON_SPARE_1_0_SCR                        0
#define DC_CMD_IHUB_COMMON_SPARE_1_0_WORD_COUNT                         0x1
#define DC_CMD_IHUB_COMMON_SPARE_1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_REG_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_REG_FIELD                  _MK_FIELD_CONST(0xffffffff, DC_CMD_IHUB_COMMON_SPARE_1_0_REG_SHIFT)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_REG_RANGE                  31:0
#define DC_CMD_IHUB_COMMON_SPARE_1_0_REG_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_SPARE_1_0_REG_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_REG_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_REG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_SPARE_1_0_REG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_CMD_IHUB_COMMON_CGCTL_0
#define DC_CMD_IHUB_COMMON_CGCTL_0                      _MK_ADDR_CONST(0x72)
#define DC_CMD_IHUB_COMMON_CGCTL_0_SECURE                       0x0
#define DC_CMD_IHUB_COMMON_CGCTL_0_SCR                  0
#define DC_CMD_IHUB_COMMON_CGCTL_0_WORD_COUNT                   0x1
#define DC_CMD_IHUB_COMMON_CGCTL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CGCTL_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_CGCTL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CGCTL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CGCTL_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_CGCTL_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_CGCTL_0_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_CGCTL_0_VAL_FIELD                    _MK_FIELD_CONST(0xffffffff, DC_CMD_IHUB_COMMON_CGCTL_0_VAL_SHIFT)
#define DC_CMD_IHUB_COMMON_CGCTL_0_VAL_RANGE                    31:0
#define DC_CMD_IHUB_COMMON_CGCTL_0_VAL_WOFFSET                  0x0
#define DC_CMD_IHUB_COMMON_CGCTL_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CGCTL_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_CGCTL_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_CGCTL_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0                      _MK_ADDR_CONST(0x73)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_SECURE                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_SCR                  0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_WORD_COUNT                   0x1
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_SHIFT                 _MK_SHIFT_CONST(31)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_RANGE                 31:31
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_31_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_SHIFT                 _MK_SHIFT_CONST(30)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_RANGE                 30:30
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_30_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_SHIFT                 _MK_SHIFT_CONST(29)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_RANGE                 29:29
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_29_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_SHIFT                 _MK_SHIFT_CONST(28)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_RANGE                 28:28
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_28_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_SHIFT                 _MK_SHIFT_CONST(27)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_RANGE                 27:27
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_27_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_SHIFT                 _MK_SHIFT_CONST(26)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_RANGE                 26:26
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_26_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_SHIFT                 _MK_SHIFT_CONST(25)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_RANGE                 25:25
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_25_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_SHIFT                 _MK_SHIFT_CONST(24)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_RANGE                 24:24
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_24_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_SHIFT                 _MK_SHIFT_CONST(23)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_RANGE                 23:23
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_23_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_SHIFT                 _MK_SHIFT_CONST(22)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_RANGE                 22:22
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_22_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_SHIFT                 _MK_SHIFT_CONST(21)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_RANGE                 21:21
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_21_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_SHIFT                 _MK_SHIFT_CONST(20)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_RANGE                 20:20
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_20_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_SHIFT                 _MK_SHIFT_CONST(19)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_RANGE                 19:19
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_19_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_SHIFT                 _MK_SHIFT_CONST(18)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_RANGE                 18:18
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_18_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_SHIFT                 _MK_SHIFT_CONST(17)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_RANGE                 17:17
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_17_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_RANGE                 16:16
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_16_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_SHIFT                 _MK_SHIFT_CONST(15)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_RANGE                 15:15
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_15_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_SHIFT                 _MK_SHIFT_CONST(14)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_RANGE                 14:14
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_14_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_SHIFT                 _MK_SHIFT_CONST(13)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_RANGE                 13:13
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_13_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_SHIFT                 _MK_SHIFT_CONST(12)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_RANGE                 12:12
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_12_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_SHIFT                 _MK_SHIFT_CONST(11)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_RANGE                 11:11
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_11_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_SHIFT                 _MK_SHIFT_CONST(10)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_RANGE                 10:10
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_10_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_SHIFT                  _MK_SHIFT_CONST(9)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_RANGE                  9:9
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_9_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_SHIFT                  _MK_SHIFT_CONST(8)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_RANGE                  8:8
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_8_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_RANGE                  7:7
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_7_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_RANGE                  6:6
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_6_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_RANGE                  5:5
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_5_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_RANGE                  4:4
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_4_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_RANGE                  3:3
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_3_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_RANGE                  2:2
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_2_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_RANGE                  1:1
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_1_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_RANGE                  0:0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0_BIT_0_CLEAR                  _MK_ENUM_CONST(1)


// Register DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0                      _MK_ADDR_CONST(0x74)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_SECURE                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_SCR                  0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_WORD_COUNT                   0x1
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_SHIFT                 _MK_SHIFT_CONST(31)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_RANGE                 31:31
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_31_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_SHIFT                 _MK_SHIFT_CONST(30)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_RANGE                 30:30
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_30_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_SHIFT                 _MK_SHIFT_CONST(29)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_RANGE                 29:29
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_29_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_SHIFT                 _MK_SHIFT_CONST(28)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_RANGE                 28:28
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_28_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_SHIFT                 _MK_SHIFT_CONST(27)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_RANGE                 27:27
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_27_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_SHIFT                 _MK_SHIFT_CONST(26)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_RANGE                 26:26
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_26_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_SHIFT                 _MK_SHIFT_CONST(25)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_RANGE                 25:25
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_25_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_SHIFT                 _MK_SHIFT_CONST(24)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_RANGE                 24:24
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_24_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_SHIFT                 _MK_SHIFT_CONST(23)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_RANGE                 23:23
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_23_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_SHIFT                 _MK_SHIFT_CONST(22)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_RANGE                 22:22
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_22_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_SHIFT                 _MK_SHIFT_CONST(21)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_RANGE                 21:21
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_21_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_SHIFT                 _MK_SHIFT_CONST(20)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_RANGE                 20:20
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_20_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_SHIFT                 _MK_SHIFT_CONST(19)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_RANGE                 19:19
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_19_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_SHIFT                 _MK_SHIFT_CONST(18)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_RANGE                 18:18
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_18_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_SHIFT                 _MK_SHIFT_CONST(17)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_RANGE                 17:17
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_17_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_RANGE                 16:16
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_16_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_SHIFT                 _MK_SHIFT_CONST(15)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_RANGE                 15:15
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_15_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_SHIFT                 _MK_SHIFT_CONST(14)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_RANGE                 14:14
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_14_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_SHIFT                 _MK_SHIFT_CONST(13)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_RANGE                 13:13
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_13_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_SHIFT                 _MK_SHIFT_CONST(12)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_RANGE                 12:12
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_12_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_SHIFT                 _MK_SHIFT_CONST(11)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_RANGE                 11:11
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_11_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_SHIFT                 _MK_SHIFT_CONST(10)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_RANGE                 10:10
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_WOFFSET                       0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_NO                    _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_YES                   _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_10_CLEAR                 _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_SHIFT                  _MK_SHIFT_CONST(9)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_RANGE                  9:9
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_9_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_SHIFT                  _MK_SHIFT_CONST(8)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_RANGE                  8:8
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_8_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_RANGE                  7:7
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_7_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_RANGE                  6:6
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_6_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_RANGE                  5:5
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_5_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_RANGE                  4:4
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_4_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_RANGE                  3:3
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_3_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_RANGE                  2:2
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_2_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_RANGE                  1:1
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_1_CLEAR                  _MK_ENUM_CONST(1)

#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_SHIFT)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_RANGE                  0:0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_WOFFSET                        0x0
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_NO                     _MK_ENUM_CONST(0)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_YES                    _MK_ENUM_CONST(1)
#define DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0_BIT_0_CLEAR                  _MK_ENUM_CONST(1)


// Register DC_CMD_IHUB_COMMON_RO_SPARE_0_0
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0                 _MK_ADDR_CONST(0x75)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_SECURE                  0x0
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_SCR                     0
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_WORD_COUNT                      0x1
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_RESET_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_REG_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_REG_FIELD                       _MK_FIELD_CONST(0xffffffff, DC_CMD_IHUB_COMMON_RO_SPARE_0_0_REG_SHIFT)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_REG_RANGE                       31:0
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_REG_WOFFSET                     0x0
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_REG_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_REG_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_REG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_0_0_REG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_CMD_IHUB_COMMON_RO_SPARE_1_0
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0                 _MK_ADDR_CONST(0x76)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_SECURE                  0x0
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_SCR                     0
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_WORD_COUNT                      0x1
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_RESET_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_REG_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_REG_FIELD                       _MK_FIELD_CONST(0xffffffff, DC_CMD_IHUB_COMMON_RO_SPARE_1_0_REG_SHIFT)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_REG_RANGE                       31:0
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_REG_WOFFSET                     0x0
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_REG_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_REG_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_REG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_IHUB_COMMON_RO_SPARE_1_0_REG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define NV_DISPLAY_WIN_E_INCR_SYNCPT_NB_CONDS   6

// Register DC_CMD_WIN_E_INCR_SYNCPT_0
#define DC_CMD_WIN_E_INCR_SYNCPT_0                      _MK_ADDR_CONST(0x78)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_SECURE                       0x0
#define DC_CMD_WIN_E_INCR_SYNCPT_0_SCR                  0
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WORD_COUNT                   0x1
#define DC_CMD_WIN_E_INCR_SYNCPT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_RESET_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_READ_MASK                    _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WRITE_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_SHIFT                     _MK_SHIFT_CONST(10)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_FIELD                     _MK_FIELD_CONST(0xff, DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_SHIFT)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_RANGE                     17:10
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_WOFFSET                   0x0
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_IMMEDIATE                 _MK_ENUM_CONST(0)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_OP_DONE                   _MK_ENUM_CONST(1)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_RD_DONE                   _MK_ENUM_CONST(2)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_REG_WR_SAFE                       _MK_ENUM_CONST(3)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_ENGINE_IDLE                       _MK_ENUM_CONST(4)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_LINE_FLIPPED                      _MK_ENUM_CONST(5)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_6                    _MK_ENUM_CONST(6)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_7                    _MK_ENUM_CONST(7)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_8                    _MK_ENUM_CONST(8)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_9                    _MK_ENUM_CONST(9)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_10                   _MK_ENUM_CONST(10)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_11                   _MK_ENUM_CONST(11)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_12                   _MK_ENUM_CONST(12)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_13                   _MK_ENUM_CONST(13)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_14                   _MK_ENUM_CONST(14)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_15                   _MK_ENUM_CONST(15)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_16                   _MK_ENUM_CONST(16)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_17                   _MK_ENUM_CONST(17)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_18                   _MK_ENUM_CONST(18)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_19                   _MK_ENUM_CONST(19)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_20                   _MK_ENUM_CONST(20)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_21                   _MK_ENUM_CONST(21)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_22                   _MK_ENUM_CONST(22)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_23                   _MK_ENUM_CONST(23)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_24                   _MK_ENUM_CONST(24)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_25                   _MK_ENUM_CONST(25)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_26                   _MK_ENUM_CONST(26)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_27                   _MK_ENUM_CONST(27)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_28                   _MK_ENUM_CONST(28)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_29                   _MK_ENUM_CONST(29)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_30                   _MK_ENUM_CONST(30)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_COND_COND_31                   _MK_ENUM_CONST(31)

#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_INDX_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_INDX_FIELD                     _MK_FIELD_CONST(0x3ff, DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_INDX_SHIFT)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_INDX_RANGE                     9:0
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_INDX_WOFFSET                   0x0
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_INDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_INDX_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_INDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_0_WIN_E_INDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0                        _MK_ADDR_CONST(0x79)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_SECURE                         0x0
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_SCR                    0
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_RESET_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_READ_MASK                      _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_NO_STALL_SHIFT                       _MK_SHIFT_CONST(8)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_NO_STALL_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_NO_STALL_SHIFT)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_NO_STALL_RANGE                       8:8
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_NO_STALL_WOFFSET                     0x0
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_NO_STALL_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_NO_STALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_SOFT_RESET_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_SOFT_RESET_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_SOFT_RESET_SHIFT)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_SOFT_RESET_RANGE                     0:0
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_SOFT_RESET_WOFFSET                   0x0
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_SOFT_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0_WIN_E_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0                        _MK_ADDR_CONST(0x7a)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_SECURE                         0x0
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_SCR                    0
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_WIN_E_COND_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_WIN_E_COND_STATUS_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_WIN_E_COND_STATUS_SHIFT)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_WIN_E_COND_STATUS_RANGE                        31:0
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_WIN_E_COND_STATUS_WOFFSET                      0x0
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_WIN_E_COND_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_WIN_E_COND_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_WIN_E_COND_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0_WIN_E_COND_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 123 [0x7b]

// Reserved address 124 [0x7c]

// Reserved address 125 [0x7d]

// Reserved address 126 [0x7e]

// Reserved address 127 [0x7f]
#define NV_DISPLAY_WIN_F_INCR_SYNCPT_NB_CONDS   6

// Register DC_CMD_WIN_F_INCR_SYNCPT_0
#define DC_CMD_WIN_F_INCR_SYNCPT_0                      _MK_ADDR_CONST(0x80)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_SECURE                       0x0
#define DC_CMD_WIN_F_INCR_SYNCPT_0_SCR                  0
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WORD_COUNT                   0x1
#define DC_CMD_WIN_F_INCR_SYNCPT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_RESET_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_READ_MASK                    _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WRITE_MASK                   _MK_MASK_CONST(0x3ffff)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_SHIFT                     _MK_SHIFT_CONST(10)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_FIELD                     _MK_FIELD_CONST(0xff, DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_SHIFT)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_RANGE                     17:10
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_WOFFSET                   0x0
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_IMMEDIATE                 _MK_ENUM_CONST(0)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_OP_DONE                   _MK_ENUM_CONST(1)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_RD_DONE                   _MK_ENUM_CONST(2)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_REG_WR_SAFE                       _MK_ENUM_CONST(3)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_ENGINE_IDLE                       _MK_ENUM_CONST(4)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_LINE_FLIPPED                      _MK_ENUM_CONST(5)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_6                    _MK_ENUM_CONST(6)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_7                    _MK_ENUM_CONST(7)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_8                    _MK_ENUM_CONST(8)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_9                    _MK_ENUM_CONST(9)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_10                   _MK_ENUM_CONST(10)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_11                   _MK_ENUM_CONST(11)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_12                   _MK_ENUM_CONST(12)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_13                   _MK_ENUM_CONST(13)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_14                   _MK_ENUM_CONST(14)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_15                   _MK_ENUM_CONST(15)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_16                   _MK_ENUM_CONST(16)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_17                   _MK_ENUM_CONST(17)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_18                   _MK_ENUM_CONST(18)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_19                   _MK_ENUM_CONST(19)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_20                   _MK_ENUM_CONST(20)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_21                   _MK_ENUM_CONST(21)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_22                   _MK_ENUM_CONST(22)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_23                   _MK_ENUM_CONST(23)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_24                   _MK_ENUM_CONST(24)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_25                   _MK_ENUM_CONST(25)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_26                   _MK_ENUM_CONST(26)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_27                   _MK_ENUM_CONST(27)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_28                   _MK_ENUM_CONST(28)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_29                   _MK_ENUM_CONST(29)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_30                   _MK_ENUM_CONST(30)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_COND_COND_31                   _MK_ENUM_CONST(31)

#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_INDX_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_INDX_FIELD                     _MK_FIELD_CONST(0x3ff, DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_INDX_SHIFT)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_INDX_RANGE                     9:0
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_INDX_WOFFSET                   0x0
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_INDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_INDX_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_INDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_0_WIN_F_INDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0                        _MK_ADDR_CONST(0x81)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_SECURE                         0x0
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_SCR                    0
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_RESET_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_READ_MASK                      _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x101)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_NO_STALL_SHIFT                       _MK_SHIFT_CONST(8)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_NO_STALL_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_NO_STALL_SHIFT)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_NO_STALL_RANGE                       8:8
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_NO_STALL_WOFFSET                     0x0
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_NO_STALL_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_NO_STALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_SOFT_RESET_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_SOFT_RESET_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_SOFT_RESET_SHIFT)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_SOFT_RESET_RANGE                     0:0
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_SOFT_RESET_WOFFSET                   0x0
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_SOFT_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0_WIN_F_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0                        _MK_ADDR_CONST(0x82)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_SECURE                         0x0
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_SCR                    0
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_WORD_COUNT                     0x1
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_WIN_F_COND_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_WIN_F_COND_STATUS_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_WIN_F_COND_STATUS_SHIFT)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_WIN_F_COND_STATUS_RANGE                        31:0
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_WIN_F_COND_STATUS_WOFFSET                      0x0
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_WIN_F_COND_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_WIN_F_COND_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_WIN_F_COND_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0_WIN_F_COND_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 131 [0x83]

// Reserved address 132 [0x84]

// Reserved address 133 [0x85]

// Reserved address 134 [0x86]

// Reserved address 135 [0x87]

// Register DC_CMD_SECURE_INT_STATUS_0
#define DC_CMD_SECURE_INT_STATUS_0                      _MK_ADDR_CONST(0x88)
#define DC_CMD_SECURE_INT_STATUS_0_SECURE                       0x0
#define DC_CMD_SECURE_INT_STATUS_0_SCR                  0
#define DC_CMD_SECURE_INT_STATUS_0_WORD_COUNT                   0x1
#define DC_CMD_SECURE_INT_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_STATUS_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define DC_CMD_SECURE_INT_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define DC_CMD_SECURE_INT_STATUS_0_TZ_ACCESS_VIOLATION_INT_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_INT_STATUS_0_TZ_ACCESS_VIOLATION_INT_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_SECURE_INT_STATUS_0_TZ_ACCESS_VIOLATION_INT_SHIFT)
#define DC_CMD_SECURE_INT_STATUS_0_TZ_ACCESS_VIOLATION_INT_RANGE                        0:0
#define DC_CMD_SECURE_INT_STATUS_0_TZ_ACCESS_VIOLATION_INT_WOFFSET                      0x0
#define DC_CMD_SECURE_INT_STATUS_0_TZ_ACCESS_VIOLATION_INT_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_STATUS_0_TZ_ACCESS_VIOLATION_INT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_STATUS_0_TZ_ACCESS_VIOLATION_INT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_STATUS_0_TZ_ACCESS_VIOLATION_INT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_INT_STATUS_0_LOCKDOWN_VIOLATION_INT_SHIFT                 _MK_SHIFT_CONST(1)
#define DC_CMD_SECURE_INT_STATUS_0_LOCKDOWN_VIOLATION_INT_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_SECURE_INT_STATUS_0_LOCKDOWN_VIOLATION_INT_SHIFT)
#define DC_CMD_SECURE_INT_STATUS_0_LOCKDOWN_VIOLATION_INT_RANGE                 1:1
#define DC_CMD_SECURE_INT_STATUS_0_LOCKDOWN_VIOLATION_INT_WOFFSET                       0x0
#define DC_CMD_SECURE_INT_STATUS_0_LOCKDOWN_VIOLATION_INT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_STATUS_0_LOCKDOWN_VIOLATION_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_STATUS_0_LOCKDOWN_VIOLATION_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_STATUS_0_LOCKDOWN_VIOLATION_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_CMD_SECURE_INT_MASK_0
#define DC_CMD_SECURE_INT_MASK_0                        _MK_ADDR_CONST(0x89)
#define DC_CMD_SECURE_INT_MASK_0_SECURE                         0x0
#define DC_CMD_SECURE_INT_MASK_0_SCR                    0
#define DC_CMD_SECURE_INT_MASK_0_WORD_COUNT                     0x1
#define DC_CMD_SECURE_INT_MASK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_MASK_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define DC_CMD_SECURE_INT_MASK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_MASK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_MASK_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define DC_CMD_SECURE_INT_MASK_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_SHIFT)
#define DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_RANGE                 0:0
#define DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_WOFFSET                       0x0
#define DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_INIT_ENUM                     MASKED
#define DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_MASKED                        _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_INT_MASK_0_TZ_ACCESS_VIOLATION_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_SHIFT                  _MK_SHIFT_CONST(1)
#define DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_SHIFT)
#define DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_RANGE                  1:1
#define DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_WOFFSET                        0x0
#define DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_INIT_ENUM                      MASKED
#define DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_MASKED                 _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_INT_MASK_0_LOCKDOWN_VIOLATION_MASK_NOTMASKED                      _MK_ENUM_CONST(1)


// Register DC_CMD_SECURE_INT_ENABLE_0
#define DC_CMD_SECURE_INT_ENABLE_0                      _MK_ADDR_CONST(0x8a)
#define DC_CMD_SECURE_INT_ENABLE_0_SECURE                       0x0
#define DC_CMD_SECURE_INT_ENABLE_0_SCR                  0
#define DC_CMD_SECURE_INT_ENABLE_0_WORD_COUNT                   0x1
#define DC_CMD_SECURE_INT_ENABLE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_ENABLE_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define DC_CMD_SECURE_INT_ENABLE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_ENABLE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_ENABLE_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define DC_CMD_SECURE_INT_ENABLE_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_SHIFT)
#define DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_RANGE                     0:0
#define DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_WOFFSET                   0x0
#define DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_INIT_ENUM                 DISABLE
#define DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_INT_ENABLE_0_TZ_ACCESS_VIOLATION_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_SHIFT                      _MK_SHIFT_CONST(1)
#define DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_SHIFT)
#define DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_RANGE                      1:1
#define DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_WOFFSET                    0x0
#define DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_INIT_ENUM                  DISABLE
#define DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_INT_ENABLE_0_LOCKDOWN_VIOLATION_ENABLE_ENABLE                     _MK_ENUM_CONST(1)


// Reserved address 139 [0x8b]

// Reserved address 140 [0x8c]

// Register DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0                  _MK_ADDR_CONST(0x8d)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_SECURE                   0x0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_SCR                      0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_WORD_COUNT                       0x1
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_READ_MASK                        _MK_MASK_CONST(0x30fffff)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_OFFSET_FIELD                     _MK_FIELD_CONST(0xfffff, DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_OFFSET_SHIFT)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_OFFSET_RANGE                     19:0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_OFFSET_WOFFSET                   0x0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_COR_SHIFT                        _MK_SHIFT_CONST(24)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_COR_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_COR_SHIFT)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_COR_RANGE                        24:24
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_COR_WOFFSET                      0x0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_COR_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_COR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_COR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_COR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_COR_CLASS                        _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_COR_REGISTER                     _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RWN_SHIFT                        _MK_SHIFT_CONST(25)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RWN_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RWN_SHIFT)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RWN_RANGE                        25:25
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RWN_WOFFSET                      0x0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RWN_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RWN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RWN_WRITE                        _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0_RWN_READ                 _MK_ENUM_CONST(1)


// Register DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0                  _MK_ADDR_CONST(0x8e)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SECURE                   0x0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SCR                      0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_WORD_COUNT                       0x1
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_READ_MASK                        _MK_MASK_CONST(0x7ff03ff)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_CHANNEL_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_CHANNEL_FIELD                    _MK_FIELD_CONST(0x3ff, DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_CHANNEL_SHIFT)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_CHANNEL_RANGE                    9:0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_CHANNEL_WOFFSET                  0x0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_CHANNEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_CHANNEL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_CHANNEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_CHANNEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SECGROUP_SHIFT                   _MK_SHIFT_CONST(16)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SECGROUP_FIELD                   _MK_FIELD_CONST(0x7ff, DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SECGROUP_SHIFT)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SECGROUP_RANGE                   26:16
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SECGROUP_WOFFSET                 0x0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SECGROUP_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SECGROUP_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SECGROUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0_SECGROUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0                  _MK_ADDR_CONST(0x8f)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_SECURE                   0x0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_SCR                      0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_WORD_COUNT                       0x1
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_DATA_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_DATA_FIELD                       _MK_FIELD_CONST(0xffffffff, DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_DATA_SHIFT)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_DATA_RANGE                       31:0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_DATA_WOFFSET                     0x0
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_CMD_SECURE_LOCKDOWN_0
#define DC_CMD_SECURE_LOCKDOWN_0                        _MK_ADDR_CONST(0x90)
#define DC_CMD_SECURE_LOCKDOWN_0_SECURE                         0x0
#define DC_CMD_SECURE_LOCKDOWN_0_SCR                    0
#define DC_CMD_SECURE_LOCKDOWN_0_WORD_COUNT                     0x1
#define DC_CMD_SECURE_LOCKDOWN_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_0_RESET_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_0_READ_MASK                      _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_0_WRITE_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_0_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_0_OFFSET_FIELD                   _MK_FIELD_CONST(0xfffff, DC_CMD_SECURE_LOCKDOWN_0_OFFSET_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_0_OFFSET_RANGE                   19:0
#define DC_CMD_SECURE_LOCKDOWN_0_OFFSET_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_0_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_0_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
#define DC_CMD_SECURE_LOCKDOWN_0_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_0_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_LOCKDOWN_0_HEADS_SHIFT                    _MK_SHIFT_CONST(30)
#define DC_CMD_SECURE_LOCKDOWN_0_HEADS_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_0_HEADS_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_0_HEADS_RANGE                    30:30
#define DC_CMD_SECURE_LOCKDOWN_0_HEADS_WOFFSET                  0x0
#define DC_CMD_SECURE_LOCKDOWN_0_HEADS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_0_HEADS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_0_HEADS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_0_HEADS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_0_HEADS_INIT_ENUM                        HEAD0
#define DC_CMD_SECURE_LOCKDOWN_0_HEADS_HEAD0                    _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_0_HEADS_ALL                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_LOCKDOWN_0_ENABLE_SHIFT                   _MK_SHIFT_CONST(31)
#define DC_CMD_SECURE_LOCKDOWN_0_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_0_ENABLE_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_0_ENABLE_RANGE                   31:31
#define DC_CMD_SECURE_LOCKDOWN_0_ENABLE_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_0_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_0_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_0_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_0_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_0_ENABLE_INIT_ENUM                       DISABLE
#define DC_CMD_SECURE_LOCKDOWN_0_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_0_ENABLE_ENABLE                  _MK_ENUM_CONST(1)


// Register DC_CMD_SECURE_LOCKDOWN
#define DC_CMD_SECURE_LOCKDOWN                  _MK_ADDR_CONST(0x90)
#define DC_CMD_SECURE_LOCKDOWN_SECURE                   0x0
#define DC_CMD_SECURE_LOCKDOWN_SCR                      0
#define DC_CMD_SECURE_LOCKDOWN_WORD_COUNT                       0x1
#define DC_CMD_SECURE_LOCKDOWN_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_RESET_MASK                       _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_READ_MASK                        _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_WRITE_MASK                       _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_OFFSET_FIELD                     _MK_FIELD_CONST(0xfffff, DC_CMD_SECURE_LOCKDOWN_OFFSET_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_OFFSET_RANGE                     19:0
#define DC_CMD_SECURE_LOCKDOWN_OFFSET_WOFFSET                   0x0
#define DC_CMD_SECURE_LOCKDOWN_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0xfffff)
#define DC_CMD_SECURE_LOCKDOWN_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_LOCKDOWN_HEADS_SHIFT                      _MK_SHIFT_CONST(30)
#define DC_CMD_SECURE_LOCKDOWN_HEADS_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_HEADS_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_HEADS_RANGE                      30:30
#define DC_CMD_SECURE_LOCKDOWN_HEADS_WOFFSET                    0x0
#define DC_CMD_SECURE_LOCKDOWN_HEADS_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_HEADS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_HEADS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_HEADS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_HEADS_INIT_ENUM                  HEAD0
#define DC_CMD_SECURE_LOCKDOWN_HEADS_HEAD0                      _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_HEADS_ALL                        _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_LOCKDOWN_ENABLE_SHIFT                     _MK_SHIFT_CONST(31)
#define DC_CMD_SECURE_LOCKDOWN_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_ENABLE_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_ENABLE_RANGE                     31:31
#define DC_CMD_SECURE_LOCKDOWN_ENABLE_WOFFSET                   0x0
#define DC_CMD_SECURE_LOCKDOWN_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_ENABLE_INIT_ENUM                 DISABLE
#define DC_CMD_SECURE_LOCKDOWN_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_ENABLE_ENABLE                    _MK_ENUM_CONST(1)


// Register DC_CMD_SECURE_LOCKDOWN_1
#define DC_CMD_SECURE_LOCKDOWN_1                        _MK_ADDR_CONST(0x91)
#define DC_CMD_SECURE_LOCKDOWN_1_SECURE                         0x0
#define DC_CMD_SECURE_LOCKDOWN_1_SCR                    0
#define DC_CMD_SECURE_LOCKDOWN_1_WORD_COUNT                     0x1
#define DC_CMD_SECURE_LOCKDOWN_1_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_1_RESET_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_1_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_1_READ_MASK                      _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_1_WRITE_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_1_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_1_OFFSET_FIELD                   _MK_FIELD_CONST(0xfffff, DC_CMD_SECURE_LOCKDOWN_1_OFFSET_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_1_OFFSET_RANGE                   19:0
#define DC_CMD_SECURE_LOCKDOWN_1_OFFSET_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_1_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_1_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
#define DC_CMD_SECURE_LOCKDOWN_1_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_1_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_LOCKDOWN_1_HEADS_SHIFT                    _MK_SHIFT_CONST(30)
#define DC_CMD_SECURE_LOCKDOWN_1_HEADS_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_1_HEADS_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_1_HEADS_RANGE                    30:30
#define DC_CMD_SECURE_LOCKDOWN_1_HEADS_WOFFSET                  0x0
#define DC_CMD_SECURE_LOCKDOWN_1_HEADS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_1_HEADS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_1_HEADS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_1_HEADS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_1_HEADS_INIT_ENUM                        HEAD0
#define DC_CMD_SECURE_LOCKDOWN_1_HEADS_HEAD0                    _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_1_HEADS_ALL                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_LOCKDOWN_1_ENABLE_SHIFT                   _MK_SHIFT_CONST(31)
#define DC_CMD_SECURE_LOCKDOWN_1_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_1_ENABLE_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_1_ENABLE_RANGE                   31:31
#define DC_CMD_SECURE_LOCKDOWN_1_ENABLE_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_1_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_1_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_1_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_1_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_1_ENABLE_INIT_ENUM                       DISABLE
#define DC_CMD_SECURE_LOCKDOWN_1_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_1_ENABLE_ENABLE                  _MK_ENUM_CONST(1)


// Register DC_CMD_SECURE_LOCKDOWN_2
#define DC_CMD_SECURE_LOCKDOWN_2                        _MK_ADDR_CONST(0x92)
#define DC_CMD_SECURE_LOCKDOWN_2_SECURE                         0x0
#define DC_CMD_SECURE_LOCKDOWN_2_SCR                    0
#define DC_CMD_SECURE_LOCKDOWN_2_WORD_COUNT                     0x1
#define DC_CMD_SECURE_LOCKDOWN_2_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_2_RESET_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_2_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_2_READ_MASK                      _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_2_WRITE_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_2_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_2_OFFSET_FIELD                   _MK_FIELD_CONST(0xfffff, DC_CMD_SECURE_LOCKDOWN_2_OFFSET_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_2_OFFSET_RANGE                   19:0
#define DC_CMD_SECURE_LOCKDOWN_2_OFFSET_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_2_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_2_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
#define DC_CMD_SECURE_LOCKDOWN_2_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_2_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_LOCKDOWN_2_HEADS_SHIFT                    _MK_SHIFT_CONST(30)
#define DC_CMD_SECURE_LOCKDOWN_2_HEADS_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_2_HEADS_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_2_HEADS_RANGE                    30:30
#define DC_CMD_SECURE_LOCKDOWN_2_HEADS_WOFFSET                  0x0
#define DC_CMD_SECURE_LOCKDOWN_2_HEADS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_2_HEADS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_2_HEADS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_2_HEADS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_2_HEADS_INIT_ENUM                        HEAD0
#define DC_CMD_SECURE_LOCKDOWN_2_HEADS_HEAD0                    _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_2_HEADS_ALL                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_LOCKDOWN_2_ENABLE_SHIFT                   _MK_SHIFT_CONST(31)
#define DC_CMD_SECURE_LOCKDOWN_2_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_2_ENABLE_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_2_ENABLE_RANGE                   31:31
#define DC_CMD_SECURE_LOCKDOWN_2_ENABLE_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_2_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_2_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_2_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_2_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_2_ENABLE_INIT_ENUM                       DISABLE
#define DC_CMD_SECURE_LOCKDOWN_2_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_2_ENABLE_ENABLE                  _MK_ENUM_CONST(1)


// Register DC_CMD_SECURE_LOCKDOWN_3
#define DC_CMD_SECURE_LOCKDOWN_3                        _MK_ADDR_CONST(0x93)
#define DC_CMD_SECURE_LOCKDOWN_3_SECURE                         0x0
#define DC_CMD_SECURE_LOCKDOWN_3_SCR                    0
#define DC_CMD_SECURE_LOCKDOWN_3_WORD_COUNT                     0x1
#define DC_CMD_SECURE_LOCKDOWN_3_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_3_RESET_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_3_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_3_READ_MASK                      _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_3_WRITE_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_3_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_3_OFFSET_FIELD                   _MK_FIELD_CONST(0xfffff, DC_CMD_SECURE_LOCKDOWN_3_OFFSET_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_3_OFFSET_RANGE                   19:0
#define DC_CMD_SECURE_LOCKDOWN_3_OFFSET_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_3_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_3_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
#define DC_CMD_SECURE_LOCKDOWN_3_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_3_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_LOCKDOWN_3_HEADS_SHIFT                    _MK_SHIFT_CONST(30)
#define DC_CMD_SECURE_LOCKDOWN_3_HEADS_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_3_HEADS_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_3_HEADS_RANGE                    30:30
#define DC_CMD_SECURE_LOCKDOWN_3_HEADS_WOFFSET                  0x0
#define DC_CMD_SECURE_LOCKDOWN_3_HEADS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_3_HEADS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_3_HEADS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_3_HEADS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_3_HEADS_INIT_ENUM                        HEAD0
#define DC_CMD_SECURE_LOCKDOWN_3_HEADS_HEAD0                    _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_3_HEADS_ALL                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_LOCKDOWN_3_ENABLE_SHIFT                   _MK_SHIFT_CONST(31)
#define DC_CMD_SECURE_LOCKDOWN_3_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_3_ENABLE_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_3_ENABLE_RANGE                   31:31
#define DC_CMD_SECURE_LOCKDOWN_3_ENABLE_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_3_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_3_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_3_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_3_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_3_ENABLE_INIT_ENUM                       DISABLE
#define DC_CMD_SECURE_LOCKDOWN_3_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_3_ENABLE_ENABLE                  _MK_ENUM_CONST(1)


// Register DC_CMD_SECURE_LOCKDOWN_4
#define DC_CMD_SECURE_LOCKDOWN_4                        _MK_ADDR_CONST(0x94)
#define DC_CMD_SECURE_LOCKDOWN_4_SECURE                         0x0
#define DC_CMD_SECURE_LOCKDOWN_4_SCR                    0
#define DC_CMD_SECURE_LOCKDOWN_4_WORD_COUNT                     0x1
#define DC_CMD_SECURE_LOCKDOWN_4_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_4_RESET_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_4_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_4_READ_MASK                      _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_4_WRITE_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_4_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_4_OFFSET_FIELD                   _MK_FIELD_CONST(0xfffff, DC_CMD_SECURE_LOCKDOWN_4_OFFSET_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_4_OFFSET_RANGE                   19:0
#define DC_CMD_SECURE_LOCKDOWN_4_OFFSET_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_4_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_4_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
#define DC_CMD_SECURE_LOCKDOWN_4_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_4_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_LOCKDOWN_4_HEADS_SHIFT                    _MK_SHIFT_CONST(30)
#define DC_CMD_SECURE_LOCKDOWN_4_HEADS_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_4_HEADS_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_4_HEADS_RANGE                    30:30
#define DC_CMD_SECURE_LOCKDOWN_4_HEADS_WOFFSET                  0x0
#define DC_CMD_SECURE_LOCKDOWN_4_HEADS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_4_HEADS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_4_HEADS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_4_HEADS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_4_HEADS_INIT_ENUM                        HEAD0
#define DC_CMD_SECURE_LOCKDOWN_4_HEADS_HEAD0                    _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_4_HEADS_ALL                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_LOCKDOWN_4_ENABLE_SHIFT                   _MK_SHIFT_CONST(31)
#define DC_CMD_SECURE_LOCKDOWN_4_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_4_ENABLE_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_4_ENABLE_RANGE                   31:31
#define DC_CMD_SECURE_LOCKDOWN_4_ENABLE_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_4_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_4_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_4_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_4_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_4_ENABLE_INIT_ENUM                       DISABLE
#define DC_CMD_SECURE_LOCKDOWN_4_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_4_ENABLE_ENABLE                  _MK_ENUM_CONST(1)


// Register DC_CMD_SECURE_LOCKDOWN_5
#define DC_CMD_SECURE_LOCKDOWN_5                        _MK_ADDR_CONST(0x95)
#define DC_CMD_SECURE_LOCKDOWN_5_SECURE                         0x0
#define DC_CMD_SECURE_LOCKDOWN_5_SCR                    0
#define DC_CMD_SECURE_LOCKDOWN_5_WORD_COUNT                     0x1
#define DC_CMD_SECURE_LOCKDOWN_5_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_5_RESET_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_5_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_5_READ_MASK                      _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_5_WRITE_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_5_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_5_OFFSET_FIELD                   _MK_FIELD_CONST(0xfffff, DC_CMD_SECURE_LOCKDOWN_5_OFFSET_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_5_OFFSET_RANGE                   19:0
#define DC_CMD_SECURE_LOCKDOWN_5_OFFSET_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_5_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_5_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
#define DC_CMD_SECURE_LOCKDOWN_5_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_5_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_LOCKDOWN_5_HEADS_SHIFT                    _MK_SHIFT_CONST(30)
#define DC_CMD_SECURE_LOCKDOWN_5_HEADS_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_5_HEADS_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_5_HEADS_RANGE                    30:30
#define DC_CMD_SECURE_LOCKDOWN_5_HEADS_WOFFSET                  0x0
#define DC_CMD_SECURE_LOCKDOWN_5_HEADS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_5_HEADS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_5_HEADS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_5_HEADS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_5_HEADS_INIT_ENUM                        HEAD0
#define DC_CMD_SECURE_LOCKDOWN_5_HEADS_HEAD0                    _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_5_HEADS_ALL                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_LOCKDOWN_5_ENABLE_SHIFT                   _MK_SHIFT_CONST(31)
#define DC_CMD_SECURE_LOCKDOWN_5_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_5_ENABLE_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_5_ENABLE_RANGE                   31:31
#define DC_CMD_SECURE_LOCKDOWN_5_ENABLE_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_5_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_5_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_5_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_5_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_5_ENABLE_INIT_ENUM                       DISABLE
#define DC_CMD_SECURE_LOCKDOWN_5_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_5_ENABLE_ENABLE                  _MK_ENUM_CONST(1)


// Register DC_CMD_SECURE_LOCKDOWN_6
#define DC_CMD_SECURE_LOCKDOWN_6                        _MK_ADDR_CONST(0x96)
#define DC_CMD_SECURE_LOCKDOWN_6_SECURE                         0x0
#define DC_CMD_SECURE_LOCKDOWN_6_SCR                    0
#define DC_CMD_SECURE_LOCKDOWN_6_WORD_COUNT                     0x1
#define DC_CMD_SECURE_LOCKDOWN_6_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_6_RESET_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_6_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_6_READ_MASK                      _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_6_WRITE_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_6_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_6_OFFSET_FIELD                   _MK_FIELD_CONST(0xfffff, DC_CMD_SECURE_LOCKDOWN_6_OFFSET_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_6_OFFSET_RANGE                   19:0
#define DC_CMD_SECURE_LOCKDOWN_6_OFFSET_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_6_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_6_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
#define DC_CMD_SECURE_LOCKDOWN_6_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_6_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_LOCKDOWN_6_HEADS_SHIFT                    _MK_SHIFT_CONST(30)
#define DC_CMD_SECURE_LOCKDOWN_6_HEADS_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_6_HEADS_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_6_HEADS_RANGE                    30:30
#define DC_CMD_SECURE_LOCKDOWN_6_HEADS_WOFFSET                  0x0
#define DC_CMD_SECURE_LOCKDOWN_6_HEADS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_6_HEADS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_6_HEADS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_6_HEADS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_6_HEADS_INIT_ENUM                        HEAD0
#define DC_CMD_SECURE_LOCKDOWN_6_HEADS_HEAD0                    _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_6_HEADS_ALL                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_LOCKDOWN_6_ENABLE_SHIFT                   _MK_SHIFT_CONST(31)
#define DC_CMD_SECURE_LOCKDOWN_6_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_6_ENABLE_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_6_ENABLE_RANGE                   31:31
#define DC_CMD_SECURE_LOCKDOWN_6_ENABLE_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_6_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_6_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_6_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_6_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_6_ENABLE_INIT_ENUM                       DISABLE
#define DC_CMD_SECURE_LOCKDOWN_6_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_6_ENABLE_ENABLE                  _MK_ENUM_CONST(1)


// Register DC_CMD_SECURE_LOCKDOWN_7
#define DC_CMD_SECURE_LOCKDOWN_7                        _MK_ADDR_CONST(0x97)
#define DC_CMD_SECURE_LOCKDOWN_7_SECURE                         0x0
#define DC_CMD_SECURE_LOCKDOWN_7_SCR                    0
#define DC_CMD_SECURE_LOCKDOWN_7_WORD_COUNT                     0x1
#define DC_CMD_SECURE_LOCKDOWN_7_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_7_RESET_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_7_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_7_READ_MASK                      _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_7_WRITE_MASK                     _MK_MASK_CONST(0xc00fffff)
#define DC_CMD_SECURE_LOCKDOWN_7_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_7_OFFSET_FIELD                   _MK_FIELD_CONST(0xfffff, DC_CMD_SECURE_LOCKDOWN_7_OFFSET_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_7_OFFSET_RANGE                   19:0
#define DC_CMD_SECURE_LOCKDOWN_7_OFFSET_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_7_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_7_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
#define DC_CMD_SECURE_LOCKDOWN_7_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_7_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_SECURE_LOCKDOWN_7_HEADS_SHIFT                    _MK_SHIFT_CONST(30)
#define DC_CMD_SECURE_LOCKDOWN_7_HEADS_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_7_HEADS_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_7_HEADS_RANGE                    30:30
#define DC_CMD_SECURE_LOCKDOWN_7_HEADS_WOFFSET                  0x0
#define DC_CMD_SECURE_LOCKDOWN_7_HEADS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_7_HEADS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_7_HEADS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_7_HEADS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_7_HEADS_INIT_ENUM                        HEAD0
#define DC_CMD_SECURE_LOCKDOWN_7_HEADS_HEAD0                    _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_7_HEADS_ALL                      _MK_ENUM_CONST(1)

#define DC_CMD_SECURE_LOCKDOWN_7_ENABLE_SHIFT                   _MK_SHIFT_CONST(31)
#define DC_CMD_SECURE_LOCKDOWN_7_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_SECURE_LOCKDOWN_7_ENABLE_SHIFT)
#define DC_CMD_SECURE_LOCKDOWN_7_ENABLE_RANGE                   31:31
#define DC_CMD_SECURE_LOCKDOWN_7_ENABLE_WOFFSET                 0x0
#define DC_CMD_SECURE_LOCKDOWN_7_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_7_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_SECURE_LOCKDOWN_7_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_7_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_SECURE_LOCKDOWN_7_ENABLE_INIT_ENUM                       DISABLE
#define DC_CMD_SECURE_LOCKDOWN_7_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_SECURE_LOCKDOWN_7_ENABLE_ENABLE                  _MK_ENUM_CONST(1)


// Register DC_CMD_STREAMID_HEAD_0
#define DC_CMD_STREAMID_HEAD_0                  _MK_ADDR_CONST(0xa0)
#define DC_CMD_STREAMID_HEAD_0_SECURE                   0x0
#define DC_CMD_STREAMID_HEAD_0_SCR                      0
#define DC_CMD_STREAMID_HEAD_0_WORD_COUNT                       0x1
#define DC_CMD_STREAMID_HEAD_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_STREAMID_HEAD_0_RESET_MASK                       _MK_MASK_CONST(0x3ff)
#define DC_CMD_STREAMID_HEAD_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_CMD_STREAMID_HEAD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_STREAMID_HEAD_0_READ_MASK                        _MK_MASK_CONST(0x3ff)
#define DC_CMD_STREAMID_HEAD_0_WRITE_MASK                       _MK_MASK_CONST(0x3ff)
#define DC_CMD_STREAMID_HEAD_0_ID_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_CMD_STREAMID_HEAD_0_ID_FIELD                 _MK_FIELD_CONST(0x3ff, DC_CMD_STREAMID_HEAD_0_ID_SHIFT)
#define DC_CMD_STREAMID_HEAD_0_ID_RANGE                 9:0
#define DC_CMD_STREAMID_HEAD_0_ID_WOFFSET                       0x0
#define DC_CMD_STREAMID_HEAD_0_ID_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_STREAMID_HEAD_0_ID_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
#define DC_CMD_STREAMID_HEAD_0_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_STREAMID_HEAD_0_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_CMD_RSB_HEAD_0
#define DC_CMD_RSB_HEAD_0                       _MK_ADDR_CONST(0xa1)
#define DC_CMD_RSB_HEAD_0_SECURE                        0x0
#define DC_CMD_RSB_HEAD_0_SCR                   0
#define DC_CMD_RSB_HEAD_0_WORD_COUNT                    0x1
#define DC_CMD_RSB_HEAD_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define DC_CMD_RSB_HEAD_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_RSB_HEAD_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_RSB_HEAD_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_RSB_HEAD_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_RSB_HEAD_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_RSB_HEAD_0_NONSECURE_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_CMD_RSB_HEAD_0_NONSECURE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_RSB_HEAD_0_NONSECURE_SHIFT)
#define DC_CMD_RSB_HEAD_0_NONSECURE_RANGE                       0:0
#define DC_CMD_RSB_HEAD_0_NONSECURE_WOFFSET                     0x0
#define DC_CMD_RSB_HEAD_0_NONSECURE_DEFAULT                     _MK_MASK_CONST(0x1)
#define DC_CMD_RSB_HEAD_0_NONSECURE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_RSB_HEAD_0_NONSECURE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_RSB_HEAD_0_NONSECURE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_CMD_DISPLAY_MONITOR_ADDR_0
#define DC_CMD_DISPLAY_MONITOR_ADDR_0                   _MK_ADDR_CONST(0xb0)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_SECURE                    0x0
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_SCR                       0
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_WORD_COUNT                        0x1
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_OFFSET_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_OFFSET_FIELD                      _MK_FIELD_CONST(0x7fffffff, DC_CMD_DISPLAY_MONITOR_ADDR_0_OFFSET_SHIFT)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_OFFSET_RANGE                      30:0
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_OFFSET_WOFFSET                    0x0
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_OFFSET_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_OFFSET_DEFAULT_MASK                       _MK_MASK_CONST(0x7fffffff)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_OFFSET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_OFFSET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_CMD_DISPLAY_MONITOR_ADDR_0_WRITE_SHIFT                       _MK_SHIFT_CONST(31)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_WRITE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_MONITOR_ADDR_0_WRITE_SHIFT)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_WRITE_RANGE                       31:31
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_WRITE_WOFFSET                     0x0
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_WRITE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_WRITE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_WRITE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_ADDR_0_WRITE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_CMD_DISPLAY_MONITOR_DATA_0
#define DC_CMD_DISPLAY_MONITOR_DATA_0                   _MK_ADDR_CONST(0xb1)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_SECURE                    0x0
#define DC_CMD_DISPLAY_MONITOR_DATA_0_SCR                       0
#define DC_CMD_DISPLAY_MONITOR_DATA_0_WORD_COUNT                        0x1
#define DC_CMD_DISPLAY_MONITOR_DATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_VALUE_FIELD                       _MK_FIELD_CONST(0xffffffff, DC_CMD_DISPLAY_MONITOR_DATA_0_VALUE_SHIFT)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_VALUE_RANGE                       31:0
#define DC_CMD_DISPLAY_MONITOR_DATA_0_VALUE_WOFFSET                     0x0
#define DC_CMD_DISPLAY_MONITOR_DATA_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_DISPLAY_MONITOR_DATA_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_CMD_HSM_INT_STATUS_0
#define DC_CMD_HSM_INT_STATUS_0                 _MK_ADDR_CONST(0xc0)
#define DC_CMD_HSM_INT_STATUS_0_SECURE                  0x0
#define DC_CMD_HSM_INT_STATUS_0_SCR                     0
#define DC_CMD_HSM_INT_STATUS_0_WORD_COUNT                      0x1
#define DC_CMD_HSM_INT_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_STATUS_0_FRAME_END_INT_SHIFT                     _MK_SHIFT_CONST(1)
#define DC_CMD_HSM_INT_STATUS_0_FRAME_END_INT_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_FRAME_END_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_FRAME_END_INT_RANGE                     1:1
#define DC_CMD_HSM_INT_STATUS_0_FRAME_END_INT_WOFFSET                   0x0
#define DC_CMD_HSM_INT_STATUS_0_FRAME_END_INT_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_FRAME_END_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_FRAME_END_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_FRAME_END_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_V_BLANK_INT_SHIFT                       _MK_SHIFT_CONST(2)
#define DC_CMD_HSM_INT_STATUS_0_V_BLANK_INT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_V_BLANK_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_V_BLANK_INT_RANGE                       2:2
#define DC_CMD_HSM_INT_STATUS_0_V_BLANK_INT_WOFFSET                     0x0
#define DC_CMD_HSM_INT_STATUS_0_V_BLANK_INT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_V_BLANK_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_V_BLANK_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_V_BLANK_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_V_PULSE3_INT_SHIFT                      _MK_SHIFT_CONST(4)
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE3_INT_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_V_PULSE3_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE3_INT_RANGE                      4:4
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE3_INT_WOFFSET                    0x0
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE3_INT_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE3_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE3_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE3_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_V_PULSE2_INT_SHIFT                      _MK_SHIFT_CONST(5)
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE2_INT_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_V_PULSE2_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE2_INT_RANGE                      5:5
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE2_INT_WOFFSET                    0x0
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE2_INT_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE2_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE2_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_V_PULSE2_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_REGION_CRC_INT_SHIFT                    _MK_SHIFT_CONST(6)
#define DC_CMD_HSM_INT_STATUS_0_REGION_CRC_INT_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_REGION_CRC_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_REGION_CRC_INT_RANGE                    6:6
#define DC_CMD_HSM_INT_STATUS_0_REGION_CRC_INT_WOFFSET                  0x0
#define DC_CMD_HSM_INT_STATUS_0_REGION_CRC_INT_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_REGION_CRC_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_REGION_CRC_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_REGION_CRC_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_REG_TMOUT_INT_SHIFT                     _MK_SHIFT_CONST(7)
#define DC_CMD_HSM_INT_STATUS_0_REG_TMOUT_INT_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_REG_TMOUT_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_REG_TMOUT_INT_RANGE                     7:7
#define DC_CMD_HSM_INT_STATUS_0_REG_TMOUT_INT_WOFFSET                   0x0
#define DC_CMD_HSM_INT_STATUS_0_REG_TMOUT_INT_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_REG_TMOUT_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_REG_TMOUT_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_REG_TMOUT_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_MSF_INT_SHIFT                   _MK_SHIFT_CONST(12)
#define DC_CMD_HSM_INT_STATUS_0_MSF_INT_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_MSF_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_MSF_INT_RANGE                   12:12
#define DC_CMD_HSM_INT_STATUS_0_MSF_INT_WOFFSET                 0x0
#define DC_CMD_HSM_INT_STATUS_0_MSF_INT_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_MSF_INT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_MSF_INT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_MSF_INT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_HEAD_UF_INT_SHIFT                       _MK_SHIFT_CONST(23)
#define DC_CMD_HSM_INT_STATUS_0_HEAD_UF_INT_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_HEAD_UF_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_HEAD_UF_INT_RANGE                       23:23
#define DC_CMD_HSM_INT_STATUS_0_HEAD_UF_INT_WOFFSET                     0x0
#define DC_CMD_HSM_INT_STATUS_0_HEAD_UF_INT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_HEAD_UF_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_HEAD_UF_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_HEAD_UF_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_SHIFT                  _MK_SHIFT_CONST(24)
#define DC_CMD_HSM_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_RANGE                  24:24
#define DC_CMD_HSM_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_WOFFSET                        0x0
#define DC_CMD_HSM_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_SD3_BUCKET_WALK_DONE_INT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_DSC_OBUF_UF_INT_SHIFT                   _MK_SHIFT_CONST(26)
#define DC_CMD_HSM_INT_STATUS_0_DSC_OBUF_UF_INT_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_DSC_OBUF_UF_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_DSC_OBUF_UF_INT_RANGE                   26:26
#define DC_CMD_HSM_INT_STATUS_0_DSC_OBUF_UF_INT_WOFFSET                 0x0
#define DC_CMD_HSM_INT_STATUS_0_DSC_OBUF_UF_INT_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_OBUF_UF_INT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_OBUF_UF_INT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_OBUF_UF_INT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_DSC_RBUF_UF_INT_SHIFT                   _MK_SHIFT_CONST(27)
#define DC_CMD_HSM_INT_STATUS_0_DSC_RBUF_UF_INT_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_DSC_RBUF_UF_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_DSC_RBUF_UF_INT_RANGE                   27:27
#define DC_CMD_HSM_INT_STATUS_0_DSC_RBUF_UF_INT_WOFFSET                 0x0
#define DC_CMD_HSM_INT_STATUS_0_DSC_RBUF_UF_INT_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_RBUF_UF_INT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_RBUF_UF_INT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_RBUF_UF_INT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_DSC_BBUF_UF_INT_SHIFT                   _MK_SHIFT_CONST(28)
#define DC_CMD_HSM_INT_STATUS_0_DSC_BBUF_UF_INT_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_DSC_BBUF_UF_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_DSC_BBUF_UF_INT_RANGE                   28:28
#define DC_CMD_HSM_INT_STATUS_0_DSC_BBUF_UF_INT_WOFFSET                 0x0
#define DC_CMD_HSM_INT_STATUS_0_DSC_BBUF_UF_INT_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_BBUF_UF_INT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_BBUF_UF_INT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_BBUF_UF_INT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_CMD_HSM_INT_STATUS_0_DSC_TO_UF_INT_SHIFT                     _MK_SHIFT_CONST(29)
#define DC_CMD_HSM_INT_STATUS_0_DSC_TO_UF_INT_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_STATUS_0_DSC_TO_UF_INT_SHIFT)
#define DC_CMD_HSM_INT_STATUS_0_DSC_TO_UF_INT_RANGE                     29:29
#define DC_CMD_HSM_INT_STATUS_0_DSC_TO_UF_INT_WOFFSET                   0x0
#define DC_CMD_HSM_INT_STATUS_0_DSC_TO_UF_INT_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_TO_UF_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_TO_UF_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_STATUS_0_DSC_TO_UF_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_CMD_HSM_INT_MASK_0
#define DC_CMD_HSM_INT_MASK_0                   _MK_ADDR_CONST(0xc1)
#define DC_CMD_HSM_INT_MASK_0_SECURE                    0x0
#define DC_CMD_HSM_INT_MASK_0_SCR                       0
#define DC_CMD_HSM_INT_MASK_0_WORD_COUNT                        0x1
#define DC_CMD_HSM_INT_MASK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_RESET_MASK                        _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_MASK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_READ_MASK                         _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_MASK_0_WRITE_MASK                        _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_MASK_0_FRAME_END_INT_MASK_SHIFT                  _MK_SHIFT_CONST(1)
#define DC_CMD_HSM_INT_MASK_0_FRAME_END_INT_MASK_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_FRAME_END_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_FRAME_END_INT_MASK_RANGE                  1:1
#define DC_CMD_HSM_INT_MASK_0_FRAME_END_INT_MASK_WOFFSET                        0x0
#define DC_CMD_HSM_INT_MASK_0_FRAME_END_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_FRAME_END_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_FRAME_END_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_FRAME_END_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_FRAME_END_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_FRAME_END_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_V_BLANK_INT_MASK_SHIFT                    _MK_SHIFT_CONST(2)
#define DC_CMD_HSM_INT_MASK_0_V_BLANK_INT_MASK_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_V_BLANK_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_V_BLANK_INT_MASK_RANGE                    2:2
#define DC_CMD_HSM_INT_MASK_0_V_BLANK_INT_MASK_WOFFSET                  0x0
#define DC_CMD_HSM_INT_MASK_0_V_BLANK_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_V_BLANK_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_V_BLANK_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_V_BLANK_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_V_BLANK_INT_MASK_MASKED                   _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_V_BLANK_INT_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_V_PULSE3_INT_MASK_SHIFT                   _MK_SHIFT_CONST(4)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE3_INT_MASK_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_V_PULSE3_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE3_INT_MASK_RANGE                   4:4
#define DC_CMD_HSM_INT_MASK_0_V_PULSE3_INT_MASK_WOFFSET                 0x0
#define DC_CMD_HSM_INT_MASK_0_V_PULSE3_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE3_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE3_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE3_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE3_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE3_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_V_PULSE2_INT_MASK_SHIFT                   _MK_SHIFT_CONST(5)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE2_INT_MASK_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_V_PULSE2_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE2_INT_MASK_RANGE                   5:5
#define DC_CMD_HSM_INT_MASK_0_V_PULSE2_INT_MASK_WOFFSET                 0x0
#define DC_CMD_HSM_INT_MASK_0_V_PULSE2_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE2_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE2_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE2_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE2_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_V_PULSE2_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_REGION_CRC_INT_MASK_SHIFT                 _MK_SHIFT_CONST(6)
#define DC_CMD_HSM_INT_MASK_0_REGION_CRC_INT_MASK_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_REGION_CRC_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_REGION_CRC_INT_MASK_RANGE                 6:6
#define DC_CMD_HSM_INT_MASK_0_REGION_CRC_INT_MASK_WOFFSET                       0x0
#define DC_CMD_HSM_INT_MASK_0_REGION_CRC_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_REGION_CRC_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_REGION_CRC_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_REGION_CRC_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_REGION_CRC_INT_MASK_MASKED                        _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_REGION_CRC_INT_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_REG_TMOUT_INT_MASK_SHIFT                  _MK_SHIFT_CONST(7)
#define DC_CMD_HSM_INT_MASK_0_REG_TMOUT_INT_MASK_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_REG_TMOUT_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_REG_TMOUT_INT_MASK_RANGE                  7:7
#define DC_CMD_HSM_INT_MASK_0_REG_TMOUT_INT_MASK_WOFFSET                        0x0
#define DC_CMD_HSM_INT_MASK_0_REG_TMOUT_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_REG_TMOUT_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_REG_TMOUT_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_REG_TMOUT_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_REG_TMOUT_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_REG_TMOUT_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_MSF_INT_MASK_SHIFT                        _MK_SHIFT_CONST(12)
#define DC_CMD_HSM_INT_MASK_0_MSF_INT_MASK_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_MSF_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_MSF_INT_MASK_RANGE                        12:12
#define DC_CMD_HSM_INT_MASK_0_MSF_INT_MASK_WOFFSET                      0x0
#define DC_CMD_HSM_INT_MASK_0_MSF_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_MSF_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_MSF_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_MSF_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_MSF_INT_MASK_MASKED                       _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_MSF_INT_MASK_NOTMASKED                    _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_HEAD_UF_INT_MASK_SHIFT                    _MK_SHIFT_CONST(23)
#define DC_CMD_HSM_INT_MASK_0_HEAD_UF_INT_MASK_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_HEAD_UF_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_HEAD_UF_INT_MASK_RANGE                    23:23
#define DC_CMD_HSM_INT_MASK_0_HEAD_UF_INT_MASK_WOFFSET                  0x0
#define DC_CMD_HSM_INT_MASK_0_HEAD_UF_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_HEAD_UF_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_HEAD_UF_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_HEAD_UF_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_HEAD_UF_INT_MASK_MASKED                   _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_HEAD_UF_INT_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_SHIFT                       _MK_SHIFT_CONST(24)
#define DC_CMD_HSM_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_RANGE                       24:24
#define DC_CMD_HSM_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_WOFFSET                     0x0
#define DC_CMD_HSM_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_MASKED                      _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_SD3_BUCKET_WALK_DONE_INT_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_DSC_OBUF_UF_INT_MASK_SHIFT                        _MK_SHIFT_CONST(26)
#define DC_CMD_HSM_INT_MASK_0_DSC_OBUF_UF_INT_MASK_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_DSC_OBUF_UF_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_DSC_OBUF_UF_INT_MASK_RANGE                        26:26
#define DC_CMD_HSM_INT_MASK_0_DSC_OBUF_UF_INT_MASK_WOFFSET                      0x0
#define DC_CMD_HSM_INT_MASK_0_DSC_OBUF_UF_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_OBUF_UF_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_DSC_OBUF_UF_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_OBUF_UF_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_OBUF_UF_INT_MASK_MASKED                       _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_DSC_OBUF_UF_INT_MASK_NOTMASKED                    _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_DSC_RBUF_UF_INT_MASK_SHIFT                        _MK_SHIFT_CONST(27)
#define DC_CMD_HSM_INT_MASK_0_DSC_RBUF_UF_INT_MASK_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_DSC_RBUF_UF_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_DSC_RBUF_UF_INT_MASK_RANGE                        27:27
#define DC_CMD_HSM_INT_MASK_0_DSC_RBUF_UF_INT_MASK_WOFFSET                      0x0
#define DC_CMD_HSM_INT_MASK_0_DSC_RBUF_UF_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_RBUF_UF_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_DSC_RBUF_UF_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_RBUF_UF_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_RBUF_UF_INT_MASK_MASKED                       _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_DSC_RBUF_UF_INT_MASK_NOTMASKED                    _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_DSC_BBUF_UF_INT_MASK_SHIFT                        _MK_SHIFT_CONST(28)
#define DC_CMD_HSM_INT_MASK_0_DSC_BBUF_UF_INT_MASK_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_DSC_BBUF_UF_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_DSC_BBUF_UF_INT_MASK_RANGE                        28:28
#define DC_CMD_HSM_INT_MASK_0_DSC_BBUF_UF_INT_MASK_WOFFSET                      0x0
#define DC_CMD_HSM_INT_MASK_0_DSC_BBUF_UF_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_BBUF_UF_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_DSC_BBUF_UF_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_BBUF_UF_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_BBUF_UF_INT_MASK_MASKED                       _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_DSC_BBUF_UF_INT_MASK_NOTMASKED                    _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_MASK_0_DSC_TO_UF_INT_MASK_SHIFT                  _MK_SHIFT_CONST(29)
#define DC_CMD_HSM_INT_MASK_0_DSC_TO_UF_INT_MASK_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_MASK_0_DSC_TO_UF_INT_MASK_SHIFT)
#define DC_CMD_HSM_INT_MASK_0_DSC_TO_UF_INT_MASK_RANGE                  29:29
#define DC_CMD_HSM_INT_MASK_0_DSC_TO_UF_INT_MASK_WOFFSET                        0x0
#define DC_CMD_HSM_INT_MASK_0_DSC_TO_UF_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_TO_UF_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_MASK_0_DSC_TO_UF_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_TO_UF_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_MASK_0_DSC_TO_UF_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_MASK_0_DSC_TO_UF_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)


// Register DC_CMD_HSM_INT_ENABLE_0
#define DC_CMD_HSM_INT_ENABLE_0                 _MK_ADDR_CONST(0xc2)
#define DC_CMD_HSM_INT_ENABLE_0_SECURE                  0x0
#define DC_CMD_HSM_INT_ENABLE_0_SCR                     0
#define DC_CMD_HSM_INT_ENABLE_0_WORD_COUNT                      0x1
#define DC_CMD_HSM_INT_ENABLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_RESET_MASK                      _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_ENABLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_READ_MASK                       _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_ENABLE_0_WRITE_MASK                      _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_ENABLE_0_FRAME_END_INT_ENABLE_SHIFT                      _MK_SHIFT_CONST(1)
#define DC_CMD_HSM_INT_ENABLE_0_FRAME_END_INT_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_FRAME_END_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_FRAME_END_INT_ENABLE_RANGE                      1:1
#define DC_CMD_HSM_INT_ENABLE_0_FRAME_END_INT_ENABLE_WOFFSET                    0x0
#define DC_CMD_HSM_INT_ENABLE_0_FRAME_END_INT_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_FRAME_END_INT_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_FRAME_END_INT_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_FRAME_END_INT_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_FRAME_END_INT_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_FRAME_END_INT_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_V_BLANK_INT_ENABLE_SHIFT                        _MK_SHIFT_CONST(2)
#define DC_CMD_HSM_INT_ENABLE_0_V_BLANK_INT_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_V_BLANK_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_V_BLANK_INT_ENABLE_RANGE                        2:2
#define DC_CMD_HSM_INT_ENABLE_0_V_BLANK_INT_ENABLE_WOFFSET                      0x0
#define DC_CMD_HSM_INT_ENABLE_0_V_BLANK_INT_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_V_BLANK_INT_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_V_BLANK_INT_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_V_BLANK_INT_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_V_BLANK_INT_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_V_BLANK_INT_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SHIFT                       _MK_SHIFT_CONST(4)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE3_INT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE3_INT_ENABLE_RANGE                       4:4
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE3_INT_ENABLE_WOFFSET                     0x0
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE3_INT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE3_INT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE3_INT_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE3_INT_ENABLE_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SHIFT                       _MK_SHIFT_CONST(5)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE2_INT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE2_INT_ENABLE_RANGE                       5:5
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE2_INT_ENABLE_WOFFSET                     0x0
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE2_INT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE2_INT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE2_INT_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_V_PULSE2_INT_ENABLE_ENABLE                      _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_REGION_CRC_INT_ENABLE_SHIFT                     _MK_SHIFT_CONST(6)
#define DC_CMD_HSM_INT_ENABLE_0_REGION_CRC_INT_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_REGION_CRC_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_REGION_CRC_INT_ENABLE_RANGE                     6:6
#define DC_CMD_HSM_INT_ENABLE_0_REGION_CRC_INT_ENABLE_WOFFSET                   0x0
#define DC_CMD_HSM_INT_ENABLE_0_REGION_CRC_INT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_REGION_CRC_INT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_REGION_CRC_INT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_REGION_CRC_INT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_REGION_CRC_INT_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_REGION_CRC_INT_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_SHIFT                      _MK_SHIFT_CONST(7)
#define DC_CMD_HSM_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_RANGE                      7:7
#define DC_CMD_HSM_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_WOFFSET                    0x0
#define DC_CMD_HSM_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_REG_TMOUT_INT_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_MSF_INT_ENABLE_SHIFT                    _MK_SHIFT_CONST(12)
#define DC_CMD_HSM_INT_ENABLE_0_MSF_INT_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_MSF_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_MSF_INT_ENABLE_RANGE                    12:12
#define DC_CMD_HSM_INT_ENABLE_0_MSF_INT_ENABLE_WOFFSET                  0x0
#define DC_CMD_HSM_INT_ENABLE_0_MSF_INT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_MSF_INT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_MSF_INT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_MSF_INT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_MSF_INT_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_MSF_INT_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_HEAD_UF_INT_ENABLE_SHIFT                        _MK_SHIFT_CONST(23)
#define DC_CMD_HSM_INT_ENABLE_0_HEAD_UF_INT_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_HEAD_UF_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_HEAD_UF_INT_ENABLE_RANGE                        23:23
#define DC_CMD_HSM_INT_ENABLE_0_HEAD_UF_INT_ENABLE_WOFFSET                      0x0
#define DC_CMD_HSM_INT_ENABLE_0_HEAD_UF_INT_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_HEAD_UF_INT_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_HEAD_UF_INT_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_HEAD_UF_INT_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_HEAD_UF_INT_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_HEAD_UF_INT_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_SHIFT                   _MK_SHIFT_CONST(24)
#define DC_CMD_HSM_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_RANGE                   24:24
#define DC_CMD_HSM_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_WOFFSET                 0x0
#define DC_CMD_HSM_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_SD3_BUCKET_WALK_DONE_INT_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_SHIFT                    _MK_SHIFT_CONST(26)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_RANGE                    26:26
#define DC_CMD_HSM_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_WOFFSET                  0x0
#define DC_CMD_HSM_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_OBUF_UF_INT_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_SHIFT                    _MK_SHIFT_CONST(27)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_RANGE                    27:27
#define DC_CMD_HSM_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_WOFFSET                  0x0
#define DC_CMD_HSM_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_RBUF_UF_INT_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_SHIFT                    _MK_SHIFT_CONST(28)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_RANGE                    28:28
#define DC_CMD_HSM_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_WOFFSET                  0x0
#define DC_CMD_HSM_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_BBUF_UF_INT_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_SHIFT                      _MK_SHIFT_CONST(29)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_SHIFT)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_RANGE                      29:29
#define DC_CMD_HSM_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_WOFFSET                    0x0
#define DC_CMD_HSM_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_ENABLE_0_DSC_TO_UF_INT_ENABLE_ENABLE                     _MK_ENUM_CONST(1)


// Register DC_CMD_HSM_INT_TYPE_0
#define DC_CMD_HSM_INT_TYPE_0                   _MK_ADDR_CONST(0xc3)
#define DC_CMD_HSM_INT_TYPE_0_SECURE                    0x0
#define DC_CMD_HSM_INT_TYPE_0_SCR                       0
#define DC_CMD_HSM_INT_TYPE_0_WORD_COUNT                        0x1
#define DC_CMD_HSM_INT_TYPE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_RESET_MASK                        _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_TYPE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_READ_MASK                         _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_TYPE_0_WRITE_MASK                        _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_TYPE_0_FRAME_END_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(1)
#define DC_CMD_HSM_INT_TYPE_0_FRAME_END_INT_TYPE_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_FRAME_END_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_FRAME_END_INT_TYPE_RANGE                  1:1
#define DC_CMD_HSM_INT_TYPE_0_FRAME_END_INT_TYPE_WOFFSET                        0x0
#define DC_CMD_HSM_INT_TYPE_0_FRAME_END_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_FRAME_END_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_FRAME_END_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_FRAME_END_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_FRAME_END_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_FRAME_END_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_V_BLANK_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define DC_CMD_HSM_INT_TYPE_0_V_BLANK_INT_TYPE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_V_BLANK_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_V_BLANK_INT_TYPE_RANGE                    2:2
#define DC_CMD_HSM_INT_TYPE_0_V_BLANK_INT_TYPE_WOFFSET                  0x0
#define DC_CMD_HSM_INT_TYPE_0_V_BLANK_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_V_BLANK_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_V_BLANK_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_V_BLANK_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_V_BLANK_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_V_BLANK_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_V_PULSE3_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(4)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE3_INT_TYPE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_V_PULSE3_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE3_INT_TYPE_RANGE                   4:4
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE3_INT_TYPE_WOFFSET                 0x0
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE3_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE3_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE3_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE3_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE3_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE3_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_V_PULSE2_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(5)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE2_INT_TYPE_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_V_PULSE2_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE2_INT_TYPE_RANGE                   5:5
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE2_INT_TYPE_WOFFSET                 0x0
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE2_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE2_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE2_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE2_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE2_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_V_PULSE2_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_REGION_CRC_INT_TYPE_SHIFT                 _MK_SHIFT_CONST(6)
#define DC_CMD_HSM_INT_TYPE_0_REGION_CRC_INT_TYPE_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_REGION_CRC_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_REGION_CRC_INT_TYPE_RANGE                 6:6
#define DC_CMD_HSM_INT_TYPE_0_REGION_CRC_INT_TYPE_WOFFSET                       0x0
#define DC_CMD_HSM_INT_TYPE_0_REGION_CRC_INT_TYPE_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_REGION_CRC_INT_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_REGION_CRC_INT_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_REGION_CRC_INT_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_REGION_CRC_INT_TYPE_EDGE                  _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_REGION_CRC_INT_TYPE_LEVEL                 _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_REG_TMOUT_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(7)
#define DC_CMD_HSM_INT_TYPE_0_REG_TMOUT_INT_TYPE_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_REG_TMOUT_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_REG_TMOUT_INT_TYPE_RANGE                  7:7
#define DC_CMD_HSM_INT_TYPE_0_REG_TMOUT_INT_TYPE_WOFFSET                        0x0
#define DC_CMD_HSM_INT_TYPE_0_REG_TMOUT_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_REG_TMOUT_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_REG_TMOUT_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_REG_TMOUT_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_REG_TMOUT_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_REG_TMOUT_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_MSF_INT_TYPE_SHIFT                        _MK_SHIFT_CONST(12)
#define DC_CMD_HSM_INT_TYPE_0_MSF_INT_TYPE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_MSF_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_MSF_INT_TYPE_RANGE                        12:12
#define DC_CMD_HSM_INT_TYPE_0_MSF_INT_TYPE_WOFFSET                      0x0
#define DC_CMD_HSM_INT_TYPE_0_MSF_INT_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_MSF_INT_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_MSF_INT_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_MSF_INT_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_MSF_INT_TYPE_EDGE                 _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_MSF_INT_TYPE_LEVEL                        _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_HEAD_UF_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(23)
#define DC_CMD_HSM_INT_TYPE_0_HEAD_UF_INT_TYPE_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_HEAD_UF_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_HEAD_UF_INT_TYPE_RANGE                    23:23
#define DC_CMD_HSM_INT_TYPE_0_HEAD_UF_INT_TYPE_WOFFSET                  0x0
#define DC_CMD_HSM_INT_TYPE_0_HEAD_UF_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_HEAD_UF_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_HEAD_UF_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_HEAD_UF_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_HEAD_UF_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_HEAD_UF_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_SHIFT                       _MK_SHIFT_CONST(24)
#define DC_CMD_HSM_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_RANGE                       24:24
#define DC_CMD_HSM_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_WOFFSET                     0x0
#define DC_CMD_HSM_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_EDGE                        _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_SD3_BUCKET_WALK_DONE_INT_TYPE_LEVEL                       _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_SHIFT                        _MK_SHIFT_CONST(26)
#define DC_CMD_HSM_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_RANGE                        26:26
#define DC_CMD_HSM_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_WOFFSET                      0x0
#define DC_CMD_HSM_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_EDGE                 _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_OBUF_UF_INT_TYPE_LEVEL                        _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_SHIFT                        _MK_SHIFT_CONST(27)
#define DC_CMD_HSM_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_RANGE                        27:27
#define DC_CMD_HSM_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_WOFFSET                      0x0
#define DC_CMD_HSM_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_EDGE                 _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_RBUF_UF_INT_TYPE_LEVEL                        _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_SHIFT                        _MK_SHIFT_CONST(28)
#define DC_CMD_HSM_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_RANGE                        28:28
#define DC_CMD_HSM_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_WOFFSET                      0x0
#define DC_CMD_HSM_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_EDGE                 _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_BBUF_UF_INT_TYPE_LEVEL                        _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_TYPE_0_DSC_TO_UF_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(29)
#define DC_CMD_HSM_INT_TYPE_0_DSC_TO_UF_INT_TYPE_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_TYPE_0_DSC_TO_UF_INT_TYPE_SHIFT)
#define DC_CMD_HSM_INT_TYPE_0_DSC_TO_UF_INT_TYPE_RANGE                  29:29
#define DC_CMD_HSM_INT_TYPE_0_DSC_TO_UF_INT_TYPE_WOFFSET                        0x0
#define DC_CMD_HSM_INT_TYPE_0_DSC_TO_UF_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_TO_UF_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_TYPE_0_DSC_TO_UF_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_TO_UF_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_TO_UF_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_TYPE_0_DSC_TO_UF_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)


// Register DC_CMD_HSM_INT_POLARITY_0
#define DC_CMD_HSM_INT_POLARITY_0                       _MK_ADDR_CONST(0xc4)
#define DC_CMD_HSM_INT_POLARITY_0_SECURE                        0x0
#define DC_CMD_HSM_INT_POLARITY_0_SCR                   0
#define DC_CMD_HSM_INT_POLARITY_0_WORD_COUNT                    0x1
#define DC_CMD_HSM_INT_POLARITY_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_RESET_MASK                    _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_POLARITY_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_READ_MASK                     _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_POLARITY_0_WRITE_MASK                    _MK_MASK_CONST(0x3d8010f6)
#define DC_CMD_HSM_INT_POLARITY_0_FRAME_END_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(1)
#define DC_CMD_HSM_INT_POLARITY_0_FRAME_END_INT_POLARITY_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_FRAME_END_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_FRAME_END_INT_POLARITY_RANGE                  1:1
#define DC_CMD_HSM_INT_POLARITY_0_FRAME_END_INT_POLARITY_WOFFSET                        0x0
#define DC_CMD_HSM_INT_POLARITY_0_FRAME_END_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_FRAME_END_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_FRAME_END_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_FRAME_END_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_FRAME_END_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_FRAME_END_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_V_BLANK_INT_POLARITY_SHIFT                    _MK_SHIFT_CONST(2)
#define DC_CMD_HSM_INT_POLARITY_0_V_BLANK_INT_POLARITY_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_V_BLANK_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_V_BLANK_INT_POLARITY_RANGE                    2:2
#define DC_CMD_HSM_INT_POLARITY_0_V_BLANK_INT_POLARITY_WOFFSET                  0x0
#define DC_CMD_HSM_INT_POLARITY_0_V_BLANK_INT_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_V_BLANK_INT_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_V_BLANK_INT_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_V_BLANK_INT_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_V_BLANK_INT_POLARITY_LOW                      _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_V_BLANK_INT_POLARITY_HIGH                     _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(4)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE3_INT_POLARITY_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE3_INT_POLARITY_RANGE                   4:4
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE3_INT_POLARITY_WOFFSET                 0x0
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE3_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE3_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE3_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE3_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(5)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE2_INT_POLARITY_FIELD                   _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE2_INT_POLARITY_RANGE                   5:5
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE2_INT_POLARITY_WOFFSET                 0x0
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE2_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE2_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE2_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_V_PULSE2_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_REGION_CRC_INT_POLARITY_SHIFT                 _MK_SHIFT_CONST(6)
#define DC_CMD_HSM_INT_POLARITY_0_REGION_CRC_INT_POLARITY_FIELD                 _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_REGION_CRC_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_REGION_CRC_INT_POLARITY_RANGE                 6:6
#define DC_CMD_HSM_INT_POLARITY_0_REGION_CRC_INT_POLARITY_WOFFSET                       0x0
#define DC_CMD_HSM_INT_POLARITY_0_REGION_CRC_INT_POLARITY_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_REGION_CRC_INT_POLARITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_REGION_CRC_INT_POLARITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_REGION_CRC_INT_POLARITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_REGION_CRC_INT_POLARITY_LOW                   _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_REGION_CRC_INT_POLARITY_HIGH                  _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(7)
#define DC_CMD_HSM_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_RANGE                  7:7
#define DC_CMD_HSM_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_WOFFSET                        0x0
#define DC_CMD_HSM_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_REG_TMOUT_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_MSF_INT_POLARITY_SHIFT                        _MK_SHIFT_CONST(12)
#define DC_CMD_HSM_INT_POLARITY_0_MSF_INT_POLARITY_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_MSF_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_MSF_INT_POLARITY_RANGE                        12:12
#define DC_CMD_HSM_INT_POLARITY_0_MSF_INT_POLARITY_WOFFSET                      0x0
#define DC_CMD_HSM_INT_POLARITY_0_MSF_INT_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_MSF_INT_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_MSF_INT_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_MSF_INT_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_MSF_INT_POLARITY_LOW                  _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_MSF_INT_POLARITY_HIGH                 _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_HEAD_UF_INT_POLARITY_SHIFT                    _MK_SHIFT_CONST(23)
#define DC_CMD_HSM_INT_POLARITY_0_HEAD_UF_INT_POLARITY_FIELD                    _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_HEAD_UF_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_HEAD_UF_INT_POLARITY_RANGE                    23:23
#define DC_CMD_HSM_INT_POLARITY_0_HEAD_UF_INT_POLARITY_WOFFSET                  0x0
#define DC_CMD_HSM_INT_POLARITY_0_HEAD_UF_INT_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_HEAD_UF_INT_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_HEAD_UF_INT_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_HEAD_UF_INT_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_HEAD_UF_INT_POLARITY_LOW                      _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_HEAD_UF_INT_POLARITY_HIGH                     _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_SHIFT                       _MK_SHIFT_CONST(24)
#define DC_CMD_HSM_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_FIELD                       _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_RANGE                       24:24
#define DC_CMD_HSM_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_WOFFSET                     0x0
#define DC_CMD_HSM_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_LOW                 _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_SD3_BUCKET_WALK_DONE_INT_POLARITY_HIGH                        _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_SHIFT                        _MK_SHIFT_CONST(26)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_RANGE                        26:26
#define DC_CMD_HSM_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_WOFFSET                      0x0
#define DC_CMD_HSM_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_LOW                  _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_OBUF_UF_INT_POLARITY_HIGH                 _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_SHIFT                        _MK_SHIFT_CONST(27)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_RANGE                        27:27
#define DC_CMD_HSM_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_WOFFSET                      0x0
#define DC_CMD_HSM_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_LOW                  _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_RBUF_UF_INT_POLARITY_HIGH                 _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_SHIFT                        _MK_SHIFT_CONST(28)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_FIELD                        _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_RANGE                        28:28
#define DC_CMD_HSM_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_WOFFSET                      0x0
#define DC_CMD_HSM_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_LOW                  _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_BBUF_UF_INT_POLARITY_HIGH                 _MK_ENUM_CONST(1)

#define DC_CMD_HSM_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(29)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_FIELD                  _MK_FIELD_CONST(0x1, DC_CMD_HSM_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_SHIFT)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_RANGE                  29:29
#define DC_CMD_HSM_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_WOFFSET                        0x0
#define DC_CMD_HSM_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
#define DC_CMD_HSM_INT_POLARITY_0_DSC_TO_UF_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)


// Register DC_COM_CRC_CONTROL_0
#define DC_COM_CRC_CONTROL_0                    _MK_ADDR_CONST(0x300)
#define DC_COM_CRC_CONTROL_0_SECURE                     0x0
#define DC_COM_CRC_CONTROL_0_SCR                        0
#define DC_COM_CRC_CONTROL_0_WORD_COUNT                         0x1
#define DC_COM_CRC_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_CRC_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x5)
#define DC_COM_CRC_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_CRC_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_CRC_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x5)
#define DC_COM_CRC_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x5)
#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_COM_CRC_CONTROL_0_CRC_ENABLE_SHIFT)
#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_RANGE                   0:0
#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_WOFFSET                 0x0
#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(2)
#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_FIELD                       _MK_FIELD_CONST(0x1, DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_SHIFT)
#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_RANGE                       2:2
#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_WOFFSET                     0x0
#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_FULL_FRAME                  _MK_ENUM_CONST(0)
#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_ACTIVE_DATA                 _MK_ENUM_CONST(1)


// Register DC_COM_CORE_HEAD_SET_CRC_CONTROL_0
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0                      _MK_ADDR_CONST(0x301)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_SECURE                       0x0
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_SCR                  0
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_WORD_COUNT                   0x1
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_CRC_DURING_SNOOZE_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_CRC_DURING_SNOOZE_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_CRC_DURING_SNOOZE_SHIFT)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_CRC_DURING_SNOOZE_RANGE                      0:0
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_CRC_DURING_SNOOZE_WOFFSET                    0x0
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_CRC_DURING_SNOOZE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_CRC_DURING_SNOOZE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_CRC_DURING_SNOOZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_CRC_DURING_SNOOZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_CRC_DURING_SNOOZE_DISABLE                    _MK_ENUM_CONST(0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_CRC_DURING_SNOOZE_ENABLE                     _MK_ENUM_CONST(1)

#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_COLOR_DEPTH_AGNOSTIC_SHIFT                   _MK_SHIFT_CONST(1)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_COLOR_DEPTH_AGNOSTIC_FIELD                   _MK_FIELD_CONST(0x1, DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_COLOR_DEPTH_AGNOSTIC_SHIFT)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_COLOR_DEPTH_AGNOSTIC_RANGE                   1:1
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_COLOR_DEPTH_AGNOSTIC_WOFFSET                 0x0
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_COLOR_DEPTH_AGNOSTIC_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_COLOR_DEPTH_AGNOSTIC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_COLOR_DEPTH_AGNOSTIC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_COLOR_DEPTH_AGNOSTIC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_COLOR_DEPTH_AGNOSTIC_DISABLE                 _MK_ENUM_CONST(0)
#define DC_COM_CORE_HEAD_SET_CRC_CONTROL_0_COLOR_DEPTH_AGNOSTIC_ENABLE                  _MK_ENUM_CONST(1)


// Register DC_COM_SCRATCH_REGISTER_A_0
#define DC_COM_SCRATCH_REGISTER_A_0                     _MK_ADDR_CONST(0x325)
#define DC_COM_SCRATCH_REGISTER_A_0_SECURE                      0x0
#define DC_COM_SCRATCH_REGISTER_A_0_SCR                         0
#define DC_COM_SCRATCH_REGISTER_A_0_WORD_COUNT                  0x1
#define DC_COM_SCRATCH_REGISTER_A_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_SCRATCH_REGISTER_A_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_SCRATCH_REGISTER_A_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_SCRATCH_REGISTER_A_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_SCRATCH_REGISTER_A_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_SCRATCH_REGISTER_A_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_FIELD                    _MK_FIELD_CONST(0xffffffff, DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_SHIFT)
#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_RANGE                    31:0
#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_WOFFSET                  0x0
#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_COM_SCRATCH_REGISTER_B_0
#define DC_COM_SCRATCH_REGISTER_B_0                     _MK_ADDR_CONST(0x326)
#define DC_COM_SCRATCH_REGISTER_B_0_SECURE                      0x0
#define DC_COM_SCRATCH_REGISTER_B_0_SCR                         0
#define DC_COM_SCRATCH_REGISTER_B_0_WORD_COUNT                  0x1
#define DC_COM_SCRATCH_REGISTER_B_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_SCRATCH_REGISTER_B_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_SCRATCH_REGISTER_B_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_SCRATCH_REGISTER_B_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_SCRATCH_REGISTER_B_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_SCRATCH_REGISTER_B_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_FIELD                    _MK_FIELD_CONST(0xffffffff, DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_SHIFT)
#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_RANGE                    31:0
#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_WOFFSET                  0x0
#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_COM_COMP_CRCA_0
#define DC_COM_COMP_CRCA_0                      _MK_ADDR_CONST(0x32a)
#define DC_COM_COMP_CRCA_0_SECURE                       0x0
#define DC_COM_COMP_CRCA_0_SCR                  0
#define DC_COM_COMP_CRCA_0_WORD_COUNT                   0x1
#define DC_COM_COMP_CRCA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCA_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define DC_COM_COMP_CRCA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCA_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define DC_COM_COMP_CRCA_0_WRITE_MASK                   _MK_MASK_CONST(0x2)
#define DC_COM_COMP_CRCA_0_VALID_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_COMP_CRCA_0_VALID_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_COMP_CRCA_0_VALID_SHIFT)
#define DC_COM_COMP_CRCA_0_VALID_RANGE                  0:0
#define DC_COM_COMP_CRCA_0_VALID_WOFFSET                        0x0
#define DC_COM_COMP_CRCA_0_VALID_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCA_0_VALID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_COM_COMP_CRCA_0_VALID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCA_0_VALID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCA_0_VALID_FALSE                  _MK_ENUM_CONST(0)
#define DC_COM_COMP_CRCA_0_VALID_TRUE                   _MK_ENUM_CONST(1)

#define DC_COM_COMP_CRCA_0_ERROR_SHIFT                  _MK_SHIFT_CONST(1)
#define DC_COM_COMP_CRCA_0_ERROR_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_COMP_CRCA_0_ERROR_SHIFT)
#define DC_COM_COMP_CRCA_0_ERROR_RANGE                  1:1
#define DC_COM_COMP_CRCA_0_ERROR_WOFFSET                        0x0
#define DC_COM_COMP_CRCA_0_ERROR_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCA_0_ERROR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_COM_COMP_CRCA_0_ERROR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCA_0_ERROR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCA_0_ERROR_FALSE                  _MK_ENUM_CONST(0)
#define DC_COM_COMP_CRCA_0_ERROR_TRUE                   _MK_ENUM_CONST(1)
#define DC_COM_COMP_CRCA_0_ERROR_CLEAR                  _MK_ENUM_CONST(1)


// Register DC_COM_COMP_CRCB_0
#define DC_COM_COMP_CRCB_0                      _MK_ADDR_CONST(0x32b)
#define DC_COM_COMP_CRCB_0_SECURE                       0x0
#define DC_COM_COMP_CRCB_0_SCR                  0
#define DC_COM_COMP_CRCB_0_WORD_COUNT                   0x1
#define DC_COM_COMP_CRCB_0_RESET_VAL                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_CRCB_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_CRCB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCB_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_CRCB_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCB_0_CRC_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_COMP_CRCB_0_CRC_FIELD                    _MK_FIELD_CONST(0xffffffff, DC_COM_COMP_CRCB_0_CRC_SHIFT)
#define DC_COM_COMP_CRCB_0_CRC_RANGE                    31:0
#define DC_COM_COMP_CRCB_0_CRC_WOFFSET                  0x0
#define DC_COM_COMP_CRCB_0_CRC_DEFAULT                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_CRCB_0_CRC_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_CRCB_0_CRC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCB_0_CRC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CRCB_0_CRC_INIT_ENUM                        -1


// Register DC_COM_RG_CRCA_0
#define DC_COM_RG_CRCA_0                        _MK_ADDR_CONST(0x32c)
#define DC_COM_RG_CRCA_0_SECURE                         0x0
#define DC_COM_RG_CRCA_0_SCR                    0
#define DC_COM_RG_CRCA_0_WORD_COUNT                     0x1
#define DC_COM_RG_CRCA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCA_0_RESET_MASK                     _MK_MASK_CONST(0xf0003)
#define DC_COM_RG_CRCA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCA_0_READ_MASK                      _MK_MASK_CONST(0xf0003)
#define DC_COM_RG_CRCA_0_WRITE_MASK                     _MK_MASK_CONST(0x2)
#define DC_COM_RG_CRCA_0_VALID_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_RG_CRCA_0_VALID_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_CRCA_0_VALID_SHIFT)
#define DC_COM_RG_CRCA_0_VALID_RANGE                    0:0
#define DC_COM_RG_CRCA_0_VALID_WOFFSET                  0x0
#define DC_COM_RG_CRCA_0_VALID_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCA_0_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_CRCA_0_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCA_0_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCA_0_VALID_FALSE                    _MK_ENUM_CONST(0)
#define DC_COM_RG_CRCA_0_VALID_TRUE                     _MK_ENUM_CONST(1)

#define DC_COM_RG_CRCA_0_ERROR_SHIFT                    _MK_SHIFT_CONST(1)
#define DC_COM_RG_CRCA_0_ERROR_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_CRCA_0_ERROR_SHIFT)
#define DC_COM_RG_CRCA_0_ERROR_RANGE                    1:1
#define DC_COM_RG_CRCA_0_ERROR_WOFFSET                  0x0
#define DC_COM_RG_CRCA_0_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCA_0_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_CRCA_0_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCA_0_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCA_0_ERROR_FALSE                    _MK_ENUM_CONST(0)
#define DC_COM_RG_CRCA_0_ERROR_TRUE                     _MK_ENUM_CONST(1)
#define DC_COM_RG_CRCA_0_ERROR_CLEAR                    _MK_ENUM_CONST(1)

#define DC_COM_RG_CRCA_0_DTRPHASE_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_CRCA_0_DTRPHASE_FIELD                 _MK_FIELD_CONST(0xf, DC_COM_RG_CRCA_0_DTRPHASE_SHIFT)
#define DC_COM_RG_CRCA_0_DTRPHASE_RANGE                 19:16
#define DC_COM_RG_CRCA_0_DTRPHASE_WOFFSET                       0x0
#define DC_COM_RG_CRCA_0_DTRPHASE_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCA_0_DTRPHASE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define DC_COM_RG_CRCA_0_DTRPHASE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCA_0_DTRPHASE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_CRCB_0
#define DC_COM_RG_CRCB_0                        _MK_ADDR_CONST(0x32d)
#define DC_COM_RG_CRCB_0_SECURE                         0x0
#define DC_COM_RG_CRCB_0_SCR                    0
#define DC_COM_RG_CRCB_0_WORD_COUNT                     0x1
#define DC_COM_RG_CRCB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCB_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_CRCB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCB_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_CRCB_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCB_0_CRC_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_CRCB_0_CRC_FIELD                      _MK_FIELD_CONST(0xffffffff, DC_COM_RG_CRCB_0_CRC_SHIFT)
#define DC_COM_RG_CRCB_0_CRC_RANGE                      31:0
#define DC_COM_RG_CRCB_0_CRC_WOFFSET                    0x0
#define DC_COM_RG_CRCB_0_CRC_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCB_0_CRC_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_CRCB_0_CRC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_CRCB_0_CRC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_TOP_CTL_0
#define DC_COM_DSC_TOP_CTL_0                    _MK_ADDR_CONST(0x33e)
#define DC_COM_DSC_TOP_CTL_0_SECURE                     0x0
#define DC_COM_DSC_TOP_CTL_0_SCR                        0
#define DC_COM_DSC_TOP_CTL_0_WORD_COUNT                         0x1
#define DC_COM_DSC_TOP_CTL_0_RESET_VAL                  _MK_MASK_CONST(0xffff08)
#define DC_COM_DSC_TOP_CTL_0_RESET_MASK                         _MK_MASK_CONST(0xffff3f)
#define DC_COM_DSC_TOP_CTL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_READ_MASK                  _MK_MASK_CONST(0xffff3f)
#define DC_COM_DSC_TOP_CTL_0_WRITE_MASK                         _MK_MASK_CONST(0xffff3f)
#define DC_COM_DSC_TOP_CTL_0_DSC_SOFT_RESET_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_COM_DSC_TOP_CTL_0_DSC_SOFT_RESET_FIELD                       _MK_FIELD_CONST(0x1, DC_COM_DSC_TOP_CTL_0_DSC_SOFT_RESET_SHIFT)
#define DC_COM_DSC_TOP_CTL_0_DSC_SOFT_RESET_RANGE                       0:0
#define DC_COM_DSC_TOP_CTL_0_DSC_SOFT_RESET_WOFFSET                     0x0
#define DC_COM_DSC_TOP_CTL_0_DSC_SOFT_RESET_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_SOFT_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_COM_DSC_TOP_CTL_0_DSC_SOFT_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_SOFT_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_COM_DSC_TOP_CTL_0_DSC_ENABLE_SHIFT                   _MK_SHIFT_CONST(1)
#define DC_COM_DSC_TOP_CTL_0_DSC_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_COM_DSC_TOP_CTL_0_DSC_ENABLE_SHIFT)
#define DC_COM_DSC_TOP_CTL_0_DSC_ENABLE_RANGE                   1:1
#define DC_COM_DSC_TOP_CTL_0_DSC_ENABLE_WOFFSET                 0x0
#define DC_COM_DSC_TOP_CTL_0_DSC_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_COM_DSC_TOP_CTL_0_DSC_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_COM_DSC_TOP_CTL_0_DSC_SLCG_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(2)
#define DC_COM_DSC_TOP_CTL_0_DSC_SLCG_OVERRIDE_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_DSC_TOP_CTL_0_DSC_SLCG_OVERRIDE_SHIFT)
#define DC_COM_DSC_TOP_CTL_0_DSC_SLCG_OVERRIDE_RANGE                    2:2
#define DC_COM_DSC_TOP_CTL_0_DSC_SLCG_OVERRIDE_WOFFSET                  0x0
#define DC_COM_DSC_TOP_CTL_0_DSC_SLCG_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_SLCG_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_DSC_TOP_CTL_0_DSC_SLCG_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_SLCG_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_TOP_CTL_0_DSC_AUTO_RESET_SHIFT                       _MK_SHIFT_CONST(3)
#define DC_COM_DSC_TOP_CTL_0_DSC_AUTO_RESET_FIELD                       _MK_FIELD_CONST(0x1, DC_COM_DSC_TOP_CTL_0_DSC_AUTO_RESET_SHIFT)
#define DC_COM_DSC_TOP_CTL_0_DSC_AUTO_RESET_RANGE                       3:3
#define DC_COM_DSC_TOP_CTL_0_DSC_AUTO_RESET_WOFFSET                     0x0
#define DC_COM_DSC_TOP_CTL_0_DSC_AUTO_RESET_DEFAULT                     _MK_MASK_CONST(0x1)
#define DC_COM_DSC_TOP_CTL_0_DSC_AUTO_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_COM_DSC_TOP_CTL_0_DSC_AUTO_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_AUTO_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_COM_DSC_TOP_CTL_0_DSC_DUAL_ENABLE_SHIFT                      _MK_SHIFT_CONST(4)
#define DC_COM_DSC_TOP_CTL_0_DSC_DUAL_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_DSC_TOP_CTL_0_DSC_DUAL_ENABLE_SHIFT)
#define DC_COM_DSC_TOP_CTL_0_DSC_DUAL_ENABLE_RANGE                      4:4
#define DC_COM_DSC_TOP_CTL_0_DSC_DUAL_ENABLE_WOFFSET                    0x0
#define DC_COM_DSC_TOP_CTL_0_DSC_DUAL_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_DUAL_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_DSC_TOP_CTL_0_DSC_DUAL_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_DUAL_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_DSC_TOP_CTL_0_DSC_FORCE_ICH_EOL_RESET_SHIFT                      _MK_SHIFT_CONST(5)
#define DC_COM_DSC_TOP_CTL_0_DSC_FORCE_ICH_EOL_RESET_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_DSC_TOP_CTL_0_DSC_FORCE_ICH_EOL_RESET_SHIFT)
#define DC_COM_DSC_TOP_CTL_0_DSC_FORCE_ICH_EOL_RESET_RANGE                      5:5
#define DC_COM_DSC_TOP_CTL_0_DSC_FORCE_ICH_EOL_RESET_WOFFSET                    0x0
#define DC_COM_DSC_TOP_CTL_0_DSC_FORCE_ICH_EOL_RESET_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_FORCE_ICH_EOL_RESET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_DSC_TOP_CTL_0_DSC_FORCE_ICH_EOL_RESET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_FORCE_ICH_EOL_RESET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_DSC_TOP_CTL_0_DSC_TIMEOUT_COUNTER_SHIFT                  _MK_SHIFT_CONST(8)
#define DC_COM_DSC_TOP_CTL_0_DSC_TIMEOUT_COUNTER_FIELD                  _MK_FIELD_CONST(0xffff, DC_COM_DSC_TOP_CTL_0_DSC_TIMEOUT_COUNTER_SHIFT)
#define DC_COM_DSC_TOP_CTL_0_DSC_TIMEOUT_COUNTER_RANGE                  23:8
#define DC_COM_DSC_TOP_CTL_0_DSC_TIMEOUT_COUNTER_WOFFSET                        0x0
#define DC_COM_DSC_TOP_CTL_0_DSC_TIMEOUT_COUNTER_DEFAULT                        _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_TOP_CTL_0_DSC_TIMEOUT_COUNTER_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_TOP_CTL_0_DSC_TIMEOUT_COUNTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_TOP_CTL_0_DSC_TIMEOUT_COUNTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_DELAY_0
#define DC_COM_DSC_DELAY_0                      _MK_ADDR_CONST(0x33f)
#define DC_COM_DSC_DELAY_0_SECURE                       0x0
#define DC_COM_DSC_DELAY_0_SCR                  0
#define DC_COM_DSC_DELAY_0_WORD_COUNT                   0x1
#define DC_COM_DSC_DELAY_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_DELAY_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_DELAY_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_DELAY_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_DELAY_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_DELAY_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_DELAY_0_DSC_CORE_OUTPUT_DELAY_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_DSC_DELAY_0_DSC_CORE_OUTPUT_DELAY_FIELD                  _MK_FIELD_CONST(0xffff, DC_COM_DSC_DELAY_0_DSC_CORE_OUTPUT_DELAY_SHIFT)
#define DC_COM_DSC_DELAY_0_DSC_CORE_OUTPUT_DELAY_RANGE                  15:0
#define DC_COM_DSC_DELAY_0_DSC_CORE_OUTPUT_DELAY_WOFFSET                        0x0
#define DC_COM_DSC_DELAY_0_DSC_CORE_OUTPUT_DELAY_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_DELAY_0_DSC_CORE_OUTPUT_DELAY_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_DELAY_0_DSC_CORE_OUTPUT_DELAY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_DELAY_0_DSC_CORE_OUTPUT_DELAY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_DSC_DELAY_0_DSC_WRAP_OUTPUT_DELAY_SHIFT                  _MK_SHIFT_CONST(16)
#define DC_COM_DSC_DELAY_0_DSC_WRAP_OUTPUT_DELAY_FIELD                  _MK_FIELD_CONST(0xffff, DC_COM_DSC_DELAY_0_DSC_WRAP_OUTPUT_DELAY_SHIFT)
#define DC_COM_DSC_DELAY_0_DSC_WRAP_OUTPUT_DELAY_RANGE                  31:16
#define DC_COM_DSC_DELAY_0_DSC_WRAP_OUTPUT_DELAY_WOFFSET                        0x0
#define DC_COM_DSC_DELAY_0_DSC_WRAP_OUTPUT_DELAY_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_DELAY_0_DSC_WRAP_OUTPUT_DELAY_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_DELAY_0_DSC_WRAP_OUTPUT_DELAY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_DELAY_0_DSC_WRAP_OUTPUT_DELAY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_COMMON_CTL_0
#define DC_COM_DSC_COMMON_CTL_0                 _MK_ADDR_CONST(0x340)
#define DC_COM_DSC_COMMON_CTL_0_SECURE                  0x0
#define DC_COM_DSC_COMMON_CTL_0_SCR                     0
#define DC_COM_DSC_COMMON_CTL_0_WORD_COUNT                      0x1
#define DC_COM_DSC_COMMON_CTL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_COMMON_CTL_0_RESET_MASK                      _MK_MASK_CONST(0xffff07ff)
#define DC_COM_DSC_COMMON_CTL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_COMMON_CTL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_DSC_COMMON_CTL_0_READ_MASK                       _MK_MASK_CONST(0xffff07ff)
#define DC_COM_DSC_COMMON_CTL_0_WRITE_MASK                      _MK_MASK_CONST(0xffff07ff)
#define DC_COM_DSC_COMMON_CTL_0_DSC_BITS_PER_PIXEL_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_DSC_COMMON_CTL_0_DSC_BITS_PER_PIXEL_FIELD                        _MK_FIELD_CONST(0x3ff, DC_COM_DSC_COMMON_CTL_0_DSC_BITS_PER_PIXEL_SHIFT)
#define DC_COM_DSC_COMMON_CTL_0_DSC_BITS_PER_PIXEL_RANGE                        9:0
#define DC_COM_DSC_COMMON_CTL_0_DSC_BITS_PER_PIXEL_WOFFSET                      0x0
#define DC_COM_DSC_COMMON_CTL_0_DSC_BITS_PER_PIXEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_COMMON_CTL_0_DSC_BITS_PER_PIXEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
#define DC_COM_DSC_COMMON_CTL_0_DSC_BITS_PER_PIXEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_COMMON_CTL_0_DSC_BITS_PER_PIXEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_COM_DSC_COMMON_CTL_0_DSC_BLOCK_PRED_ENABLE_SHIFT                     _MK_SHIFT_CONST(10)
#define DC_COM_DSC_COMMON_CTL_0_DSC_BLOCK_PRED_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, DC_COM_DSC_COMMON_CTL_0_DSC_BLOCK_PRED_ENABLE_SHIFT)
#define DC_COM_DSC_COMMON_CTL_0_DSC_BLOCK_PRED_ENABLE_RANGE                     10:10
#define DC_COM_DSC_COMMON_CTL_0_DSC_BLOCK_PRED_ENABLE_WOFFSET                   0x0
#define DC_COM_DSC_COMMON_CTL_0_DSC_BLOCK_PRED_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_COMMON_CTL_0_DSC_BLOCK_PRED_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_COM_DSC_COMMON_CTL_0_DSC_BLOCK_PRED_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_COMMON_CTL_0_DSC_BLOCK_PRED_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_COMMON_CTL_0_DSC_CHUNK_SIZE_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_COM_DSC_COMMON_CTL_0_DSC_CHUNK_SIZE_FIELD                    _MK_FIELD_CONST(0xffff, DC_COM_DSC_COMMON_CTL_0_DSC_CHUNK_SIZE_SHIFT)
#define DC_COM_DSC_COMMON_CTL_0_DSC_CHUNK_SIZE_RANGE                    31:16
#define DC_COM_DSC_COMMON_CTL_0_DSC_CHUNK_SIZE_WOFFSET                  0x0
#define DC_COM_DSC_COMMON_CTL_0_DSC_CHUNK_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_COMMON_CTL_0_DSC_CHUNK_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_COMMON_CTL_0_DSC_CHUNK_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_COMMON_CTL_0_DSC_CHUNK_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_SLICE_INFO_0
#define DC_COM_DSC_SLICE_INFO_0                 _MK_ADDR_CONST(0x341)
#define DC_COM_DSC_SLICE_INFO_0_SECURE                  0x0
#define DC_COM_DSC_SLICE_INFO_0_SCR                     0
#define DC_COM_DSC_SLICE_INFO_0_WORD_COUNT                      0x1
#define DC_COM_DSC_SLICE_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_SLICE_INFO_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_SLICE_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_SLICE_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_DSC_SLICE_INFO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_SLICE_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_WIDTH_FIELD                   _MK_FIELD_CONST(0xffff, DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_WIDTH_SHIFT)
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_WIDTH_RANGE                   15:0
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_WIDTH_WOFFSET                 0x0
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_HEIGHT_SHIFT                  _MK_SHIFT_CONST(16)
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_HEIGHT_FIELD                  _MK_FIELD_CONST(0xffff, DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_HEIGHT_SHIFT)
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_HEIGHT_RANGE                  31:16
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_HEIGHT_WOFFSET                        0x0
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_HEIGHT_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_HEIGHT_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_HEIGHT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_SLICE_INFO_0_DSC_SLICE_HEIGHT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_DELAY_INFO_0
#define DC_COM_DSC_RC_DELAY_INFO_0                      _MK_ADDR_CONST(0x342)
#define DC_COM_DSC_RC_DELAY_INFO_0_SECURE                       0x0
#define DC_COM_DSC_RC_DELAY_INFO_0_SCR                  0
#define DC_COM_DSC_RC_DELAY_INFO_0_WORD_COUNT                   0x1
#define DC_COM_DSC_RC_DELAY_INFO_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_DELAY_INFO_0_RESET_MASK                   _MK_MASK_CONST(0xffff03ff)
#define DC_COM_DSC_RC_DELAY_INFO_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_DELAY_INFO_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_DELAY_INFO_0_READ_MASK                    _MK_MASK_CONST(0xffff03ff)
#define DC_COM_DSC_RC_DELAY_INFO_0_WRITE_MASK                   _MK_MASK_CONST(0xffff03ff)
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_XMIT_DELAY_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_XMIT_DELAY_FIELD                 _MK_FIELD_CONST(0x3ff, DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_XMIT_DELAY_SHIFT)
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_XMIT_DELAY_RANGE                 9:0
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_XMIT_DELAY_WOFFSET                       0x0
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_XMIT_DELAY_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_XMIT_DELAY_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_XMIT_DELAY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_XMIT_DELAY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_DEC_DELAY_SHIFT                  _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_DEC_DELAY_FIELD                  _MK_FIELD_CONST(0xffff, DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_DEC_DELAY_SHIFT)
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_DEC_DELAY_RANGE                  31:16
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_DEC_DELAY_WOFFSET                        0x0
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_DEC_DELAY_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_DEC_DELAY_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_DEC_DELAY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_DELAY_INFO_0_DSC_INITIAL_DEC_DELAY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_SCALE_INFO_0
#define DC_COM_DSC_RC_SCALE_INFO_0                      _MK_ADDR_CONST(0x343)
#define DC_COM_DSC_RC_SCALE_INFO_0_SECURE                       0x0
#define DC_COM_DSC_RC_SCALE_INFO_0_SCR                  0
#define DC_COM_DSC_RC_SCALE_INFO_0_WORD_COUNT                   0x1
#define DC_COM_DSC_RC_SCALE_INFO_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_0_RESET_MASK                   _MK_MASK_CONST(0x3fffff)
#define DC_COM_DSC_RC_SCALE_INFO_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_0_READ_MASK                    _MK_MASK_CONST(0x3fffff)
#define DC_COM_DSC_RC_SCALE_INFO_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffff)
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_INITIAL_SCALE_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_INITIAL_SCALE_VALUE_FIELD                        _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_SCALE_INFO_0_DSC_INITIAL_SCALE_VALUE_SHIFT)
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_INITIAL_SCALE_VALUE_RANGE                        5:0
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_INITIAL_SCALE_VALUE_WOFFSET                      0x0
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_INITIAL_SCALE_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_INITIAL_SCALE_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_INITIAL_SCALE_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_INITIAL_SCALE_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_SCALE_DECR_INTERVAL_SHIFT                        _MK_SHIFT_CONST(6)
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_SCALE_DECR_INTERVAL_FIELD                        _MK_FIELD_CONST(0xffff, DC_COM_DSC_RC_SCALE_INFO_0_DSC_SCALE_DECR_INTERVAL_SHIFT)
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_SCALE_DECR_INTERVAL_RANGE                        21:6
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_SCALE_DECR_INTERVAL_WOFFSET                      0x0
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_SCALE_DECR_INTERVAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_SCALE_DECR_INTERVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_SCALE_DECR_INTERVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_0_DSC_SCALE_DECR_INTERVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_SCALE_INFO_2_0
#define DC_COM_DSC_RC_SCALE_INFO_2_0                    _MK_ADDR_CONST(0x344)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_SECURE                     0x0
#define DC_COM_DSC_RC_SCALE_INFO_2_0_SCR                        0
#define DC_COM_DSC_RC_SCALE_INFO_2_0_WORD_COUNT                         0x1
#define DC_COM_DSC_RC_SCALE_INFO_2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_READ_MASK                  _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_DSC_SCALE_INCR_INTERVAL_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_DSC_SCALE_INCR_INTERVAL_FIELD                      _MK_FIELD_CONST(0xffff, DC_COM_DSC_RC_SCALE_INFO_2_0_DSC_SCALE_INCR_INTERVAL_SHIFT)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_DSC_SCALE_INCR_INTERVAL_RANGE                      15:0
#define DC_COM_DSC_RC_SCALE_INFO_2_0_DSC_SCALE_INCR_INTERVAL_WOFFSET                    0x0
#define DC_COM_DSC_RC_SCALE_INFO_2_0_DSC_SCALE_INCR_INTERVAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_DSC_SCALE_INCR_INTERVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_DSC_SCALE_INCR_INTERVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_SCALE_INFO_2_0_DSC_SCALE_INCR_INTERVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_BPGOFF_INFO_0
#define DC_COM_DSC_RC_BPGOFF_INFO_0                     _MK_ADDR_CONST(0x345)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_SECURE                      0x0
#define DC_COM_DSC_RC_BPGOFF_INFO_0_SCR                         0
#define DC_COM_DSC_RC_BPGOFF_INFO_0_WORD_COUNT                  0x1
#define DC_COM_DSC_RC_BPGOFF_INFO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_NFL_BPG_OFFSET_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_NFL_BPG_OFFSET_FIELD                    _MK_FIELD_CONST(0xffff, DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_NFL_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_NFL_BPG_OFFSET_RANGE                    15:0
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_NFL_BPG_OFFSET_WOFFSET                  0x0
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_NFL_BPG_OFFSET_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_NFL_BPG_OFFSET_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_NFL_BPG_OFFSET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_NFL_BPG_OFFSET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_SLICE_BPG_OFFSET_SHIFT                  _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_SLICE_BPG_OFFSET_FIELD                  _MK_FIELD_CONST(0xffff, DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_SLICE_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_SLICE_BPG_OFFSET_RANGE                  31:16
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_SLICE_BPG_OFFSET_WOFFSET                        0x0
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_SLICE_BPG_OFFSET_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_SLICE_BPG_OFFSET_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_SLICE_BPG_OFFSET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BPGOFF_INFO_0_DSC_SLICE_BPG_OFFSET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_OFFSET_INFO_0
#define DC_COM_DSC_RC_OFFSET_INFO_0                     _MK_ADDR_CONST(0x346)
#define DC_COM_DSC_RC_OFFSET_INFO_0_SECURE                      0x0
#define DC_COM_DSC_RC_OFFSET_INFO_0_SCR                         0
#define DC_COM_DSC_RC_OFFSET_INFO_0_WORD_COUNT                  0x1
#define DC_COM_DSC_RC_OFFSET_INFO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_OFFSET_INFO_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_OFFSET_INFO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_OFFSET_INFO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_OFFSET_INFO_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_OFFSET_INFO_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_INITIAL_OFFSET_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_INITIAL_OFFSET_FIELD                    _MK_FIELD_CONST(0xffff, DC_COM_DSC_RC_OFFSET_INFO_0_DSC_INITIAL_OFFSET_SHIFT)
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_INITIAL_OFFSET_RANGE                    15:0
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_INITIAL_OFFSET_WOFFSET                  0x0
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_INITIAL_OFFSET_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_INITIAL_OFFSET_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_INITIAL_OFFSET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_INITIAL_OFFSET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_FINAL_OFFSET_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_FINAL_OFFSET_FIELD                      _MK_FIELD_CONST(0xffff, DC_COM_DSC_RC_OFFSET_INFO_0_DSC_FINAL_OFFSET_SHIFT)
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_FINAL_OFFSET_RANGE                      31:16
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_FINAL_OFFSET_WOFFSET                    0x0
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_FINAL_OFFSET_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_FINAL_OFFSET_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_FINAL_OFFSET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_OFFSET_INFO_0_DSC_FINAL_OFFSET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_FLATNESS_INFO_0
#define DC_COM_DSC_RC_FLATNESS_INFO_0                   _MK_ADDR_CONST(0x347)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_SECURE                    0x0
#define DC_COM_DSC_RC_FLATNESS_INFO_0_SCR                       0
#define DC_COM_DSC_RC_FLATNESS_INFO_0_WORD_COUNT                        0x1
#define DC_COM_DSC_RC_FLATNESS_INFO_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_RESET_MASK                        _MK_MASK_CONST(0x7fff)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_READ_MASK                         _MK_MASK_CONST(0x7fff)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MIN_QP_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MIN_QP_FIELD                 _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MIN_QP_RANGE                 4:0
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MIN_QP_WOFFSET                       0x0
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MIN_QP_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MIN_QP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MIN_QP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MIN_QP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MAX_QP_SHIFT                 _MK_SHIFT_CONST(5)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MAX_QP_FIELD                 _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MAX_QP_RANGE                 9:5
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MAX_QP_WOFFSET                       0x0
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MAX_QP_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MAX_QP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MAX_QP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FLATNESS_MAX_QP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FIRST_LINE_BPG_OFFS_SHIFT                     _MK_SHIFT_CONST(10)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FIRST_LINE_BPG_OFFS_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FIRST_LINE_BPG_OFFS_SHIFT)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FIRST_LINE_BPG_OFFS_RANGE                     14:10
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FIRST_LINE_BPG_OFFS_WOFFSET                   0x0
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FIRST_LINE_BPG_OFFS_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FIRST_LINE_BPG_OFFS_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FIRST_LINE_BPG_OFFS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_FLATNESS_INFO_0_DSC_FIRST_LINE_BPG_OFFS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_PARAM_SET_0
#define DC_COM_DSC_RC_PARAM_SET_0                       _MK_ADDR_CONST(0x348)
#define DC_COM_DSC_RC_PARAM_SET_0_SECURE                        0x0
#define DC_COM_DSC_RC_PARAM_SET_0_SCR                   0
#define DC_COM_DSC_RC_PARAM_SET_0_WORD_COUNT                    0x1
#define DC_COM_DSC_RC_PARAM_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_RESET_MASK                    _MK_MASK_CONST(0x3fffff)
#define DC_COM_DSC_RC_PARAM_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_READ_MASK                     _MK_MASK_CONST(0x3fffff)
#define DC_COM_DSC_RC_PARAM_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffff)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_EDGE_FACTOR_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_EDGE_FACTOR_FIELD                      _MK_FIELD_CONST(0xf, DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_EDGE_FACTOR_SHIFT)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_EDGE_FACTOR_RANGE                      3:0
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_EDGE_FACTOR_WOFFSET                    0x0
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_EDGE_FACTOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_EDGE_FACTOR_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_EDGE_FACTOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_EDGE_FACTOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT0_SHIFT                        _MK_SHIFT_CONST(4)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT0_FIELD                        _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT0_SHIFT)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT0_RANGE                        8:4
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT0_WOFFSET                      0x0
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT0_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT0_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT1_SHIFT                        _MK_SHIFT_CONST(9)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT1_FIELD                        _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT1_SHIFT)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT1_RANGE                        13:9
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT1_WOFFSET                      0x0
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT1_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT1_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_QUANT_INCR_LIMIT1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_HI_SHIFT                    _MK_SHIFT_CONST(14)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_HI_FIELD                    _MK_FIELD_CONST(0xf, DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_HI_SHIFT)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_HI_RANGE                    17:14
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_HI_WOFFSET                  0x0
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_HI_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_HI_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_HI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_HI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_LO_SHIFT                    _MK_SHIFT_CONST(18)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_LO_FIELD                    _MK_FIELD_CONST(0xf, DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_LO_SHIFT)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_LO_RANGE                    21:18
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_LO_WOFFSET                  0x0
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_LO_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_LO_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_LO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_PARAM_SET_0_DSC_RC_TGT_OFFSET_LO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_BUF_THRESH0_0
#define DC_COM_DSC_RC_BUF_THRESH0_0                     _MK_ADDR_CONST(0x349)
#define DC_COM_DSC_RC_BUF_THRESH0_0_SECURE                      0x0
#define DC_COM_DSC_RC_BUF_THRESH0_0_SCR                         0
#define DC_COM_DSC_RC_BUF_THRESH0_0_WORD_COUNT                  0x1
#define DC_COM_DSC_RC_BUF_THRESH0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_MODEL_SIZE_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_MODEL_SIZE_FIELD                     _MK_FIELD_CONST(0xffff, DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_MODEL_SIZE_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_MODEL_SIZE_RANGE                     15:0
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_MODEL_SIZE_WOFFSET                   0x0
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_MODEL_SIZE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_MODEL_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_MODEL_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_MODEL_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH0_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH0_FIELD                    _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH0_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH0_RANGE                    23:16
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH0_WOFFSET                  0x0
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH0_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH0_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH1_SHIFT                    _MK_SHIFT_CONST(24)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH1_FIELD                    _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH1_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH1_RANGE                    31:24
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH1_WOFFSET                  0x0
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH1_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH1_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH0_0_DSC_RC_BUF_THRESH1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_BUF_THRESH1_0
#define DC_COM_DSC_RC_BUF_THRESH1_0                     _MK_ADDR_CONST(0x34a)
#define DC_COM_DSC_RC_BUF_THRESH1_0_SECURE                      0x0
#define DC_COM_DSC_RC_BUF_THRESH1_0_SCR                         0
#define DC_COM_DSC_RC_BUF_THRESH1_0_WORD_COUNT                  0x1
#define DC_COM_DSC_RC_BUF_THRESH1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH2_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH2_FIELD                    _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH2_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH2_RANGE                    7:0
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH2_WOFFSET                  0x0
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH2_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH2_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH3_SHIFT                    _MK_SHIFT_CONST(8)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH3_FIELD                    _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH3_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH3_RANGE                    15:8
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH3_WOFFSET                  0x0
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH3_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH3_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH4_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH4_FIELD                    _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH4_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH4_RANGE                    23:16
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH4_WOFFSET                  0x0
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH4_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH4_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH5_SHIFT                    _MK_SHIFT_CONST(24)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH5_FIELD                    _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH5_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH5_RANGE                    31:24
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH5_WOFFSET                  0x0
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH5_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH5_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH1_0_DSC_RC_BUF_THRESH5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_BUF_THRESH2_0
#define DC_COM_DSC_RC_BUF_THRESH2_0                     _MK_ADDR_CONST(0x34b)
#define DC_COM_DSC_RC_BUF_THRESH2_0_SECURE                      0x0
#define DC_COM_DSC_RC_BUF_THRESH2_0_SCR                         0
#define DC_COM_DSC_RC_BUF_THRESH2_0_WORD_COUNT                  0x1
#define DC_COM_DSC_RC_BUF_THRESH2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH6_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH6_FIELD                    _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH6_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH6_RANGE                    7:0
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH6_WOFFSET                  0x0
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH6_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH6_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH7_SHIFT                    _MK_SHIFT_CONST(8)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH7_FIELD                    _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH7_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH7_RANGE                    15:8
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH7_WOFFSET                  0x0
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH7_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH7_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH8_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH8_FIELD                    _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH8_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH8_RANGE                    23:16
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH8_WOFFSET                  0x0
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH8_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH8_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH9_SHIFT                    _MK_SHIFT_CONST(24)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH9_FIELD                    _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH9_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH9_RANGE                    31:24
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH9_WOFFSET                  0x0
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH9_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH9_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH2_0_DSC_RC_BUF_THRESH9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_BUF_THRESH3_0
#define DC_COM_DSC_RC_BUF_THRESH3_0                     _MK_ADDR_CONST(0x34c)
#define DC_COM_DSC_RC_BUF_THRESH3_0_SECURE                      0x0
#define DC_COM_DSC_RC_BUF_THRESH3_0_SCR                         0
#define DC_COM_DSC_RC_BUF_THRESH3_0_WORD_COUNT                  0x1
#define DC_COM_DSC_RC_BUF_THRESH3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH3_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH10_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH10_FIELD                   _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH10_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH10_RANGE                   7:0
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH10_WOFFSET                 0x0
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH10_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH10_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH10_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH10_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH11_SHIFT                   _MK_SHIFT_CONST(8)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH11_FIELD                   _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH11_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH11_RANGE                   15:8
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH11_WOFFSET                 0x0
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH11_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH11_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH11_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH11_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH12_SHIFT                   _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH12_FIELD                   _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH12_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH12_RANGE                   23:16
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH12_WOFFSET                 0x0
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH12_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH12_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH12_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH12_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH13_SHIFT                   _MK_SHIFT_CONST(24)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH13_FIELD                   _MK_FIELD_CONST(0xff, DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH13_SHIFT)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH13_RANGE                   31:24
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH13_WOFFSET                 0x0
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH13_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH13_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH13_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_BUF_THRESH3_0_DSC_RC_BUF_THRESH13_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_RANGE_CFG0_0
#define DC_COM_DSC_RC_RANGE_CFG0_0                      _MK_ADDR_CONST(0x34d)
#define DC_COM_DSC_RC_RANGE_CFG0_0_SECURE                       0x0
#define DC_COM_DSC_RC_RANGE_CFG0_0_SCR                  0
#define DC_COM_DSC_RC_RANGE_CFG0_0_WORD_COUNT                   0x1
#define DC_COM_DSC_RC_RANGE_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MIN_QP_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MIN_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MIN_QP_RANGE                     4:0
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MIN_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MIN_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MIN_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MIN_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MIN_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MAX_QP_SHIFT                     _MK_SHIFT_CONST(5)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MAX_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MAX_QP_RANGE                     9:5
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MAX_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MAX_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MAX_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MAX_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_MAX_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_BPG_OFFSET_SHIFT                 _MK_SHIFT_CONST(10)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_BPG_OFFSET_FIELD                 _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_BPG_OFFSET_RANGE                 15:10
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_BPG_OFFSET_WOFFSET                       0x0
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_BPG_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_BPG_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_BPG_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM0_BPG_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MIN_QP_SHIFT                     _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MIN_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MIN_QP_RANGE                     20:16
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MIN_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MIN_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MIN_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MIN_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MIN_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MAX_QP_SHIFT                     _MK_SHIFT_CONST(21)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MAX_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MAX_QP_RANGE                     25:21
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MAX_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MAX_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MAX_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MAX_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_MAX_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_BPG_OFFSET_SHIFT                 _MK_SHIFT_CONST(26)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_BPG_OFFSET_FIELD                 _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_BPG_OFFSET_RANGE                 31:26
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_BPG_OFFSET_WOFFSET                       0x0
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_BPG_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_BPG_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_BPG_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG0_0_DSC_RC_RANGE_PARAM1_BPG_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_RANGE_CFG1_0
#define DC_COM_DSC_RC_RANGE_CFG1_0                      _MK_ADDR_CONST(0x34e)
#define DC_COM_DSC_RC_RANGE_CFG1_0_SECURE                       0x0
#define DC_COM_DSC_RC_RANGE_CFG1_0_SCR                  0
#define DC_COM_DSC_RC_RANGE_CFG1_0_WORD_COUNT                   0x1
#define DC_COM_DSC_RC_RANGE_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MIN_QP_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MIN_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MIN_QP_RANGE                     4:0
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MIN_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MIN_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MIN_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MIN_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MIN_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MAX_QP_SHIFT                     _MK_SHIFT_CONST(5)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MAX_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MAX_QP_RANGE                     9:5
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MAX_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MAX_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MAX_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MAX_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_MAX_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_BPG_OFFSET_SHIFT                 _MK_SHIFT_CONST(10)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_BPG_OFFSET_FIELD                 _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_BPG_OFFSET_RANGE                 15:10
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_BPG_OFFSET_WOFFSET                       0x0
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_BPG_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_BPG_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_BPG_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM2_BPG_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MIN_QP_SHIFT                     _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MIN_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MIN_QP_RANGE                     20:16
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MIN_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MIN_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MIN_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MIN_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MIN_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MAX_QP_SHIFT                     _MK_SHIFT_CONST(21)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MAX_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MAX_QP_RANGE                     25:21
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MAX_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MAX_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MAX_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MAX_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_MAX_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_BPG_OFFSET_SHIFT                 _MK_SHIFT_CONST(26)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_BPG_OFFSET_FIELD                 _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_BPG_OFFSET_RANGE                 31:26
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_BPG_OFFSET_WOFFSET                       0x0
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_BPG_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_BPG_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_BPG_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG1_0_DSC_RC_RANGE_PARAM3_BPG_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_RANGE_CFG2_0
#define DC_COM_DSC_RC_RANGE_CFG2_0                      _MK_ADDR_CONST(0x34f)
#define DC_COM_DSC_RC_RANGE_CFG2_0_SECURE                       0x0
#define DC_COM_DSC_RC_RANGE_CFG2_0_SCR                  0
#define DC_COM_DSC_RC_RANGE_CFG2_0_WORD_COUNT                   0x1
#define DC_COM_DSC_RC_RANGE_CFG2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MIN_QP_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MIN_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MIN_QP_RANGE                     4:0
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MIN_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MIN_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MIN_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MIN_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MIN_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MAX_QP_SHIFT                     _MK_SHIFT_CONST(5)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MAX_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MAX_QP_RANGE                     9:5
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MAX_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MAX_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MAX_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MAX_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_MAX_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_BPG_OFFSET_SHIFT                 _MK_SHIFT_CONST(10)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_BPG_OFFSET_FIELD                 _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_BPG_OFFSET_RANGE                 15:10
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_BPG_OFFSET_WOFFSET                       0x0
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_BPG_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_BPG_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_BPG_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM4_BPG_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MIN_QP_SHIFT                     _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MIN_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MIN_QP_RANGE                     20:16
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MIN_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MIN_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MIN_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MIN_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MIN_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MAX_QP_SHIFT                     _MK_SHIFT_CONST(21)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MAX_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MAX_QP_RANGE                     25:21
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MAX_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MAX_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MAX_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MAX_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_MAX_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_BPG_OFFSET_SHIFT                 _MK_SHIFT_CONST(26)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_BPG_OFFSET_FIELD                 _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_BPG_OFFSET_RANGE                 31:26
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_BPG_OFFSET_WOFFSET                       0x0
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_BPG_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_BPG_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_BPG_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG2_0_DSC_RC_RANGE_PARAM5_BPG_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_RANGE_CFG3_0
#define DC_COM_DSC_RC_RANGE_CFG3_0                      _MK_ADDR_CONST(0x350)
#define DC_COM_DSC_RC_RANGE_CFG3_0_SECURE                       0x0
#define DC_COM_DSC_RC_RANGE_CFG3_0_SCR                  0
#define DC_COM_DSC_RC_RANGE_CFG3_0_WORD_COUNT                   0x1
#define DC_COM_DSC_RC_RANGE_CFG3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG3_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MIN_QP_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MIN_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MIN_QP_RANGE                     4:0
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MIN_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MIN_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MIN_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MIN_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MIN_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MAX_QP_SHIFT                     _MK_SHIFT_CONST(5)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MAX_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MAX_QP_RANGE                     9:5
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MAX_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MAX_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MAX_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MAX_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_MAX_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_BPG_OFFSET_SHIFT                 _MK_SHIFT_CONST(10)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_BPG_OFFSET_FIELD                 _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_BPG_OFFSET_RANGE                 15:10
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_BPG_OFFSET_WOFFSET                       0x0
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_BPG_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_BPG_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_BPG_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM6_BPG_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MIN_QP_SHIFT                     _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MIN_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MIN_QP_RANGE                     20:16
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MIN_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MIN_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MIN_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MIN_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MIN_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MAX_QP_SHIFT                     _MK_SHIFT_CONST(21)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MAX_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MAX_QP_RANGE                     25:21
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MAX_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MAX_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MAX_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MAX_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_MAX_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_BPG_OFFSET_SHIFT                 _MK_SHIFT_CONST(26)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_BPG_OFFSET_FIELD                 _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_BPG_OFFSET_RANGE                 31:26
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_BPG_OFFSET_WOFFSET                       0x0
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_BPG_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_BPG_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_BPG_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG3_0_DSC_RC_RANGE_PARAM7_BPG_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_RANGE_CFG4_0
#define DC_COM_DSC_RC_RANGE_CFG4_0                      _MK_ADDR_CONST(0x351)
#define DC_COM_DSC_RC_RANGE_CFG4_0_SECURE                       0x0
#define DC_COM_DSC_RC_RANGE_CFG4_0_SCR                  0
#define DC_COM_DSC_RC_RANGE_CFG4_0_WORD_COUNT                   0x1
#define DC_COM_DSC_RC_RANGE_CFG4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG4_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MIN_QP_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MIN_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MIN_QP_RANGE                     4:0
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MIN_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MIN_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MIN_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MIN_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MIN_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MAX_QP_SHIFT                     _MK_SHIFT_CONST(5)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MAX_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MAX_QP_RANGE                     9:5
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MAX_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MAX_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MAX_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MAX_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_MAX_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_BPG_OFFSET_SHIFT                 _MK_SHIFT_CONST(10)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_BPG_OFFSET_FIELD                 _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_BPG_OFFSET_RANGE                 15:10
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_BPG_OFFSET_WOFFSET                       0x0
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_BPG_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_BPG_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_BPG_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM8_BPG_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MIN_QP_SHIFT                     _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MIN_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MIN_QP_RANGE                     20:16
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MIN_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MIN_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MIN_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MIN_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MIN_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MAX_QP_SHIFT                     _MK_SHIFT_CONST(21)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MAX_QP_FIELD                     _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MAX_QP_RANGE                     25:21
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MAX_QP_WOFFSET                   0x0
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MAX_QP_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MAX_QP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MAX_QP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_MAX_QP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_BPG_OFFSET_SHIFT                 _MK_SHIFT_CONST(26)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_BPG_OFFSET_FIELD                 _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_BPG_OFFSET_RANGE                 31:26
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_BPG_OFFSET_WOFFSET                       0x0
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_BPG_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_BPG_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_BPG_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG4_0_DSC_RC_RANGE_PARAM9_BPG_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_RANGE_CFG5_0
#define DC_COM_DSC_RC_RANGE_CFG5_0                      _MK_ADDR_CONST(0x352)
#define DC_COM_DSC_RC_RANGE_CFG5_0_SECURE                       0x0
#define DC_COM_DSC_RC_RANGE_CFG5_0_SCR                  0
#define DC_COM_DSC_RC_RANGE_CFG5_0_WORD_COUNT                   0x1
#define DC_COM_DSC_RC_RANGE_CFG5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG5_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MIN_QP_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MIN_QP_FIELD                    _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MIN_QP_RANGE                    4:0
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MIN_QP_WOFFSET                  0x0
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MIN_QP_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MIN_QP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MIN_QP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MIN_QP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MAX_QP_SHIFT                    _MK_SHIFT_CONST(5)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MAX_QP_FIELD                    _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MAX_QP_RANGE                    9:5
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MAX_QP_WOFFSET                  0x0
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MAX_QP_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MAX_QP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MAX_QP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_MAX_QP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_BPG_OFFSET_SHIFT                        _MK_SHIFT_CONST(10)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_BPG_OFFSET_FIELD                        _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_BPG_OFFSET_RANGE                        15:10
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_BPG_OFFSET_WOFFSET                      0x0
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_BPG_OFFSET_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_BPG_OFFSET_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_BPG_OFFSET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM10_BPG_OFFSET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MIN_QP_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MIN_QP_FIELD                    _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MIN_QP_RANGE                    20:16
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MIN_QP_WOFFSET                  0x0
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MIN_QP_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MIN_QP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MIN_QP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MIN_QP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MAX_QP_SHIFT                    _MK_SHIFT_CONST(21)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MAX_QP_FIELD                    _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MAX_QP_RANGE                    25:21
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MAX_QP_WOFFSET                  0x0
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MAX_QP_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MAX_QP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MAX_QP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_MAX_QP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_BPG_OFFSET_SHIFT                        _MK_SHIFT_CONST(26)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_BPG_OFFSET_FIELD                        _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_BPG_OFFSET_RANGE                        31:26
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_BPG_OFFSET_WOFFSET                      0x0
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_BPG_OFFSET_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_BPG_OFFSET_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_BPG_OFFSET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG5_0_DSC_RC_RANGE_PARAM11_BPG_OFFSET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_RANGE_CFG6_0
#define DC_COM_DSC_RC_RANGE_CFG6_0                      _MK_ADDR_CONST(0x353)
#define DC_COM_DSC_RC_RANGE_CFG6_0_SECURE                       0x0
#define DC_COM_DSC_RC_RANGE_CFG6_0_SCR                  0
#define DC_COM_DSC_RC_RANGE_CFG6_0_WORD_COUNT                   0x1
#define DC_COM_DSC_RC_RANGE_CFG6_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG6_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG6_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MIN_QP_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MIN_QP_FIELD                    _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MIN_QP_RANGE                    4:0
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MIN_QP_WOFFSET                  0x0
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MIN_QP_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MIN_QP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MIN_QP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MIN_QP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MAX_QP_SHIFT                    _MK_SHIFT_CONST(5)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MAX_QP_FIELD                    _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MAX_QP_RANGE                    9:5
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MAX_QP_WOFFSET                  0x0
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MAX_QP_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MAX_QP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MAX_QP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_MAX_QP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_BPG_OFFSET_SHIFT                        _MK_SHIFT_CONST(10)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_BPG_OFFSET_FIELD                        _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_BPG_OFFSET_RANGE                        15:10
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_BPG_OFFSET_WOFFSET                      0x0
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_BPG_OFFSET_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_BPG_OFFSET_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_BPG_OFFSET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM12_BPG_OFFSET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MIN_QP_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MIN_QP_FIELD                    _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MIN_QP_RANGE                    20:16
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MIN_QP_WOFFSET                  0x0
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MIN_QP_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MIN_QP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MIN_QP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MIN_QP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MAX_QP_SHIFT                    _MK_SHIFT_CONST(21)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MAX_QP_FIELD                    _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MAX_QP_RANGE                    25:21
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MAX_QP_WOFFSET                  0x0
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MAX_QP_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MAX_QP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MAX_QP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_MAX_QP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_BPG_OFFSET_SHIFT                        _MK_SHIFT_CONST(26)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_BPG_OFFSET_FIELD                        _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_BPG_OFFSET_RANGE                        31:26
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_BPG_OFFSET_WOFFSET                      0x0
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_BPG_OFFSET_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_BPG_OFFSET_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_BPG_OFFSET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG6_0_DSC_RC_RANGE_PARAM13_BPG_OFFSET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_RC_RANGE_CFG7_0
#define DC_COM_DSC_RC_RANGE_CFG7_0                      _MK_ADDR_CONST(0x354)
#define DC_COM_DSC_RC_RANGE_CFG7_0_SECURE                       0x0
#define DC_COM_DSC_RC_RANGE_CFG7_0_SCR                  0
#define DC_COM_DSC_RC_RANGE_CFG7_0_WORD_COUNT                   0x1
#define DC_COM_DSC_RC_RANGE_CFG7_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG7_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_RANGE_CFG7_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG7_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG7_0_READ_MASK                    _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_RANGE_CFG7_0_WRITE_MASK                   _MK_MASK_CONST(0xffff)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MIN_QP_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MIN_QP_FIELD                    _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MIN_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MIN_QP_RANGE                    4:0
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MIN_QP_WOFFSET                  0x0
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MIN_QP_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MIN_QP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MIN_QP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MIN_QP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MAX_QP_SHIFT                    _MK_SHIFT_CONST(5)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MAX_QP_FIELD                    _MK_FIELD_CONST(0x1f, DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MAX_QP_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MAX_QP_RANGE                    9:5
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MAX_QP_WOFFSET                  0x0
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MAX_QP_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MAX_QP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MAX_QP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_MAX_QP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_BPG_OFFSET_SHIFT                        _MK_SHIFT_CONST(10)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_BPG_OFFSET_FIELD                        _MK_FIELD_CONST(0x3f, DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_BPG_OFFSET_SHIFT)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_BPG_OFFSET_RANGE                        15:10
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_BPG_OFFSET_WOFFSET                      0x0
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_BPG_OFFSET_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_BPG_OFFSET_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_BPG_OFFSET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_RC_RANGE_CFG7_0_DSC_RC_RANGE_PARAM14_BPG_OFFSET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_UNIT_SET_0
#define DC_COM_DSC_UNIT_SET_0                   _MK_ADDR_CONST(0x355)
#define DC_COM_DSC_UNIT_SET_0_SECURE                    0x0
#define DC_COM_DSC_UNIT_SET_0_SCR                       0
#define DC_COM_DSC_UNIT_SET_0_WORD_COUNT                        0x1
#define DC_COM_DSC_UNIT_SET_0_RESET_VAL                         _MK_MASK_CONST(0x35410)
#define DC_COM_DSC_UNIT_SET_0_RESET_MASK                        _MK_MASK_CONST(0x3fff7)
#define DC_COM_DSC_UNIT_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_READ_MASK                         _MK_MASK_CONST(0x3fff7)
#define DC_COM_DSC_UNIT_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x3fff7)
#define DC_COM_DSC_UNIT_SET_0_DSC_SLICE_NUM_MINUS1_IN_LINE_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_DSC_UNIT_SET_0_DSC_SLICE_NUM_MINUS1_IN_LINE_FIELD                        _MK_FIELD_CONST(0x3, DC_COM_DSC_UNIT_SET_0_DSC_SLICE_NUM_MINUS1_IN_LINE_SHIFT)
#define DC_COM_DSC_UNIT_SET_0_DSC_SLICE_NUM_MINUS1_IN_LINE_RANGE                        1:0
#define DC_COM_DSC_UNIT_SET_0_DSC_SLICE_NUM_MINUS1_IN_LINE_WOFFSET                      0x0
#define DC_COM_DSC_UNIT_SET_0_DSC_SLICE_NUM_MINUS1_IN_LINE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_DSC_SLICE_NUM_MINUS1_IN_LINE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define DC_COM_DSC_UNIT_SET_0_DSC_SLICE_NUM_MINUS1_IN_LINE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_DSC_SLICE_NUM_MINUS1_IN_LINE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_COM_DSC_UNIT_SET_0_DSC_LINEBUF_DEPTH_SHIFT                   _MK_SHIFT_CONST(2)
#define DC_COM_DSC_UNIT_SET_0_DSC_LINEBUF_DEPTH_FIELD                   _MK_FIELD_CONST(0x1, DC_COM_DSC_UNIT_SET_0_DSC_LINEBUF_DEPTH_SHIFT)
#define DC_COM_DSC_UNIT_SET_0_DSC_LINEBUF_DEPTH_RANGE                   2:2
#define DC_COM_DSC_UNIT_SET_0_DSC_LINEBUF_DEPTH_WOFFSET                 0x0
#define DC_COM_DSC_UNIT_SET_0_DSC_LINEBUF_DEPTH_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_DSC_LINEBUF_DEPTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_COM_DSC_UNIT_SET_0_DSC_LINEBUF_DEPTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_DSC_LINEBUF_DEPTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_COM_DSC_UNIT_SET_0_DSC_RC_SOLUTION_MODE_SHIFT                        _MK_SHIFT_CONST(4)
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_SOLUTION_MODE_FIELD                        _MK_FIELD_CONST(0x3, DC_COM_DSC_UNIT_SET_0_DSC_RC_SOLUTION_MODE_SHIFT)
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_SOLUTION_MODE_RANGE                        5:4
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_SOLUTION_MODE_WOFFSET                      0x0
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_SOLUTION_MODE_DEFAULT                      _MK_MASK_CONST(0x1)
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_SOLUTION_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_SOLUTION_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_SOLUTION_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_COM_DSC_UNIT_SET_0_DSC_CHECK_FLATNESS2_SHIFT                 _MK_SHIFT_CONST(6)
#define DC_COM_DSC_UNIT_SET_0_DSC_CHECK_FLATNESS2_FIELD                 _MK_FIELD_CONST(0x1, DC_COM_DSC_UNIT_SET_0_DSC_CHECK_FLATNESS2_SHIFT)
#define DC_COM_DSC_UNIT_SET_0_DSC_CHECK_FLATNESS2_RANGE                 6:6
#define DC_COM_DSC_UNIT_SET_0_DSC_CHECK_FLATNESS2_WOFFSET                       0x0
#define DC_COM_DSC_UNIT_SET_0_DSC_CHECK_FLATNESS2_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_DSC_CHECK_FLATNESS2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_COM_DSC_UNIT_SET_0_DSC_CHECK_FLATNESS2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_DSC_CHECK_FLATNESS2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_DSC_UNIT_SET_0_DSC_FLATNESS_FIX_EN_SHIFT                 _MK_SHIFT_CONST(7)
#define DC_COM_DSC_UNIT_SET_0_DSC_FLATNESS_FIX_EN_FIELD                 _MK_FIELD_CONST(0x1, DC_COM_DSC_UNIT_SET_0_DSC_FLATNESS_FIX_EN_SHIFT)
#define DC_COM_DSC_UNIT_SET_0_DSC_FLATNESS_FIX_EN_RANGE                 7:7
#define DC_COM_DSC_UNIT_SET_0_DSC_FLATNESS_FIX_EN_WOFFSET                       0x0
#define DC_COM_DSC_UNIT_SET_0_DSC_FLATNESS_FIX_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_DSC_FLATNESS_FIX_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_COM_DSC_UNIT_SET_0_DSC_FLATNESS_FIX_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_DSC_FLATNESS_FIX_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_DSC_UNIT_SET_0_DSC_RC_OVERFLOW_THRESH_SHIFT                      _MK_SHIFT_CONST(8)
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_OVERFLOW_THRESH_FIELD                      _MK_FIELD_CONST(0x3ff, DC_COM_DSC_UNIT_SET_0_DSC_RC_OVERFLOW_THRESH_SHIFT)
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_OVERFLOW_THRESH_RANGE                      17:8
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_OVERFLOW_THRESH_WOFFSET                    0x0
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_OVERFLOW_THRESH_DEFAULT                    _MK_MASK_CONST(0x354)
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_OVERFLOW_THRESH_DEFAULT_MASK                       _MK_MASK_CONST(0x3ff)
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_OVERFLOW_THRESH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_UNIT_SET_0_DSC_RC_OVERFLOW_THRESH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_STATUS0_0
#define DC_COM_DSC_STATUS0_0                    _MK_ADDR_CONST(0x358)
#define DC_COM_DSC_STATUS0_0_SECURE                     0x0
#define DC_COM_DSC_STATUS0_0_SCR                        0
#define DC_COM_DSC_STATUS0_0_WORD_COUNT                         0x1
#define DC_COM_DSC_STATUS0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_RESET_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_READ_MASK                  _MK_MASK_CONST(0xbfffffff)
#define DC_COM_DSC_STATUS0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_HINDEX_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_HINDEX_FIELD                    _MK_FIELD_CONST(0x3fff, DC_COM_DSC_STATUS0_0_DSC_STATUS_HINDEX_SHIFT)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_HINDEX_RANGE                    13:0
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_HINDEX_WOFFSET                  0x0
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_HINDEX_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_HINDEX_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_HINDEX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_HINDEX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_STATUS0_0_DSC_STATUS_SLICEID_SHIFT                   _MK_SHIFT_CONST(14)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_SLICEID_FIELD                   _MK_FIELD_CONST(0x3, DC_COM_DSC_STATUS0_0_DSC_STATUS_SLICEID_SHIFT)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_SLICEID_RANGE                   15:14
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_SLICEID_WOFFSET                 0x0
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_SLICEID_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_SLICEID_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_SLICEID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_SLICEID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_COM_DSC_STATUS0_0_DSC_STATUS_VINDEX_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_VINDEX_FIELD                    _MK_FIELD_CONST(0x3fff, DC_COM_DSC_STATUS0_0_DSC_STATUS_VINDEX_SHIFT)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_VINDEX_RANGE                    29:16
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_VINDEX_WOFFSET                  0x0
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_VINDEX_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_VINDEX_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_VINDEX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_VINDEX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_STATUS0_0_DSC_STATUS_BUSY_SHIFT                      _MK_SHIFT_CONST(31)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_BUSY_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_DSC_STATUS0_0_DSC_STATUS_BUSY_SHIFT)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_BUSY_RANGE                      31:31
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_BUSY_WOFFSET                    0x0
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS0_0_DSC_STATUS_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_DSC_STATUS1_0
#define DC_COM_DSC_STATUS1_0                    _MK_ADDR_CONST(0x359)
#define DC_COM_DSC_STATUS1_0_SECURE                     0x0
#define DC_COM_DSC_STATUS1_0_SCR                        0
#define DC_COM_DSC_STATUS1_0_WORD_COUNT                         0x1
#define DC_COM_DSC_STATUS1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_RESET_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_READ_MASK                  _MK_MASK_CONST(0xbfffffff)
#define DC_COM_DSC_STATUS1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_HINDEX_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_HINDEX_FIELD                    _MK_FIELD_CONST(0x3fff, DC_COM_DSC_STATUS1_0_DSC_STATUS_HINDEX_SHIFT)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_HINDEX_RANGE                    13:0
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_HINDEX_WOFFSET                  0x0
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_HINDEX_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_HINDEX_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_HINDEX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_HINDEX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_STATUS1_0_DSC_STATUS_SLICEID_SHIFT                   _MK_SHIFT_CONST(14)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_SLICEID_FIELD                   _MK_FIELD_CONST(0x3, DC_COM_DSC_STATUS1_0_DSC_STATUS_SLICEID_SHIFT)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_SLICEID_RANGE                   15:14
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_SLICEID_WOFFSET                 0x0
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_SLICEID_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_SLICEID_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_SLICEID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_SLICEID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_COM_DSC_STATUS1_0_DSC_STATUS_VINDEX_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_VINDEX_FIELD                    _MK_FIELD_CONST(0x3fff, DC_COM_DSC_STATUS1_0_DSC_STATUS_VINDEX_SHIFT)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_VINDEX_RANGE                    29:16
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_VINDEX_WOFFSET                  0x0
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_VINDEX_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_VINDEX_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_VINDEX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_VINDEX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_COM_DSC_STATUS1_0_DSC_STATUS_BUSY_SHIFT                      _MK_SHIFT_CONST(31)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_BUSY_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_DSC_STATUS1_0_DSC_STATUS_BUSY_SHIFT)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_BUSY_RANGE                      31:31
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_BUSY_WOFFSET                    0x0
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_DSC_STATUS1_0_DSC_STATUS_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0                    _MK_ADDR_CONST(0x35f)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_SECURE                     0x0
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_SCR                        0
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_WORD_COUNT                         0x1
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_VALUE_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_VALUE_SHIFT)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_VALUE_RANGE                        31:0
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_VALUE_WOFFSET                      0x0
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_POSTCOMP_HEAD_SPARE0_0
#define DC_COM_POSTCOMP_HEAD_SPARE0_0                   _MK_ADDR_CONST(0x360)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_SECURE                    0x0
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_SCR                       0
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_WORD_COUNT                        0x1
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_ECO_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_ECO_FIELD                 _MK_FIELD_CONST(0xffffffff, DC_COM_POSTCOMP_HEAD_SPARE0_0_ECO_SHIFT)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_ECO_RANGE                 31:0
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_ECO_WOFFSET                       0x0
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_ECO_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_ECO_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_ECO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_POSTCOMP_HEAD_SPARE0_0_ECO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_STATUS_0
#define DC_COM_RG_STATUS_0                      _MK_ADDR_CONST(0x362)
#define DC_COM_RG_STATUS_0_SECURE                       0x0
#define DC_COM_RG_STATUS_0_SCR                  0
#define DC_COM_RG_STATUS_0_WORD_COUNT                   0x1
#define DC_COM_RG_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0xfa55ffff)
#define DC_COM_RG_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_READ_MASK                    _MK_MASK_CONST(0xfb77ffff)
#define DC_COM_RG_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x42017)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_FORCE_EVEN_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_FORCE_EVEN_FIELD                 _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_RASTER_SYNC_FORCE_EVEN_SHIFT)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_FORCE_EVEN_RANGE                 0:0
#define DC_COM_RG_STATUS_0_RASTER_SYNC_FORCE_EVEN_WOFFSET                       0x0
#define DC_COM_RG_STATUS_0_RASTER_SYNC_FORCE_EVEN_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_FORCE_EVEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_FORCE_EVEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_FORCE_EVEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_FORCE_EVEN_DISABLE                       _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_FORCE_EVEN_ENABLE                        _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_RASTER_SYNC_EVEN_DETECT_FLIP_SHIFT                   _MK_SHIFT_CONST(1)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_EVEN_DETECT_FLIP_FIELD                   _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_RASTER_SYNC_EVEN_DETECT_FLIP_SHIFT)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_EVEN_DETECT_FLIP_RANGE                   1:1
#define DC_COM_RG_STATUS_0_RASTER_SYNC_EVEN_DETECT_FLIP_WOFFSET                 0x0
#define DC_COM_RG_STATUS_0_RASTER_SYNC_EVEN_DETECT_FLIP_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_EVEN_DETECT_FLIP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_EVEN_DETECT_FLIP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_EVEN_DETECT_FLIP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_EVEN_DETECT_FLIP_DISABLE                 _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_RASTER_SYNC_EVEN_DETECT_FLIP_ENABLE                  _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_DP_VBLANK_SHIFT                      _MK_SHIFT_CONST(2)
#define DC_COM_RG_STATUS_0_DP_VBLANK_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_DP_VBLANK_SHIFT)
#define DC_COM_RG_STATUS_0_DP_VBLANK_RANGE                      2:2
#define DC_COM_RG_STATUS_0_DP_VBLANK_WOFFSET                    0x0
#define DC_COM_RG_STATUS_0_DP_VBLANK_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_DP_VBLANK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_DP_VBLANK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_DP_VBLANK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_DP_VBLANK_SDI                        _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_DP_VBLANK_NORMAL                     _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_STALLED_SHIFT                        _MK_SHIFT_CONST(3)
#define DC_COM_RG_STATUS_0_STALLED_FIELD                        _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_STALLED_SHIFT)
#define DC_COM_RG_STATUS_0_STALLED_RANGE                        3:3
#define DC_COM_RG_STATUS_0_STALLED_WOFFSET                      0x0
#define DC_COM_RG_STATUS_0_STALLED_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_STALLED_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_STALLED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_STALLED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_STALLED_NO                   _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_STALLED_YES                  _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_FORCE_UNSTALL_SHIFT                  _MK_SHIFT_CONST(4)
#define DC_COM_RG_STATUS_0_FORCE_UNSTALL_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_FORCE_UNSTALL_SHIFT)
#define DC_COM_RG_STATUS_0_FORCE_UNSTALL_RANGE                  4:4
#define DC_COM_RG_STATUS_0_FORCE_UNSTALL_WOFFSET                        0x0
#define DC_COM_RG_STATUS_0_FORCE_UNSTALL_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_FORCE_UNSTALL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_FORCE_UNSTALL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_FORCE_UNSTALL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_FORCE_UNSTALL_DONE                   _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_FORCE_UNSTALL_PENDING                        _MK_ENUM_CONST(1)
#define DC_COM_RG_STATUS_0_FORCE_UNSTALL_TRIGGER                        _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_EXTERNAL_UNSTALL_EVENT_CNT_SHIFT                     _MK_SHIFT_CONST(5)
#define DC_COM_RG_STATUS_0_EXTERNAL_UNSTALL_EVENT_CNT_FIELD                     _MK_FIELD_CONST(0xf, DC_COM_RG_STATUS_0_EXTERNAL_UNSTALL_EVENT_CNT_SHIFT)
#define DC_COM_RG_STATUS_0_EXTERNAL_UNSTALL_EVENT_CNT_RANGE                     8:5
#define DC_COM_RG_STATUS_0_EXTERNAL_UNSTALL_EVENT_CNT_WOFFSET                   0x0
#define DC_COM_RG_STATUS_0_EXTERNAL_UNSTALL_EVENT_CNT_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_EXTERNAL_UNSTALL_EVENT_CNT_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define DC_COM_RG_STATUS_0_EXTERNAL_UNSTALL_EVENT_CNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_EXTERNAL_UNSTALL_EVENT_CNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_COM_RG_STATUS_0_RG_UNSTALL_CNT_SHIFT                 _MK_SHIFT_CONST(9)
#define DC_COM_RG_STATUS_0_RG_UNSTALL_CNT_FIELD                 _MK_FIELD_CONST(0xf, DC_COM_RG_STATUS_0_RG_UNSTALL_CNT_SHIFT)
#define DC_COM_RG_STATUS_0_RG_UNSTALL_CNT_RANGE                 12:9
#define DC_COM_RG_STATUS_0_RG_UNSTALL_CNT_WOFFSET                       0x0
#define DC_COM_RG_STATUS_0_RG_UNSTALL_CNT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_RG_UNSTALL_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define DC_COM_RG_STATUS_0_RG_UNSTALL_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_RG_UNSTALL_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_SHIFT                        _MK_SHIFT_CONST(13)
#define DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_FIELD                        _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_SHIFT)
#define DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_RANGE                        13:13
#define DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_WOFFSET                      0x0
#define DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_DONE                 _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_PENDING                      _MK_ENUM_CONST(1)
#define DC_COM_RG_STATUS_0_UNSTALL_CNT_RST_TRIGGER                      _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_SHIFT                        _MK_SHIFT_CONST(14)
#define DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_FIELD                        _MK_FIELD_CONST(0x3, DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_SHIFT)
#define DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_RANGE                        15:14
#define DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_WOFFSET                      0x0
#define DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_SLEEP                        _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_SNOOZE                       _MK_ENUM_CONST(1)
#define DC_COM_RG_STATUS_0_ACT_HEAD_OPMODE_AWAKE                        _MK_ENUM_CONST(2)

#define DC_COM_RG_STATUS_0_HSYNC_SHIFT                  _MK_SHIFT_CONST(16)
#define DC_COM_RG_STATUS_0_HSYNC_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_HSYNC_SHIFT)
#define DC_COM_RG_STATUS_0_HSYNC_RANGE                  16:16
#define DC_COM_RG_STATUS_0_HSYNC_WOFFSET                        0x0
#define DC_COM_RG_STATUS_0_HSYNC_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_HSYNC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_HSYNC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_HSYNC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_HSYNC_INACTIVE                       _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_HSYNC_ACTIVE                 _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_HBLNK_SHIFT                  _MK_SHIFT_CONST(17)
#define DC_COM_RG_STATUS_0_HBLNK_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_HBLNK_SHIFT)
#define DC_COM_RG_STATUS_0_HBLNK_RANGE                  17:17
#define DC_COM_RG_STATUS_0_HBLNK_WOFFSET                        0x0
#define DC_COM_RG_STATUS_0_HBLNK_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_HBLNK_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_HBLNK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_HBLNK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_HBLNK_INACTIVE                       _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_HBLNK_ACTIVE                 _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_CRASHLOCK_FIX_SHIFT                  _MK_SHIFT_CONST(18)
#define DC_COM_RG_STATUS_0_CRASHLOCK_FIX_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_CRASHLOCK_FIX_SHIFT)
#define DC_COM_RG_STATUS_0_CRASHLOCK_FIX_RANGE                  18:18
#define DC_COM_RG_STATUS_0_CRASHLOCK_FIX_WOFFSET                        0x0
#define DC_COM_RG_STATUS_0_CRASHLOCK_FIX_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_CRASHLOCK_FIX_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_CRASHLOCK_FIX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_CRASHLOCK_FIX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_CRASHLOCK_FIX_ACTIVE                 _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_CRASHLOCK_FIX_LEGACY                 _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_VSYNC_SHIFT                  _MK_SHIFT_CONST(20)
#define DC_COM_RG_STATUS_0_VSYNC_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_VSYNC_SHIFT)
#define DC_COM_RG_STATUS_0_VSYNC_RANGE                  20:20
#define DC_COM_RG_STATUS_0_VSYNC_WOFFSET                        0x0
#define DC_COM_RG_STATUS_0_VSYNC_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VSYNC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_VSYNC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VSYNC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VSYNC_INACTIVE                       _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_VSYNC_ACTIVE                 _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_VBLNK_SHIFT                  _MK_SHIFT_CONST(21)
#define DC_COM_RG_STATUS_0_VBLNK_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_VBLNK_SHIFT)
#define DC_COM_RG_STATUS_0_VBLNK_RANGE                  21:21
#define DC_COM_RG_STATUS_0_VBLNK_WOFFSET                        0x0
#define DC_COM_RG_STATUS_0_VBLNK_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VBLNK_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VBLNK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VBLNK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VBLNK_INACTIVE                       _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_VBLNK_ACTIVE                 _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_FID_SHIFT                    _MK_SHIFT_CONST(22)
#define DC_COM_RG_STATUS_0_FID_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_FID_SHIFT)
#define DC_COM_RG_STATUS_0_FID_RANGE                    22:22
#define DC_COM_RG_STATUS_0_FID_WOFFSET                  0x0
#define DC_COM_RG_STATUS_0_FID_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_FID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_FID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_FID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_FID_FLD0                     _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_FID_FLD1                     _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_BLNK_SHIFT                   _MK_SHIFT_CONST(24)
#define DC_COM_RG_STATUS_0_BLNK_FIELD                   _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_BLNK_SHIFT)
#define DC_COM_RG_STATUS_0_BLNK_RANGE                   24:24
#define DC_COM_RG_STATUS_0_BLNK_WOFFSET                 0x0
#define DC_COM_RG_STATUS_0_BLNK_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_BLNK_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_BLNK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_BLNK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_BLNK_INACTIVE                        _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_BLNK_ACTIVE                  _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_VACT_SPACE_SHIFT                     _MK_SHIFT_CONST(25)
#define DC_COM_RG_STATUS_0_VACT_SPACE_FIELD                     _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_VACT_SPACE_SHIFT)
#define DC_COM_RG_STATUS_0_VACT_SPACE_RANGE                     25:25
#define DC_COM_RG_STATUS_0_VACT_SPACE_WOFFSET                   0x0
#define DC_COM_RG_STATUS_0_VACT_SPACE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VACT_SPACE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_VACT_SPACE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VACT_SPACE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VACT_SPACE_INACTIVE                  _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_VACT_SPACE_ACTIVE                    _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_STEREO_SHIFT                 _MK_SHIFT_CONST(27)
#define DC_COM_RG_STATUS_0_STEREO_FIELD                 _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_STEREO_SHIFT)
#define DC_COM_RG_STATUS_0_STEREO_RANGE                 27:27
#define DC_COM_RG_STATUS_0_STEREO_WOFFSET                       0x0
#define DC_COM_RG_STATUS_0_STEREO_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_STEREO_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_STEREO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_STEREO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_STEREO_RIGHT                 _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_STEREO_LEFT                  _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_VIEWPORT_SHIFT                       _MK_SHIFT_CONST(28)
#define DC_COM_RG_STATUS_0_VIEWPORT_FIELD                       _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_VIEWPORT_SHIFT)
#define DC_COM_RG_STATUS_0_VIEWPORT_RANGE                       28:28
#define DC_COM_RG_STATUS_0_VIEWPORT_WOFFSET                     0x0
#define DC_COM_RG_STATUS_0_VIEWPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VIEWPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_VIEWPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VIEWPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_VIEWPORT_INACTIVE                    _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_VIEWPORT_ACTIVE                      _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_BORDER_SHIFT                 _MK_SHIFT_CONST(29)
#define DC_COM_RG_STATUS_0_BORDER_FIELD                 _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_BORDER_SHIFT)
#define DC_COM_RG_STATUS_0_BORDER_RANGE                 29:29
#define DC_COM_RG_STATUS_0_BORDER_WOFFSET                       0x0
#define DC_COM_RG_STATUS_0_BORDER_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_BORDER_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_BORDER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_BORDER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_BORDER_INACTIVE                      _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_BORDER_ACTIVE                        _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_LOCKED_SHIFT                 _MK_SHIFT_CONST(30)
#define DC_COM_RG_STATUS_0_LOCKED_FIELD                 _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_LOCKED_SHIFT)
#define DC_COM_RG_STATUS_0_LOCKED_RANGE                 30:30
#define DC_COM_RG_STATUS_0_LOCKED_WOFFSET                       0x0
#define DC_COM_RG_STATUS_0_LOCKED_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_LOCKED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_LOCKED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_LOCKED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_LOCKED_FALSE                 _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_LOCKED_TRUE                  _MK_ENUM_CONST(1)

#define DC_COM_RG_STATUS_0_FLIPLOCKED_SHIFT                     _MK_SHIFT_CONST(31)
#define DC_COM_RG_STATUS_0_FLIPLOCKED_FIELD                     _MK_FIELD_CONST(0x1, DC_COM_RG_STATUS_0_FLIPLOCKED_SHIFT)
#define DC_COM_RG_STATUS_0_FLIPLOCKED_RANGE                     31:31
#define DC_COM_RG_STATUS_0_FLIPLOCKED_WOFFSET                   0x0
#define DC_COM_RG_STATUS_0_FLIPLOCKED_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_FLIPLOCKED_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_COM_RG_STATUS_0_FLIPLOCKED_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_FLIPLOCKED_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_STATUS_0_FLIPLOCKED_FALSE                     _MK_ENUM_CONST(0)
#define DC_COM_RG_STATUS_0_FLIPLOCKED_TRUE                      _MK_ENUM_CONST(1)


// Register DC_COM_RG_IN_LOADV_COUNTER_0
#define DC_COM_RG_IN_LOADV_COUNTER_0                    _MK_ADDR_CONST(0x363)
#define DC_COM_RG_IN_LOADV_COUNTER_0_SECURE                     0x0
#define DC_COM_RG_IN_LOADV_COUNTER_0_SCR                        0
#define DC_COM_RG_IN_LOADV_COUNTER_0_WORD_COUNT                         0x1
#define DC_COM_RG_IN_LOADV_COUNTER_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_IN_LOADV_COUNTER_0_RESET_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_IN_LOADV_COUNTER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_IN_LOADV_COUNTER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_IN_LOADV_COUNTER_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_IN_LOADV_COUNTER_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_IN_LOADV_COUNTER_0_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_RG_IN_LOADV_COUNTER_0_VALUE_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_RG_IN_LOADV_COUNTER_0_VALUE_SHIFT)
#define DC_COM_RG_IN_LOADV_COUNTER_0_VALUE_RANGE                        31:0
#define DC_COM_RG_IN_LOADV_COUNTER_0_VALUE_WOFFSET                      0x0
#define DC_COM_RG_IN_LOADV_COUNTER_0_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_IN_LOADV_COUNTER_0_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_IN_LOADV_COUNTER_0_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_IN_LOADV_COUNTER_0_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_RG_DCLK_0
#define DC_COM_RG_DCLK_0                        _MK_ADDR_CONST(0x364)
#define DC_COM_RG_DCLK_0_SECURE                         0x0
#define DC_COM_RG_DCLK_0_SCR                    0
#define DC_COM_RG_DCLK_0_WORD_COUNT                     0x1
#define DC_COM_RG_DCLK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_DCLK_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_DCLK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_DCLK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_DCLK_0_READ_MASK                      _MK_MASK_CONST(0xfffffff)
#define DC_COM_RG_DCLK_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_DCLK_0_CNT_PER_FRM_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_DCLK_0_CNT_PER_FRM_FIELD                      _MK_FIELD_CONST(0xfffffff, DC_COM_RG_DCLK_0_CNT_PER_FRM_SHIFT)
#define DC_COM_RG_DCLK_0_CNT_PER_FRM_RANGE                      27:0
#define DC_COM_RG_DCLK_0_CNT_PER_FRM_WOFFSET                    0x0
#define DC_COM_RG_DCLK_0_CNT_PER_FRM_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_DCLK_0_CNT_PER_FRM_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_DCLK_0_CNT_PER_FRM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_DCLK_0_CNT_PER_FRM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_UNDERFLOW_0
#define DC_COM_RG_UNDERFLOW_0                   _MK_ADDR_CONST(0x365)
#define DC_COM_RG_UNDERFLOW_0_SECURE                    0x0
#define DC_COM_RG_UNDERFLOW_0_SCR                       0
#define DC_COM_RG_UNDERFLOW_0_WORD_COUNT                        0x1
#define DC_COM_RG_UNDERFLOW_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_RESET_MASK                        _MK_MASK_CONST(0x1ff0111)
#define DC_COM_RG_UNDERFLOW_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_READ_MASK                         _MK_MASK_CONST(0x1ff0111)
#define DC_COM_RG_UNDERFLOW_0_WRITE_MASK                        _MK_MASK_CONST(0x1000111)
#define DC_COM_RG_UNDERFLOW_0_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_UNDERFLOW_0_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_UNDERFLOW_0_ENABLE_SHIFT)
#define DC_COM_RG_UNDERFLOW_0_ENABLE_RANGE                      0:0
#define DC_COM_RG_UNDERFLOW_0_ENABLE_WOFFSET                    0x0
#define DC_COM_RG_UNDERFLOW_0_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_UNDERFLOW_0_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define DC_COM_RG_UNDERFLOW_0_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_SHIFT                 _MK_SHIFT_CONST(4)
#define DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_FIELD                 _MK_FIELD_CONST(0x1, DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_SHIFT)
#define DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_RANGE                 4:4
#define DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_WOFFSET                       0x0
#define DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_NO                    _MK_ENUM_CONST(0)
#define DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_YES                   _MK_ENUM_CONST(1)
#define DC_COM_RG_UNDERFLOW_0_UNDERFLOWED_CLR                   _MK_ENUM_CONST(1)

#define DC_COM_RG_UNDERFLOW_0_MODE_SHIFT                        _MK_SHIFT_CONST(8)
#define DC_COM_RG_UNDERFLOW_0_MODE_FIELD                        _MK_FIELD_CONST(0x1, DC_COM_RG_UNDERFLOW_0_MODE_SHIFT)
#define DC_COM_RG_UNDERFLOW_0_MODE_RANGE                        8:8
#define DC_COM_RG_UNDERFLOW_0_MODE_WOFFSET                      0x0
#define DC_COM_RG_UNDERFLOW_0_MODE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_COM_RG_UNDERFLOW_0_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_MODE_REPEAT                       _MK_ENUM_CONST(0)
#define DC_COM_RG_UNDERFLOW_0_MODE_RED                  _MK_ENUM_CONST(1)

#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_FIELD                      _MK_FIELD_CONST(0xff, DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_SHIFT)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RANGE                      23:16
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_WOFFSET                    0x0
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_SHIFT                  _MK_SHIFT_CONST(24)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_SHIFT)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_RANGE                  24:24
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_WOFFSET                        0x0
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_RST_DONE                       _MK_ENUM_CONST(0)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_RST_PENDING                    _MK_ENUM_CONST(1)
#define DC_COM_RG_UNDERFLOW_0_FRAMES_UFLOWED_RST_RST_TRIGGER                    _MK_ENUM_CONST(1)


// Register DC_COM_RG_DPCA_0
#define DC_COM_RG_DPCA_0                        _MK_ADDR_CONST(0x366)
#define DC_COM_RG_DPCA_0_SECURE                         0x0
#define DC_COM_RG_DPCA_0_SCR                    0
#define DC_COM_RG_DPCA_0_WORD_COUNT                     0x1
#define DC_COM_RG_DPCA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCA_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCA_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_DPCA_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCA_0_LINE_CNT_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_COM_RG_DPCA_0_LINE_CNT_FIELD                 _MK_FIELD_CONST(0xffff, DC_COM_RG_DPCA_0_LINE_CNT_SHIFT)
#define DC_COM_RG_DPCA_0_LINE_CNT_RANGE                 15:0
#define DC_COM_RG_DPCA_0_LINE_CNT_WOFFSET                       0x0
#define DC_COM_RG_DPCA_0_LINE_CNT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCA_0_LINE_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCA_0_LINE_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCA_0_LINE_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_RG_DPCA_0_FRM_CNT_SHIFT                  _MK_SHIFT_CONST(16)
#define DC_COM_RG_DPCA_0_FRM_CNT_FIELD                  _MK_FIELD_CONST(0xffff, DC_COM_RG_DPCA_0_FRM_CNT_SHIFT)
#define DC_COM_RG_DPCA_0_FRM_CNT_RANGE                  31:16
#define DC_COM_RG_DPCA_0_FRM_CNT_WOFFSET                        0x0
#define DC_COM_RG_DPCA_0_FRM_CNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCA_0_FRM_CNT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCA_0_FRM_CNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCA_0_FRM_CNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_COM_RG_DPCB_0
#define DC_COM_RG_DPCB_0                        _MK_ADDR_CONST(0x367)
#define DC_COM_RG_DPCB_0_SECURE                         0x0
#define DC_COM_RG_DPCB_0_SCR                    0
#define DC_COM_RG_DPCB_0_WORD_COUNT                     0x1
#define DC_COM_RG_DPCB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCB_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCB_0_READ_MASK                      _MK_MASK_CONST(0xffff)
#define DC_COM_RG_DPCB_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCB_0_PIXEL_CNT_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_RG_DPCB_0_PIXEL_CNT_FIELD                        _MK_FIELD_CONST(0xffff, DC_COM_RG_DPCB_0_PIXEL_CNT_SHIFT)
#define DC_COM_RG_DPCB_0_PIXEL_CNT_RANGE                        15:0
#define DC_COM_RG_DPCB_0_PIXEL_CNT_WOFFSET                      0x0
#define DC_COM_RG_DPCB_0_PIXEL_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCB_0_PIXEL_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCB_0_PIXEL_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_DPCB_0_PIXEL_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_RG_VPCA_0
#define DC_COM_RG_VPCA_0                        _MK_ADDR_CONST(0x368)
#define DC_COM_RG_VPCA_0_SECURE                         0x0
#define DC_COM_RG_VPCA_0_SCR                    0
#define DC_COM_RG_VPCA_0_WORD_COUNT                     0x1
#define DC_COM_RG_VPCA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCA_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCA_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_VPCA_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCA_0_LEFT_PIXEL_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_COM_RG_VPCA_0_LEFT_PIXEL_FIELD                       _MK_FIELD_CONST(0xffff, DC_COM_RG_VPCA_0_LEFT_PIXEL_SHIFT)
#define DC_COM_RG_VPCA_0_LEFT_PIXEL_RANGE                       15:0
#define DC_COM_RG_VPCA_0_LEFT_PIXEL_WOFFSET                     0x0
#define DC_COM_RG_VPCA_0_LEFT_PIXEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCA_0_LEFT_PIXEL_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCA_0_LEFT_PIXEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCA_0_LEFT_PIXEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_COM_RG_VPCA_0_TOP_LINE_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_VPCA_0_TOP_LINE_FIELD                 _MK_FIELD_CONST(0xffff, DC_COM_RG_VPCA_0_TOP_LINE_SHIFT)
#define DC_COM_RG_VPCA_0_TOP_LINE_RANGE                 31:16
#define DC_COM_RG_VPCA_0_TOP_LINE_WOFFSET                       0x0
#define DC_COM_RG_VPCA_0_TOP_LINE_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCA_0_TOP_LINE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCA_0_TOP_LINE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCA_0_TOP_LINE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_VPCB_0
#define DC_COM_RG_VPCB_0                        _MK_ADDR_CONST(0x369)
#define DC_COM_RG_VPCB_0_SECURE                         0x0
#define DC_COM_RG_VPCB_0_SCR                    0
#define DC_COM_RG_VPCB_0_WORD_COUNT                     0x1
#define DC_COM_RG_VPCB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCB_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCB_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_VPCB_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCB_0_RIGHT_PIXEL_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_VPCB_0_RIGHT_PIXEL_FIELD                      _MK_FIELD_CONST(0xffff, DC_COM_RG_VPCB_0_RIGHT_PIXEL_SHIFT)
#define DC_COM_RG_VPCB_0_RIGHT_PIXEL_RANGE                      15:0
#define DC_COM_RG_VPCB_0_RIGHT_PIXEL_WOFFSET                    0x0
#define DC_COM_RG_VPCB_0_RIGHT_PIXEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCB_0_RIGHT_PIXEL_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCB_0_RIGHT_PIXEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCB_0_RIGHT_PIXEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_VPCB_0_BOTTOM_LINE_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_RG_VPCB_0_BOTTOM_LINE_FIELD                      _MK_FIELD_CONST(0xffff, DC_COM_RG_VPCB_0_BOTTOM_LINE_SHIFT)
#define DC_COM_RG_VPCB_0_BOTTOM_LINE_RANGE                      31:16
#define DC_COM_RG_VPCB_0_BOTTOM_LINE_WOFFSET                    0x0
#define DC_COM_RG_VPCB_0_BOTTOM_LINE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCB_0_BOTTOM_LINE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCB_0_BOTTOM_LINE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_VPCB_0_BOTTOM_LINE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_SNAPSHOT_RASTER_0
#define DC_COM_RG_SNAPSHOT_RASTER_0                     _MK_ADDR_CONST(0x36a)
#define DC_COM_RG_SNAPSHOT_RASTER_0_SECURE                      0x0
#define DC_COM_RG_SNAPSHOT_RASTER_0_SCR                         0
#define DC_COM_RG_SNAPSHOT_RASTER_0_WORD_COUNT                  0x1
#define DC_COM_RG_SNAPSHOT_RASTER_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_SNAPSHOT_RASTER_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_SNAPSHOT_RASTER_0_WRITE_MASK                  _MK_MASK_CONST(0x80000000)
#define DC_COM_RG_SNAPSHOT_RASTER_0_LINE_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_LINE_FIELD                  _MK_FIELD_CONST(0xffff, DC_COM_RG_SNAPSHOT_RASTER_0_LINE_SHIFT)
#define DC_COM_RG_SNAPSHOT_RASTER_0_LINE_RANGE                  15:0
#define DC_COM_RG_SNAPSHOT_RASTER_0_LINE_WOFFSET                        0x0
#define DC_COM_RG_SNAPSHOT_RASTER_0_LINE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_LINE_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define DC_COM_RG_SNAPSHOT_RASTER_0_LINE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_LINE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_RG_SNAPSHOT_RASTER_0_PIXEL_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_SNAPSHOT_RASTER_0_PIXEL_FIELD                 _MK_FIELD_CONST(0x7fff, DC_COM_RG_SNAPSHOT_RASTER_0_PIXEL_SHIFT)
#define DC_COM_RG_SNAPSHOT_RASTER_0_PIXEL_RANGE                 30:16
#define DC_COM_RG_SNAPSHOT_RASTER_0_PIXEL_WOFFSET                       0x0
#define DC_COM_RG_SNAPSHOT_RASTER_0_PIXEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_PIXEL_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_SNAPSHOT_RASTER_0_PIXEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_PIXEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_SHIFT                        _MK_SHIFT_CONST(31)
#define DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_FIELD                        _MK_FIELD_CONST(0x1, DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_SHIFT)
#define DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_RANGE                        31:31
#define DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_WOFFSET                      0x0
#define DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_DONE                 _MK_ENUM_CONST(0)
#define DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_PENDING                      _MK_ENUM_CONST(1)
#define DC_COM_RG_SNAPSHOT_RASTER_0_UPDATE_TRIGGER_ALL_HEADS                    _MK_ENUM_CONST(1)


// Register DC_COM_RG_DEBUG_0
#define DC_COM_RG_DEBUG_0                       _MK_ADDR_CONST(0x36b)
#define DC_COM_RG_DEBUG_0_SECURE                        0x0
#define DC_COM_RG_DEBUG_0_SCR                   0
#define DC_COM_RG_DEBUG_0_WORD_COUNT                    0x1
#define DC_COM_RG_DEBUG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_DEBUG_0_RESET_MASK                    _MK_MASK_CONST(0x3f)
#define DC_COM_RG_DEBUG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_DEBUG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_DEBUG_0_READ_MASK                     _MK_MASK_CONST(0x3f)
#define DC_COM_RG_DEBUG_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_DEBUG_0_PIXEL_RED2_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_DEBUG_0_PIXEL_RED2_FIELD                      _MK_FIELD_CONST(0x3, DC_COM_RG_DEBUG_0_PIXEL_RED2_SHIFT)
#define DC_COM_RG_DEBUG_0_PIXEL_RED2_RANGE                      1:0
#define DC_COM_RG_DEBUG_0_PIXEL_RED2_WOFFSET                    0x0
#define DC_COM_RG_DEBUG_0_PIXEL_RED2_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_DEBUG_0_PIXEL_RED2_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define DC_COM_RG_DEBUG_0_PIXEL_RED2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_DEBUG_0_PIXEL_RED2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_DEBUG_0_PIXEL_GRN2_SHIFT                      _MK_SHIFT_CONST(2)
#define DC_COM_RG_DEBUG_0_PIXEL_GRN2_FIELD                      _MK_FIELD_CONST(0x3, DC_COM_RG_DEBUG_0_PIXEL_GRN2_SHIFT)
#define DC_COM_RG_DEBUG_0_PIXEL_GRN2_RANGE                      3:2
#define DC_COM_RG_DEBUG_0_PIXEL_GRN2_WOFFSET                    0x0
#define DC_COM_RG_DEBUG_0_PIXEL_GRN2_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_DEBUG_0_PIXEL_GRN2_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define DC_COM_RG_DEBUG_0_PIXEL_GRN2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_DEBUG_0_PIXEL_GRN2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_DEBUG_0_PIXEL_BLU2_SHIFT                      _MK_SHIFT_CONST(4)
#define DC_COM_RG_DEBUG_0_PIXEL_BLU2_FIELD                      _MK_FIELD_CONST(0x3, DC_COM_RG_DEBUG_0_PIXEL_BLU2_SHIFT)
#define DC_COM_RG_DEBUG_0_PIXEL_BLU2_RANGE                      5:4
#define DC_COM_RG_DEBUG_0_PIXEL_BLU2_WOFFSET                    0x0
#define DC_COM_RG_DEBUG_0_PIXEL_BLU2_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_DEBUG_0_PIXEL_BLU2_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define DC_COM_RG_DEBUG_0_PIXEL_BLU2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_DEBUG_0_PIXEL_BLU2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_TEST_0
#define DC_COM_RG_TEST_0                        _MK_ADDR_CONST(0x36c)
#define DC_COM_RG_TEST_0_SECURE                         0x0
#define DC_COM_RG_TEST_0_SCR                    0
#define DC_COM_RG_TEST_0_WORD_COUNT                     0x1
#define DC_COM_RG_TEST_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_RESET_MASK                     _MK_MASK_CONST(0x1f00002)
#define DC_COM_RG_TEST_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_READ_MASK                      _MK_MASK_CONST(0x1f00002)
#define DC_COM_RG_TEST_0_WRITE_MASK                     _MK_MASK_CONST(0x1f00002)
#define DC_COM_RG_TEST_0_ENABLE_SHIFT                   _MK_SHIFT_CONST(1)
#define DC_COM_RG_TEST_0_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_COM_RG_TEST_0_ENABLE_SHIFT)
#define DC_COM_RG_TEST_0_ENABLE_RANGE                   1:1
#define DC_COM_RG_TEST_0_ENABLE_WOFFSET                 0x0
#define DC_COM_RG_TEST_0_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_COM_RG_TEST_0_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_COM_RG_TEST_0_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define DC_COM_RG_TEST_0_TPAT_SHIFT                     _MK_SHIFT_CONST(20)
#define DC_COM_RG_TEST_0_TPAT_FIELD                     _MK_FIELD_CONST(0x7, DC_COM_RG_TEST_0_TPAT_SHIFT)
#define DC_COM_RG_TEST_0_TPAT_RANGE                     22:20
#define DC_COM_RG_TEST_0_TPAT_WOFFSET                   0x0
#define DC_COM_RG_TEST_0_TPAT_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_TPAT_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define DC_COM_RG_TEST_0_TPAT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_TPAT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_TPAT_NOPTTN                    _MK_ENUM_CONST(0)
#define DC_COM_RG_TEST_0_TPAT_RAMP                      _MK_ENUM_CONST(1)
#define DC_COM_RG_TEST_0_TPAT_VERTICAL                  _MK_ENUM_CONST(2)
#define DC_COM_RG_TEST_0_TPAT_SQUARE                    _MK_ENUM_CONST(3)
#define DC_COM_RG_TEST_0_TPAT_LO                        _MK_ENUM_CONST(4)
#define DC_COM_RG_TEST_0_TPAT_ALLONE                    _MK_ENUM_CONST(5)

#define DC_COM_RG_TEST_0_BPCWTH_SHIFT                   _MK_SHIFT_CONST(23)
#define DC_COM_RG_TEST_0_BPCWTH_FIELD                   _MK_FIELD_CONST(0x3, DC_COM_RG_TEST_0_BPCWTH_SHIFT)
#define DC_COM_RG_TEST_0_BPCWTH_RANGE                   24:23
#define DC_COM_RG_TEST_0_BPCWTH_WOFFSET                 0x0
#define DC_COM_RG_TEST_0_BPCWTH_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_BPCWTH_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define DC_COM_RG_TEST_0_BPCWTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_BPCWTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_TEST_0_BPCWTH_BPC6                    _MK_ENUM_CONST(0)
#define DC_COM_RG_TEST_0_BPCWTH_BPC8                    _MK_ENUM_CONST(1)
#define DC_COM_RG_TEST_0_BPCWTH_BPC10                   _MK_ENUM_CONST(2)
#define DC_COM_RG_TEST_0_BPCWTH_BPC12                   _MK_ENUM_CONST(3)


// Register DC_COM_RG_UNDERFLOW_PIXEL_0
#define DC_COM_RG_UNDERFLOW_PIXEL_0                     _MK_ADDR_CONST(0x36d)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_SECURE                      0x0
#define DC_COM_RG_UNDERFLOW_PIXEL_0_SCR                         0
#define DC_COM_RG_UNDERFLOW_PIXEL_0_WORD_COUNT                  0x1
#define DC_COM_RG_UNDERFLOW_PIXEL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_CNT_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_CNT_FIELD                   _MK_FIELD_CONST(0xffffffff, DC_COM_RG_UNDERFLOW_PIXEL_0_CNT_SHIFT)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_CNT_RANGE                   31:0
#define DC_COM_RG_UNDERFLOW_PIXEL_0_CNT_WOFFSET                 0x0
#define DC_COM_RG_UNDERFLOW_PIXEL_0_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_UNDERFLOW_PIXEL_0_CNT_CLR                     _MK_ENUM_CONST(0)


// Register DC_COM_RG_SPARE0_0
#define DC_COM_RG_SPARE0_0                      _MK_ADDR_CONST(0x36f)
#define DC_COM_RG_SPARE0_0_SECURE                       0x0
#define DC_COM_RG_SPARE0_0_SCR                  0
#define DC_COM_RG_SPARE0_0_WORD_COUNT                   0x1
#define DC_COM_RG_SPARE0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_SPARE0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_SPARE0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_SPARE0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_SPARE0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_SPARE0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_SPARE0_0_ECO_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_RG_SPARE0_0_ECO_FIELD                    _MK_FIELD_CONST(0xffffffff, DC_COM_RG_SPARE0_0_ECO_SHIFT)
#define DC_COM_RG_SPARE0_0_ECO_RANGE                    31:0
#define DC_COM_RG_SPARE0_0_ECO_WOFFSET                  0x0
#define DC_COM_RG_SPARE0_0_ECO_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_SPARE0_0_ECO_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_SPARE0_0_ECO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_SPARE0_0_ECO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_COM_CURSOR_LOADV_COUNTER_0
#define DC_COM_CURSOR_LOADV_COUNTER_0                   _MK_ADDR_CONST(0x370)
#define DC_COM_CURSOR_LOADV_COUNTER_0_SECURE                    0x0
#define DC_COM_CURSOR_LOADV_COUNTER_0_SCR                       0
#define DC_COM_CURSOR_LOADV_COUNTER_0_WORD_COUNT                        0x1
#define DC_COM_CURSOR_LOADV_COUNTER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_LOADV_COUNTER_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_LOADV_COUNTER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_LOADV_COUNTER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_LOADV_COUNTER_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_LOADV_COUNTER_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_LOADV_COUNTER_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_COM_CURSOR_LOADV_COUNTER_0_VALUE_FIELD                       _MK_FIELD_CONST(0xffffffff, DC_COM_CURSOR_LOADV_COUNTER_0_VALUE_SHIFT)
#define DC_COM_CURSOR_LOADV_COUNTER_0_VALUE_RANGE                       31:0
#define DC_COM_CURSOR_LOADV_COUNTER_0_VALUE_WOFFSET                     0x0
#define DC_COM_CURSOR_LOADV_COUNTER_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_LOADV_COUNTER_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_LOADV_COUNTER_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_LOADV_COUNTER_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_COM_CURSOR_SPARE0_0
#define DC_COM_CURSOR_SPARE0_0                  _MK_ADDR_CONST(0x371)
#define DC_COM_CURSOR_SPARE0_0_SECURE                   0x0
#define DC_COM_CURSOR_SPARE0_0_SCR                      0
#define DC_COM_CURSOR_SPARE0_0_WORD_COUNT                       0x1
#define DC_COM_CURSOR_SPARE0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_SPARE0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_SPARE0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_SPARE0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_SPARE0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_SPARE0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_SPARE0_0_ECO_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_CURSOR_SPARE0_0_ECO_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_CURSOR_SPARE0_0_ECO_SHIFT)
#define DC_COM_CURSOR_SPARE0_0_ECO_RANGE                        31:0
#define DC_COM_CURSOR_SPARE0_0_ECO_WOFFSET                      0x0
#define DC_COM_CURSOR_SPARE0_0_ECO_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_SPARE0_0_ECO_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_SPARE0_0_ECO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_SPARE0_0_ECO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_CURSOR_PIX_RCVD_0
#define DC_COM_CURSOR_PIX_RCVD_0                        _MK_ADDR_CONST(0x372)
#define DC_COM_CURSOR_PIX_RCVD_0_SECURE                         0x0
#define DC_COM_CURSOR_PIX_RCVD_0_SCR                    0
#define DC_COM_CURSOR_PIX_RCVD_0_WORD_COUNT                     0x1
#define DC_COM_CURSOR_PIX_RCVD_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_PIX_RCVD_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_PIX_RCVD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_PIX_RCVD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_PIX_RCVD_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_PIX_RCVD_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_PIX_RCVD_0_CNT_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_CURSOR_PIX_RCVD_0_CNT_FIELD                      _MK_FIELD_CONST(0xffffffff, DC_COM_CURSOR_PIX_RCVD_0_CNT_SHIFT)
#define DC_COM_CURSOR_PIX_RCVD_0_CNT_RANGE                      31:0
#define DC_COM_CURSOR_PIX_RCVD_0_CNT_WOFFSET                    0x0
#define DC_COM_CURSOR_PIX_RCVD_0_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_PIX_RCVD_0_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_PIX_RCVD_0_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_PIX_RCVD_0_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_CURSOR_DFLT_RGB_COLOR_0
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0                  _MK_ADDR_CONST(0x373)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_SECURE                   0x0
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_SCR                      0
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_WORD_COUNT                       0x1
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_B_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_B_FIELD                  _MK_FIELD_CONST(0xff, DC_COM_CURSOR_DFLT_RGB_COLOR_0_B_SHIFT)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_B_RANGE                  7:0
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_B_WOFFSET                        0x0
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_B_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_B_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_B_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_B_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_G_SHIFT                  _MK_SHIFT_CONST(8)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_G_FIELD                  _MK_FIELD_CONST(0xff, DC_COM_CURSOR_DFLT_RGB_COLOR_0_G_SHIFT)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_G_RANGE                  15:8
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_G_WOFFSET                        0x0
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_G_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_G_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_G_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_G_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_R_SHIFT                  _MK_SHIFT_CONST(16)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_R_FIELD                  _MK_FIELD_CONST(0xff, DC_COM_CURSOR_DFLT_RGB_COLOR_0_R_SHIFT)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_R_RANGE                  23:16
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_R_WOFFSET                        0x0
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_R_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_R_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_A_SHIFT                  _MK_SHIFT_CONST(24)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_A_FIELD                  _MK_FIELD_CONST(0xff, DC_COM_CURSOR_DFLT_RGB_COLOR_0_A_SHIFT)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_A_RANGE                  31:24
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_A_WOFFSET                        0x0
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_A_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_A_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_A_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DFLT_RGB_COLOR_0_A_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_COM_COMP_CURSOR_CGCTL_0
#define DC_COM_COMP_CURSOR_CGCTL_0                      _MK_ADDR_CONST(0x374)
#define DC_COM_COMP_CURSOR_CGCTL_0_SECURE                       0x0
#define DC_COM_COMP_CURSOR_CGCTL_0_SCR                  0
#define DC_COM_COMP_CURSOR_CGCTL_0_WORD_COUNT                   0x1
#define DC_COM_COMP_CURSOR_CGCTL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_CGCTL_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_CURSOR_CGCTL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_CGCTL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_CGCTL_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_CURSOR_CGCTL_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_CURSOR_CGCTL_0_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_COMP_CURSOR_CGCTL_0_VAL_FIELD                    _MK_FIELD_CONST(0xffffffff, DC_COM_COMP_CURSOR_CGCTL_0_VAL_SHIFT)
#define DC_COM_COMP_CURSOR_CGCTL_0_VAL_RANGE                    31:0
#define DC_COM_COMP_CURSOR_CGCTL_0_VAL_WOFFSET                  0x0
#define DC_COM_COMP_CURSOR_CGCTL_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_CGCTL_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_CURSOR_CGCTL_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_CGCTL_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_COM_CURSOR_DEBUG0_0
#define DC_COM_CURSOR_DEBUG0_0                  _MK_ADDR_CONST(0x375)
#define DC_COM_CURSOR_DEBUG0_0_SECURE                   0x0
#define DC_COM_CURSOR_DEBUG0_0_SCR                      0
#define DC_COM_CURSOR_DEBUG0_0_WORD_COUNT                       0x1
#define DC_COM_CURSOR_DEBUG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_READ_MASK                        _MK_MASK_CONST(0xf)
#define DC_COM_CURSOR_DEBUG0_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_STATE_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_CURSOR_DEBUG0_0_STATE_FIELD                      _MK_FIELD_CONST(0x3, DC_COM_CURSOR_DEBUG0_0_STATE_SHIFT)
#define DC_COM_CURSOR_DEBUG0_0_STATE_RANGE                      1:0
#define DC_COM_CURSOR_DEBUG0_0_STATE_WOFFSET                    0x0
#define DC_COM_CURSOR_DEBUG0_0_STATE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_STATE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_STATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_STATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_STATE_NOT_STARTED                        _MK_ENUM_CONST(0)
#define DC_COM_CURSOR_DEBUG0_0_STATE_IN_PROGRESS                        _MK_ENUM_CONST(1)
#define DC_COM_CURSOR_DEBUG0_0_STATE_COMPLETED                  _MK_ENUM_CONST(2)

#define DC_COM_CURSOR_DEBUG0_0_ABORTED_SHIFT                    _MK_SHIFT_CONST(2)
#define DC_COM_CURSOR_DEBUG0_0_ABORTED_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_CURSOR_DEBUG0_0_ABORTED_SHIFT)
#define DC_COM_CURSOR_DEBUG0_0_ABORTED_RANGE                    2:2
#define DC_COM_CURSOR_DEBUG0_0_ABORTED_WOFFSET                  0x0
#define DC_COM_CURSOR_DEBUG0_0_ABORTED_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_ABORTED_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_ABORTED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_ABORTED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_ABORTED_FALSE                    _MK_ENUM_CONST(0)
#define DC_COM_CURSOR_DEBUG0_0_ABORTED_TRUE                     _MK_ENUM_CONST(1)

#define DC_COM_CURSOR_DEBUG0_0_DUMMY_SHIFT                      _MK_SHIFT_CONST(3)
#define DC_COM_CURSOR_DEBUG0_0_DUMMY_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_CURSOR_DEBUG0_0_DUMMY_SHIFT)
#define DC_COM_CURSOR_DEBUG0_0_DUMMY_RANGE                      3:3
#define DC_COM_CURSOR_DEBUG0_0_DUMMY_WOFFSET                    0x0
#define DC_COM_CURSOR_DEBUG0_0_DUMMY_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_DUMMY_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_DUMMY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_DUMMY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG0_0_DUMMY_FALSE                      _MK_ENUM_CONST(0)
#define DC_COM_CURSOR_DEBUG0_0_DUMMY_TRUE                       _MK_ENUM_CONST(1)


// Register DC_COM_CURSOR_DEBUG1_0
#define DC_COM_CURSOR_DEBUG1_0                  _MK_ADDR_CONST(0x376)
#define DC_COM_CURSOR_DEBUG1_0_SECURE                   0x0
#define DC_COM_CURSOR_DEBUG1_0_SCR                      0
#define DC_COM_CURSOR_DEBUG1_0_WORD_COUNT                       0x1
#define DC_COM_CURSOR_DEBUG1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG1_0_RESET_MASK                       _MK_MASK_CONST(0x2fffffff)
#define DC_COM_CURSOR_DEBUG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG1_0_READ_MASK                        _MK_MASK_CONST(0x2fffffff)
#define DC_COM_CURSOR_DEBUG1_0_WRITE_MASK                       _MK_MASK_CONST(0x20000000)
#define DC_COM_CURSOR_DEBUG1_0_CLR_SHIFT                        _MK_SHIFT_CONST(29)
#define DC_COM_CURSOR_DEBUG1_0_CLR_FIELD                        _MK_FIELD_CONST(0x1, DC_COM_CURSOR_DEBUG1_0_CLR_SHIFT)
#define DC_COM_CURSOR_DEBUG1_0_CLR_RANGE                        29:29
#define DC_COM_CURSOR_DEBUG1_0_CLR_WOFFSET                      0x0
#define DC_COM_CURSOR_DEBUG1_0_CLR_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG1_0_CLR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_COM_CURSOR_DEBUG1_0_CLR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG1_0_CLR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG1_0_CLR_INIT_ENUM                    NOP
#define DC_COM_CURSOR_DEBUG1_0_CLR_NOP                  _MK_ENUM_CONST(0)
#define DC_COM_CURSOR_DEBUG1_0_CLR_CLEAR                        _MK_ENUM_CONST(1)

#define DC_COM_CURSOR_DEBUG1_0_INPUT_WAIT_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_COM_CURSOR_DEBUG1_0_INPUT_WAIT_COUNT_FIELD                   _MK_FIELD_CONST(0xfffffff, DC_COM_CURSOR_DEBUG1_0_INPUT_WAIT_COUNT_SHIFT)
#define DC_COM_CURSOR_DEBUG1_0_INPUT_WAIT_COUNT_RANGE                   27:0
#define DC_COM_CURSOR_DEBUG1_0_INPUT_WAIT_COUNT_WOFFSET                 0x0
#define DC_COM_CURSOR_DEBUG1_0_INPUT_WAIT_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG1_0_INPUT_WAIT_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xfffffff)
#define DC_COM_CURSOR_DEBUG1_0_INPUT_WAIT_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_CURSOR_DEBUG1_0_INPUT_WAIT_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register DC_COM_COMP_CURSOR_DEBUG0_0
#define DC_COM_COMP_CURSOR_DEBUG0_0                     _MK_ADDR_CONST(0x377)
#define DC_COM_COMP_CURSOR_DEBUG0_0_SECURE                      0x0
#define DC_COM_COMP_CURSOR_DEBUG0_0_SCR                         0
#define DC_COM_COMP_CURSOR_DEBUG0_0_WORD_COUNT                  0x1
#define DC_COM_COMP_CURSOR_DEBUG0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define DC_COM_COMP_CURSOR_DEBUG0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_FIELD                     _MK_FIELD_CONST(0x7, DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_SHIFT)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_RANGE                     2:0
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_WOFFSET                   0x0
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_IDLE                      _MK_ENUM_CONST(0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_PREIF_LOADV                       _MK_ENUM_CONST(1)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_LUT                       _MK_ENUM_CONST(2)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_BEG                       _MK_ENUM_CONST(3)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_PROC                      _MK_ENUM_CONST(4)
#define DC_COM_COMP_CURSOR_DEBUG0_0_FSM_STATE_END                       _MK_ENUM_CONST(5)

#define DC_COM_COMP_CURSOR_DEBUG0_0_PACKET_ERROR_SHIFT                  _MK_SHIFT_CONST(3)
#define DC_COM_COMP_CURSOR_DEBUG0_0_PACKET_ERROR_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_COMP_CURSOR_DEBUG0_0_PACKET_ERROR_SHIFT)
#define DC_COM_COMP_CURSOR_DEBUG0_0_PACKET_ERROR_RANGE                  3:3
#define DC_COM_COMP_CURSOR_DEBUG0_0_PACKET_ERROR_WOFFSET                        0x0
#define DC_COM_COMP_CURSOR_DEBUG0_0_PACKET_ERROR_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_PACKET_ERROR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_PACKET_ERROR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_PACKET_ERROR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_PACKET_ERROR_FALSE                  _MK_ENUM_CONST(0)
#define DC_COM_COMP_CURSOR_DEBUG0_0_PACKET_ERROR_TRUE                   _MK_ENUM_CONST(1)


// Register DC_COM_IHUB_CURS_ASR_CTLA_0
#define DC_COM_IHUB_CURS_ASR_CTLA_0                     _MK_ADDR_CONST(0x378)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SECURE                      0x0
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SCR                         0
#define DC_COM_IHUB_CURS_ASR_CTLA_0_WORD_COUNT                  0x1
#define DC_COM_IHUB_CURS_ASR_CTLA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_FIELD                       _MK_FIELD_CONST(0x3, DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_SHIFT)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_RANGE                       1:0
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_WOFFSET                     0x0
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_WATERMARK                   _MK_ENUM_CONST(0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_VBLANK                      _MK_ENUM_CONST(1)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_SUBMODE_WATERMARK_AND_VBLANK                        _MK_ENUM_CONST(2)

#define DC_COM_IHUB_CURS_ASR_CTLA_0_MODE_SHIFT                  _MK_SHIFT_CONST(2)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_MODE_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_IHUB_CURS_ASR_CTLA_0_MODE_SHIFT)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_MODE_RANGE                  2:2
#define DC_COM_IHUB_CURS_ASR_CTLA_0_MODE_WOFFSET                        0x0
#define DC_COM_IHUB_CURS_ASR_CTLA_0_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_MODE_IGNORE                 _MK_ENUM_CONST(0)
#define DC_COM_IHUB_CURS_ASR_CTLA_0_MODE_ENABLE                 _MK_ENUM_CONST(1)


// Register DC_COM_IHUB_CURS_ASR_CTLB_0
#define DC_COM_IHUB_CURS_ASR_CTLB_0                     _MK_ADDR_CONST(0x379)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_SECURE                      0x0
#define DC_COM_IHUB_CURS_ASR_CTLB_0_SCR                         0
#define DC_COM_IHUB_CURS_ASR_CTLB_0_WORD_COUNT                  0x1
#define DC_COM_IHUB_CURS_ASR_CTLB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_RESET_MASK                  _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_READ_MASK                   _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_WRITE_MASK                  _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_WATERMARK_LO_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_WATERMARK_LO_FIELD                  _MK_FIELD_CONST(0x1fffffff, DC_COM_IHUB_CURS_ASR_CTLB_0_WATERMARK_LO_SHIFT)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_WATERMARK_LO_RANGE                  28:0
#define DC_COM_IHUB_CURS_ASR_CTLB_0_WATERMARK_LO_WOFFSET                        0x0
#define DC_COM_IHUB_CURS_ASR_CTLB_0_WATERMARK_LO_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_WATERMARK_LO_DEFAULT_MASK                   _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_WATERMARK_LO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLB_0_WATERMARK_LO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_COM_IHUB_CURS_ASR_CTLC_0
#define DC_COM_IHUB_CURS_ASR_CTLC_0                     _MK_ADDR_CONST(0x37a)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_SECURE                      0x0
#define DC_COM_IHUB_CURS_ASR_CTLC_0_SCR                         0
#define DC_COM_IHUB_CURS_ASR_CTLC_0_WORD_COUNT                  0x1
#define DC_COM_IHUB_CURS_ASR_CTLC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_RESET_MASK                  _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_READ_MASK                   _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_WRITE_MASK                  _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_WATERMARK_HI_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_WATERMARK_HI_FIELD                  _MK_FIELD_CONST(0x1fffffff, DC_COM_IHUB_CURS_ASR_CTLC_0_WATERMARK_HI_SHIFT)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_WATERMARK_HI_RANGE                  28:0
#define DC_COM_IHUB_CURS_ASR_CTLC_0_WATERMARK_HI_WOFFSET                        0x0
#define DC_COM_IHUB_CURS_ASR_CTLC_0_WATERMARK_HI_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_WATERMARK_HI_DEFAULT_MASK                   _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_WATERMARK_HI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_ASR_CTLC_0_WATERMARK_HI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_COM_IHUB_CURS_OCC_0
#define DC_COM_IHUB_CURS_OCC_0                  _MK_ADDR_CONST(0x37e)
#define DC_COM_IHUB_CURS_OCC_0_SECURE                   0x0
#define DC_COM_IHUB_CURS_OCC_0_SCR                      0
#define DC_COM_IHUB_CURS_OCC_0_WORD_COUNT                       0x1
#define DC_COM_IHUB_CURS_OCC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_OCC_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_OCC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_OCC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_OCC_0_READ_MASK                        _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_OCC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_OCC_0_PIXELS_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_COM_IHUB_CURS_OCC_0_PIXELS_FIELD                     _MK_FIELD_CONST(0x1fffffff, DC_COM_IHUB_CURS_OCC_0_PIXELS_SHIFT)
#define DC_COM_IHUB_CURS_OCC_0_PIXELS_RANGE                     28:0
#define DC_COM_IHUB_CURS_OCC_0_PIXELS_WOFFSET                   0x0
#define DC_COM_IHUB_CURS_OCC_0_PIXELS_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_OCC_0_PIXELS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_OCC_0_PIXELS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_OCC_0_PIXELS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_COM_IHUB_CURS_MEMACC_0
#define DC_COM_IHUB_CURS_MEMACC_0                       _MK_ADDR_CONST(0x381)
#define DC_COM_IHUB_CURS_MEMACC_0_SECURE                        0x0
#define DC_COM_IHUB_CURS_MEMACC_0_SCR                   0
#define DC_COM_IHUB_CURS_MEMACC_0_WORD_COUNT                    0x1
#define DC_COM_IHUB_CURS_MEMACC_0_RESET_VAL                     _MK_MASK_CONST(0x20)
#define DC_COM_IHUB_CURS_MEMACC_0_RESET_MASK                    _MK_MASK_CONST(0xe0)
#define DC_COM_IHUB_CURS_MEMACC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_READ_MASK                     _MK_MASK_CONST(0xe1)
#define DC_COM_IHUB_CURS_MEMACC_0_WRITE_MASK                    _MK_MASK_CONST(0xe0)
#define DC_COM_IHUB_CURS_MEMACC_0_STATUS_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_IHUB_CURS_MEMACC_0_STATUS_FIELD                  _MK_FIELD_CONST(0x1, DC_COM_IHUB_CURS_MEMACC_0_STATUS_SHIFT)
#define DC_COM_IHUB_CURS_MEMACC_0_STATUS_RANGE                  0:0
#define DC_COM_IHUB_CURS_MEMACC_0_STATUS_WOFFSET                        0x0
#define DC_COM_IHUB_CURS_MEMACC_0_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_STATUS_STOPPED                        _MK_ENUM_CONST(0)
#define DC_COM_IHUB_CURS_MEMACC_0_STATUS_FETCHING                       _MK_ENUM_CONST(1)

#define DC_COM_IHUB_CURS_MEMACC_0_REQUEST_SHIFT                 _MK_SHIFT_CONST(5)
#define DC_COM_IHUB_CURS_MEMACC_0_REQUEST_FIELD                 _MK_FIELD_CONST(0x1, DC_COM_IHUB_CURS_MEMACC_0_REQUEST_SHIFT)
#define DC_COM_IHUB_CURS_MEMACC_0_REQUEST_RANGE                 5:5
#define DC_COM_IHUB_CURS_MEMACC_0_REQUEST_WOFFSET                       0x0
#define DC_COM_IHUB_CURS_MEMACC_0_REQUEST_DEFAULT                       _MK_MASK_CONST(0x1)
#define DC_COM_IHUB_CURS_MEMACC_0_REQUEST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_COM_IHUB_CURS_MEMACC_0_REQUEST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_REQUEST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_REQUEST_STOP                  _MK_ENUM_CONST(0)
#define DC_COM_IHUB_CURS_MEMACC_0_REQUEST_FETCH                 _MK_ENUM_CONST(1)

#define DC_COM_IHUB_CURS_MEMACC_0_CONTRACT_END_SHIFT                    _MK_SHIFT_CONST(6)
#define DC_COM_IHUB_CURS_MEMACC_0_CONTRACT_END_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_IHUB_CURS_MEMACC_0_CONTRACT_END_SHIFT)
#define DC_COM_IHUB_CURS_MEMACC_0_CONTRACT_END_RANGE                    6:6
#define DC_COM_IHUB_CURS_MEMACC_0_CONTRACT_END_WOFFSET                  0x0
#define DC_COM_IHUB_CURS_MEMACC_0_CONTRACT_END_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_CONTRACT_END_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_IHUB_CURS_MEMACC_0_CONTRACT_END_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_CONTRACT_END_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_CONTRACT_END_WAIT                     _MK_ENUM_CONST(0)
#define DC_COM_IHUB_CURS_MEMACC_0_CONTRACT_END_FORCE                    _MK_ENUM_CONST(1)

#define DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_SHIFT                     _MK_SHIFT_CONST(7)
#define DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_FIELD                     _MK_FIELD_CONST(0x1, DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_SHIFT)
#define DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_RANGE                     7:7
#define DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_WOFFSET                   0x0
#define DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_DONE                      _MK_ENUM_CONST(0)
#define DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_PENDING                   _MK_ENUM_CONST(1)
#define DC_COM_IHUB_CURS_MEMACC_0_SETTING_NEW_NEW_TRIGGER                       _MK_ENUM_CONST(1)


// Register DC_COM_IHUB_CURS_LATENCY_CTLA_0
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0                 _MK_ADDR_CONST(0x382)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SECURE                  0x0
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SCR                     0
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_WORD_COUNT                      0x1
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_WRITE_MASK                      _MK_MASK_CONST(0x7)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_FIELD                   _MK_FIELD_CONST(0x3, DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_SHIFT)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_RANGE                   1:0
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_WOFFSET                 0x0
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_WATERMARK                       _MK_ENUM_CONST(0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_VBLANK                  _MK_ENUM_CONST(1)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_SUBMODE_WATERMARK_AND_VBLANK                    _MK_ENUM_CONST(2)

#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_MODE_SHIFT                      _MK_SHIFT_CONST(2)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_MODE_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_IHUB_CURS_LATENCY_CTLA_0_MODE_SHIFT)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_MODE_RANGE                      2:2
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_MODE_WOFFSET                    0x0
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_MODE_IGNORE                     _MK_ENUM_CONST(0)
#define DC_COM_IHUB_CURS_LATENCY_CTLA_0_MODE_ENABLE                     _MK_ENUM_CONST(1)


// Register DC_COM_IHUB_CURS_LATENCY_CTLB_0
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0                 _MK_ADDR_CONST(0x383)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_SECURE                  0x0
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_SCR                     0
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_WORD_COUNT                      0x1
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_RESET_VAL                       _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_READ_MASK                       _MK_MASK_CONST(0x9fffffff)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_WATERMARK_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_WATERMARK_FIELD                 _MK_FIELD_CONST(0x1fffffff, DC_COM_IHUB_CURS_LATENCY_CTLB_0_WATERMARK_SHIFT)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_WATERMARK_RANGE                 28:0
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_WATERMARK_WOFFSET                       0x0
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_WATERMARK_DEFAULT                       _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_WATERMARK_DEFAULT_MASK                  _MK_MASK_CONST(0x1fffffff)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_WATERMARK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_WATERMARK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_STATUS_SHIFT                    _MK_SHIFT_CONST(31)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_STATUS_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_IHUB_CURS_LATENCY_CTLB_0_STATUS_SHIFT)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_STATUS_RANGE                    31:31
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_STATUS_WOFFSET                  0x0
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_STATUS_NOT_ABOVE_WATERMARK                      _MK_ENUM_CONST(0)
#define DC_COM_IHUB_CURS_LATENCY_CTLB_0_STATUS_ABOVE_WATERMARK                  _MK_ENUM_CONST(1)


// Register DC_COM_IHUB_CURS_REQ_SENT_0
#define DC_COM_IHUB_CURS_REQ_SENT_0                     _MK_ADDR_CONST(0x384)
#define DC_COM_IHUB_CURS_REQ_SENT_0_SECURE                      0x0
#define DC_COM_IHUB_CURS_REQ_SENT_0_SCR                         0
#define DC_COM_IHUB_CURS_REQ_SENT_0_WORD_COUNT                  0x1
#define DC_COM_IHUB_CURS_REQ_SENT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_SENT_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_SENT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_SENT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_SENT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_IHUB_CURS_REQ_SENT_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_SENT_0_CNT_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_COM_IHUB_CURS_REQ_SENT_0_CNT_FIELD                   _MK_FIELD_CONST(0xffffffff, DC_COM_IHUB_CURS_REQ_SENT_0_CNT_SHIFT)
#define DC_COM_IHUB_CURS_REQ_SENT_0_CNT_RANGE                   31:0
#define DC_COM_IHUB_CURS_REQ_SENT_0_CNT_WOFFSET                 0x0
#define DC_COM_IHUB_CURS_REQ_SENT_0_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_SENT_0_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_SENT_0_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_SENT_0_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register DC_COM_IHUB_CURS_RSP_RCVD_0
#define DC_COM_IHUB_CURS_RSP_RCVD_0                     _MK_ADDR_CONST(0x385)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_SECURE                      0x0
#define DC_COM_IHUB_CURS_RSP_RCVD_0_SCR                         0
#define DC_COM_IHUB_CURS_RSP_RCVD_0_WORD_COUNT                  0x1
#define DC_COM_IHUB_CURS_RSP_RCVD_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_CNT_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_CNT_FIELD                   _MK_FIELD_CONST(0xffffffff, DC_COM_IHUB_CURS_RSP_RCVD_0_CNT_SHIFT)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_CNT_RANGE                   31:0
#define DC_COM_IHUB_CURS_RSP_RCVD_0_CNT_WOFFSET                 0x0
#define DC_COM_IHUB_CURS_RSP_RCVD_0_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_RSP_RCVD_0_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register DC_COM_IHUB_CURS_REQ_0
#define DC_COM_IHUB_CURS_REQ_0                  _MK_ADDR_CONST(0x386)
#define DC_COM_IHUB_CURS_REQ_0_SECURE                   0x0
#define DC_COM_IHUB_CURS_REQ_0_SCR                      0
#define DC_COM_IHUB_CURS_REQ_0_WORD_COUNT                       0x1
#define DC_COM_IHUB_CURS_REQ_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define DC_COM_IHUB_CURS_REQ_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_0_LINE_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_COM_IHUB_CURS_REQ_0_LINE_FIELD                       _MK_FIELD_CONST(0xffff, DC_COM_IHUB_CURS_REQ_0_LINE_SHIFT)
#define DC_COM_IHUB_CURS_REQ_0_LINE_RANGE                       15:0
#define DC_COM_IHUB_CURS_REQ_0_LINE_WOFFSET                     0x0
#define DC_COM_IHUB_CURS_REQ_0_LINE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_0_LINE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_0_LINE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_IHUB_CURS_REQ_0_LINE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_COM_COMP_SPARE0_0
#define DC_COM_COMP_SPARE0_0                    _MK_ADDR_CONST(0x387)
#define DC_COM_COMP_SPARE0_0_SECURE                     0x0
#define DC_COM_COMP_SPARE0_0_SCR                        0
#define DC_COM_COMP_SPARE0_0_WORD_COUNT                         0x1
#define DC_COM_COMP_SPARE0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_COMP_SPARE0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_SPARE0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_COMP_SPARE0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_COMP_SPARE0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_SPARE0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_SPARE0_0_ECO_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_COMP_SPARE0_0_ECO_FIELD                  _MK_FIELD_CONST(0xffffffff, DC_COM_COMP_SPARE0_0_ECO_SHIFT)
#define DC_COM_COMP_SPARE0_0_ECO_RANGE                  31:0
#define DC_COM_COMP_SPARE0_0_ECO_WOFFSET                        0x0
#define DC_COM_COMP_SPARE0_0_ECO_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_COMP_SPARE0_0_ECO_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_COM_COMP_SPARE0_0_ECO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_COMP_SPARE0_0_ECO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_0
#define DC_COM_RG_REGION_CRC_0                  _MK_ADDR_CONST(0x3a2)
#define DC_COM_RG_REGION_CRC_0_SECURE                   0x0
#define DC_COM_RG_REGION_CRC_0_SCR                      0
#define DC_COM_RG_REGION_CRC_0_WORD_COUNT                       0x1
#define DC_COM_RG_REGION_CRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_RESET_MASK                       _MK_MASK_CONST(0x3ffff)
#define DC_COM_RG_REGION_CRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_READ_MASK                        _MK_MASK_CONST(0x3ffff)
#define DC_COM_RG_REGION_CRC_0_WRITE_MASK                       _MK_MASK_CONST(0x3ffff)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION0_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION0_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_ERROR_REGION0_SHIFT)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION0_RANGE                      0:0
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION0_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION0_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION0_NO                 _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION0_YES                        _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION0_CLR                        _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_ERROR_REGION1_SHIFT                      _MK_SHIFT_CONST(1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION1_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_ERROR_REGION1_SHIFT)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION1_RANGE                      1:1
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION1_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION1_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION1_NO                 _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION1_YES                        _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION1_CLR                        _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_ERROR_REGION2_SHIFT                      _MK_SHIFT_CONST(2)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION2_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_ERROR_REGION2_SHIFT)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION2_RANGE                      2:2
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION2_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION2_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION2_NO                 _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION2_YES                        _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION2_CLR                        _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_ERROR_REGION3_SHIFT                      _MK_SHIFT_CONST(3)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION3_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_ERROR_REGION3_SHIFT)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION3_RANGE                      3:3
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION3_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION3_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION3_NO                 _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION3_YES                        _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION3_CLR                        _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_ERROR_REGION4_SHIFT                      _MK_SHIFT_CONST(4)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION4_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_ERROR_REGION4_SHIFT)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION4_RANGE                      4:4
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION4_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION4_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION4_NO                 _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION4_YES                        _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION4_CLR                        _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_ERROR_REGION5_SHIFT                      _MK_SHIFT_CONST(5)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION5_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_ERROR_REGION5_SHIFT)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION5_RANGE                      5:5
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION5_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION5_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION5_NO                 _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION5_YES                        _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION5_CLR                        _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_ERROR_REGION6_SHIFT                      _MK_SHIFT_CONST(6)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION6_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_ERROR_REGION6_SHIFT)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION6_RANGE                      6:6
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION6_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION6_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION6_NO                 _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION6_YES                        _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION6_CLR                        _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_ERROR_REGION7_SHIFT                      _MK_SHIFT_CONST(7)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION7_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_ERROR_REGION7_SHIFT)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION7_RANGE                      7:7
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION7_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION7_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION7_NO                 _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION7_YES                        _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION7_CLR                        _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_ERROR_REGION8_SHIFT                      _MK_SHIFT_CONST(8)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION8_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_ERROR_REGION8_SHIFT)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION8_RANGE                      8:8
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION8_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION8_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION8_NO                 _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION8_YES                        _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_ERROR_REGION8_CLR                        _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_PENDING_REGION0_SHIFT                    _MK_SHIFT_CONST(9)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION0_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_PENDING_REGION0_SHIFT)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION0_RANGE                    9:9
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION0_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION0_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION0_NO                       _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION0_YES                      _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION0_CLR                      _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_PENDING_REGION1_SHIFT                    _MK_SHIFT_CONST(10)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION1_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_PENDING_REGION1_SHIFT)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION1_RANGE                    10:10
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION1_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION1_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION1_NO                       _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION1_YES                      _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION1_CLR                      _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_PENDING_REGION2_SHIFT                    _MK_SHIFT_CONST(11)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION2_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_PENDING_REGION2_SHIFT)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION2_RANGE                    11:11
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION2_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION2_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION2_NO                       _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION2_YES                      _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION2_CLR                      _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_PENDING_REGION3_SHIFT                    _MK_SHIFT_CONST(12)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION3_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_PENDING_REGION3_SHIFT)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION3_RANGE                    12:12
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION3_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION3_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION3_NO                       _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION3_YES                      _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION3_CLR                      _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_PENDING_REGION4_SHIFT                    _MK_SHIFT_CONST(13)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION4_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_PENDING_REGION4_SHIFT)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION4_RANGE                    13:13
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION4_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION4_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION4_NO                       _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION4_YES                      _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION4_CLR                      _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_PENDING_REGION5_SHIFT                    _MK_SHIFT_CONST(14)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION5_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_PENDING_REGION5_SHIFT)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION5_RANGE                    14:14
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION5_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION5_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION5_NO                       _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION5_YES                      _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION5_CLR                      _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_PENDING_REGION6_SHIFT                    _MK_SHIFT_CONST(15)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION6_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_PENDING_REGION6_SHIFT)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION6_RANGE                    15:15
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION6_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION6_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION6_NO                       _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION6_YES                      _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION6_CLR                      _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_PENDING_REGION7_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION7_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_PENDING_REGION7_SHIFT)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION7_RANGE                    16:16
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION7_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION7_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION7_NO                       _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION7_YES                      _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION7_CLR                      _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_0_PENDING_REGION8_SHIFT                    _MK_SHIFT_CONST(17)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION8_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_0_PENDING_REGION8_SHIFT)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION8_RANGE                    17:17
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION8_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION8_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION8_NO                       _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION8_YES                      _MK_ENUM_CONST(1)
#define DC_COM_RG_REGION_CRC_0_PENDING_REGION8_CLR                      _MK_ENUM_CONST(1)


// Register DC_COM_RG_REGION_CRC_CONTROL_0
#define DC_COM_RG_REGION_CRC_CONTROL_0                  _MK_ADDR_CONST(0x3a3)
#define DC_COM_RG_REGION_CRC_CONTROL_0_SECURE                   0x0
#define DC_COM_RG_REGION_CRC_CONTROL_0_SCR                      0
#define DC_COM_RG_REGION_CRC_CONTROL_0_WORD_COUNT                       0x1
#define DC_COM_RG_REGION_CRC_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x3ff)
#define DC_COM_RG_REGION_CRC_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x3ff)
#define DC_COM_RG_REGION_CRC_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x3ff)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION0_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION0_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_CONTROL_0_REGION0_SHIFT)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION0_RANGE                    0:0
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION0_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION0_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION0_DISABLE                  _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION0_ENABLE                   _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION1_SHIFT                    _MK_SHIFT_CONST(1)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION1_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_CONTROL_0_REGION1_SHIFT)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION1_RANGE                    1:1
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION1_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION1_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION1_DISABLE                  _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION1_ENABLE                   _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION2_SHIFT                    _MK_SHIFT_CONST(2)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION2_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_CONTROL_0_REGION2_SHIFT)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION2_RANGE                    2:2
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION2_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION2_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION2_DISABLE                  _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION2_ENABLE                   _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION3_SHIFT                    _MK_SHIFT_CONST(3)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION3_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_CONTROL_0_REGION3_SHIFT)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION3_RANGE                    3:3
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION3_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION3_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION3_DISABLE                  _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION3_ENABLE                   _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION4_SHIFT                    _MK_SHIFT_CONST(4)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION4_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_CONTROL_0_REGION4_SHIFT)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION4_RANGE                    4:4
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION4_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION4_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION4_DISABLE                  _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION4_ENABLE                   _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION5_SHIFT                    _MK_SHIFT_CONST(5)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION5_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_CONTROL_0_REGION5_SHIFT)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION5_RANGE                    5:5
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION5_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION5_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION5_DISABLE                  _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION5_ENABLE                   _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION6_SHIFT                    _MK_SHIFT_CONST(6)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION6_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_CONTROL_0_REGION6_SHIFT)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION6_RANGE                    6:6
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION6_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION6_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION6_DISABLE                  _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION6_ENABLE                   _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION7_SHIFT                    _MK_SHIFT_CONST(7)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION7_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_CONTROL_0_REGION7_SHIFT)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION7_RANGE                    7:7
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION7_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION7_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION7_DISABLE                  _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION7_ENABLE                   _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION8_SHIFT                    _MK_SHIFT_CONST(8)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION8_FIELD                    _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_CONTROL_0_REGION8_SHIFT)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION8_RANGE                    8:8
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION8_WOFFSET                  0x0
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION8_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION8_DISABLE                  _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_REGION8_ENABLE                   _MK_ENUM_CONST(1)

#define DC_COM_RG_REGION_CRC_CONTROL_0_CRC_READBACK_LOCATION_SHIFT                      _MK_SHIFT_CONST(9)
#define DC_COM_RG_REGION_CRC_CONTROL_0_CRC_READBACK_LOCATION_FIELD                      _MK_FIELD_CONST(0x1, DC_COM_RG_REGION_CRC_CONTROL_0_CRC_READBACK_LOCATION_SHIFT)
#define DC_COM_RG_REGION_CRC_CONTROL_0_CRC_READBACK_LOCATION_RANGE                      9:9
#define DC_COM_RG_REGION_CRC_CONTROL_0_CRC_READBACK_LOCATION_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_CONTROL_0_CRC_READBACK_LOCATION_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_CRC_READBACK_LOCATION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_COM_RG_REGION_CRC_CONTROL_0_CRC_READBACK_LOCATION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_CRC_READBACK_LOCATION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_CRC_READBACK_LOCATION_CRC_READBACK_HW                    _MK_ENUM_CONST(0)
#define DC_COM_RG_REGION_CRC_CONTROL_0_CRC_READBACK_LOCATION_CRC_READBACK_GOLDEN                        _MK_ENUM_CONST(1)


// Register DC_COM_RG_REGION_CRC_POINT_IN_0_0
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0                       _MK_ADDR_CONST(0x3a4)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_SECURE                        0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_SCR                   0
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_WORD_COUNT                    0x1
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_RESET_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_READ_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_WRITE_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_X_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_X_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_X_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_X_RANGE                      14:0
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_X_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_X_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_X_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_X_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_X_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_Y_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_Y_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_Y_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_Y_RANGE                      30:16
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_Y_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_Y_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_Y_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_Y_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_0_0_POINT_IN_Y_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_POINT_IN_1_0
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0                       _MK_ADDR_CONST(0x3a5)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_SECURE                        0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_SCR                   0
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_WORD_COUNT                    0x1
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_RESET_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_READ_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_WRITE_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_X_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_X_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_X_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_X_RANGE                      14:0
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_X_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_X_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_X_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_X_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_X_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_Y_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_Y_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_Y_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_Y_RANGE                      30:16
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_Y_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_Y_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_Y_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_Y_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_1_0_POINT_IN_Y_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_POINT_IN_2_0
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0                       _MK_ADDR_CONST(0x3a6)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_SECURE                        0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_SCR                   0
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_WORD_COUNT                    0x1
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_RESET_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_READ_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_WRITE_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_X_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_X_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_X_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_X_RANGE                      14:0
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_X_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_X_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_X_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_X_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_X_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_Y_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_Y_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_Y_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_Y_RANGE                      30:16
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_Y_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_Y_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_Y_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_Y_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_2_0_POINT_IN_Y_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_POINT_IN_3_0
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0                       _MK_ADDR_CONST(0x3a7)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_SECURE                        0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_SCR                   0
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_WORD_COUNT                    0x1
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_RESET_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_READ_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_WRITE_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_X_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_X_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_X_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_X_RANGE                      14:0
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_X_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_X_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_X_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_X_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_X_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_Y_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_Y_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_Y_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_Y_RANGE                      30:16
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_Y_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_Y_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_Y_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_Y_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_3_0_POINT_IN_Y_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_POINT_IN_4_0
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0                       _MK_ADDR_CONST(0x3a8)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_SECURE                        0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_SCR                   0
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_WORD_COUNT                    0x1
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_RESET_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_READ_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_WRITE_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_X_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_X_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_X_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_X_RANGE                      14:0
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_X_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_X_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_X_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_X_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_X_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_Y_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_Y_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_Y_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_Y_RANGE                      30:16
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_Y_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_Y_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_Y_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_Y_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_4_0_POINT_IN_Y_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_POINT_IN_5_0
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0                       _MK_ADDR_CONST(0x3a9)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_SECURE                        0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_SCR                   0
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_WORD_COUNT                    0x1
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_RESET_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_READ_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_WRITE_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_X_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_X_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_X_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_X_RANGE                      14:0
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_X_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_X_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_X_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_X_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_X_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_Y_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_Y_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_Y_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_Y_RANGE                      30:16
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_Y_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_Y_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_Y_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_Y_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_5_0_POINT_IN_Y_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_POINT_IN_6_0
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0                       _MK_ADDR_CONST(0x3aa)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_SECURE                        0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_SCR                   0
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_WORD_COUNT                    0x1
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_RESET_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_READ_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_WRITE_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_X_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_X_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_X_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_X_RANGE                      14:0
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_X_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_X_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_X_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_X_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_X_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_Y_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_Y_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_Y_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_Y_RANGE                      30:16
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_Y_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_Y_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_Y_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_Y_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_6_0_POINT_IN_Y_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_POINT_IN_7_0
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0                       _MK_ADDR_CONST(0x3ab)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_SECURE                        0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_SCR                   0
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_WORD_COUNT                    0x1
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_RESET_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_READ_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_WRITE_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_X_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_X_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_X_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_X_RANGE                      14:0
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_X_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_X_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_X_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_X_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_X_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_Y_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_Y_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_Y_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_Y_RANGE                      30:16
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_Y_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_Y_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_Y_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_Y_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_7_0_POINT_IN_Y_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_POINT_IN_8_0
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0                       _MK_ADDR_CONST(0x3ac)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_SECURE                        0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_SCR                   0
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_WORD_COUNT                    0x1
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_RESET_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_READ_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_WRITE_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_X_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_X_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_X_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_X_RANGE                      14:0
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_X_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_X_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_X_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_X_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_X_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_Y_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_Y_FIELD                      _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_Y_SHIFT)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_Y_RANGE                      30:16
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_Y_WOFFSET                    0x0
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_Y_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_Y_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_Y_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_POINT_IN_8_0_POINT_IN_Y_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_SIZE_0_0
#define DC_COM_RG_REGION_CRC_SIZE_0_0                   _MK_ADDR_CONST(0x3ad)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SECURE                    0x0
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SCR                       0
#define DC_COM_RG_REGION_CRC_SIZE_0_0_WORD_COUNT                        0x1
#define DC_COM_RG_REGION_CRC_SIZE_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_RESET_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_READ_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_WIDTH_FIELD                  _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_WIDTH_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_WIDTH_RANGE                  14:0
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_WIDTH_WOFFSET                        0x0
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_HEIGHT_FIELD                 _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_HEIGHT_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_HEIGHT_RANGE                 30:16
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_HEIGHT_WOFFSET                       0x0
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_0_0_SIZE_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_SIZE_1_0
#define DC_COM_RG_REGION_CRC_SIZE_1_0                   _MK_ADDR_CONST(0x3ae)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SECURE                    0x0
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SCR                       0
#define DC_COM_RG_REGION_CRC_SIZE_1_0_WORD_COUNT                        0x1
#define DC_COM_RG_REGION_CRC_SIZE_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_RESET_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_READ_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_WIDTH_FIELD                  _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_WIDTH_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_WIDTH_RANGE                  14:0
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_WIDTH_WOFFSET                        0x0
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_HEIGHT_FIELD                 _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_HEIGHT_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_HEIGHT_RANGE                 30:16
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_HEIGHT_WOFFSET                       0x0
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_1_0_SIZE_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_SIZE_2_0
#define DC_COM_RG_REGION_CRC_SIZE_2_0                   _MK_ADDR_CONST(0x3af)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SECURE                    0x0
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SCR                       0
#define DC_COM_RG_REGION_CRC_SIZE_2_0_WORD_COUNT                        0x1
#define DC_COM_RG_REGION_CRC_SIZE_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_RESET_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_READ_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_WIDTH_FIELD                  _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_WIDTH_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_WIDTH_RANGE                  14:0
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_WIDTH_WOFFSET                        0x0
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_HEIGHT_FIELD                 _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_HEIGHT_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_HEIGHT_RANGE                 30:16
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_HEIGHT_WOFFSET                       0x0
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_2_0_SIZE_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_SIZE_3_0
#define DC_COM_RG_REGION_CRC_SIZE_3_0                   _MK_ADDR_CONST(0x3b0)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SECURE                    0x0
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SCR                       0
#define DC_COM_RG_REGION_CRC_SIZE_3_0_WORD_COUNT                        0x1
#define DC_COM_RG_REGION_CRC_SIZE_3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_RESET_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_READ_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_WIDTH_FIELD                  _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_WIDTH_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_WIDTH_RANGE                  14:0
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_WIDTH_WOFFSET                        0x0
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_HEIGHT_FIELD                 _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_HEIGHT_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_HEIGHT_RANGE                 30:16
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_HEIGHT_WOFFSET                       0x0
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_3_0_SIZE_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_SIZE_4_0
#define DC_COM_RG_REGION_CRC_SIZE_4_0                   _MK_ADDR_CONST(0x3b1)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SECURE                    0x0
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SCR                       0
#define DC_COM_RG_REGION_CRC_SIZE_4_0_WORD_COUNT                        0x1
#define DC_COM_RG_REGION_CRC_SIZE_4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_RESET_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_READ_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_WIDTH_FIELD                  _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_WIDTH_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_WIDTH_RANGE                  14:0
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_WIDTH_WOFFSET                        0x0
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_HEIGHT_FIELD                 _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_HEIGHT_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_HEIGHT_RANGE                 30:16
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_HEIGHT_WOFFSET                       0x0
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_4_0_SIZE_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_SIZE_5_0
#define DC_COM_RG_REGION_CRC_SIZE_5_0                   _MK_ADDR_CONST(0x3b2)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SECURE                    0x0
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SCR                       0
#define DC_COM_RG_REGION_CRC_SIZE_5_0_WORD_COUNT                        0x1
#define DC_COM_RG_REGION_CRC_SIZE_5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_RESET_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_READ_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_WIDTH_FIELD                  _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_WIDTH_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_WIDTH_RANGE                  14:0
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_WIDTH_WOFFSET                        0x0
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_HEIGHT_FIELD                 _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_HEIGHT_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_HEIGHT_RANGE                 30:16
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_HEIGHT_WOFFSET                       0x0
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_5_0_SIZE_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_SIZE_6_0
#define DC_COM_RG_REGION_CRC_SIZE_6_0                   _MK_ADDR_CONST(0x3b3)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SECURE                    0x0
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SCR                       0
#define DC_COM_RG_REGION_CRC_SIZE_6_0_WORD_COUNT                        0x1
#define DC_COM_RG_REGION_CRC_SIZE_6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_RESET_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_READ_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_WIDTH_FIELD                  _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_WIDTH_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_WIDTH_RANGE                  14:0
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_WIDTH_WOFFSET                        0x0
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_HEIGHT_FIELD                 _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_HEIGHT_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_HEIGHT_RANGE                 30:16
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_HEIGHT_WOFFSET                       0x0
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_6_0_SIZE_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_SIZE_7_0
#define DC_COM_RG_REGION_CRC_SIZE_7_0                   _MK_ADDR_CONST(0x3b4)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SECURE                    0x0
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SCR                       0
#define DC_COM_RG_REGION_CRC_SIZE_7_0_WORD_COUNT                        0x1
#define DC_COM_RG_REGION_CRC_SIZE_7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_RESET_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_READ_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_WIDTH_FIELD                  _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_WIDTH_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_WIDTH_RANGE                  14:0
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_WIDTH_WOFFSET                        0x0
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_HEIGHT_FIELD                 _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_HEIGHT_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_HEIGHT_RANGE                 30:16
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_HEIGHT_WOFFSET                       0x0
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_7_0_SIZE_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_CRC_SIZE_8_0
#define DC_COM_RG_REGION_CRC_SIZE_8_0                   _MK_ADDR_CONST(0x3b5)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SECURE                    0x0
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SCR                       0
#define DC_COM_RG_REGION_CRC_SIZE_8_0_WORD_COUNT                        0x1
#define DC_COM_RG_REGION_CRC_SIZE_8_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_RESET_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_READ_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_WIDTH_FIELD                  _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_WIDTH_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_WIDTH_RANGE                  14:0
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_WIDTH_WOFFSET                        0x0
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_HEIGHT_FIELD                 _MK_FIELD_CONST(0x7fff, DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_HEIGHT_SHIFT)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_HEIGHT_RANGE                 30:16
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_HEIGHT_WOFFSET                       0x0
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_CRC_SIZE_8_0_SIZE_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_GOLDEN_CRC_0_0
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0                 _MK_ADDR_CONST(0x3b6)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_SECURE                  0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_SCR                     0
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_WORD_COUNT                      0x1
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_GOLDEN_CRC_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_GOLDEN_CRC_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_RG_REGION_GOLDEN_CRC_0_0_GOLDEN_CRC_SHIFT)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_GOLDEN_CRC_RANGE                        31:0
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_GOLDEN_CRC_WOFFSET                      0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_GOLDEN_CRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_GOLDEN_CRC_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_GOLDEN_CRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_0_0_GOLDEN_CRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_GOLDEN_CRC_1_0
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0                 _MK_ADDR_CONST(0x3b7)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_SECURE                  0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_SCR                     0
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_WORD_COUNT                      0x1
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_GOLDEN_CRC_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_GOLDEN_CRC_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_RG_REGION_GOLDEN_CRC_1_0_GOLDEN_CRC_SHIFT)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_GOLDEN_CRC_RANGE                        31:0
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_GOLDEN_CRC_WOFFSET                      0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_GOLDEN_CRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_GOLDEN_CRC_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_GOLDEN_CRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_1_0_GOLDEN_CRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_GOLDEN_CRC_2_0
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0                 _MK_ADDR_CONST(0x3b8)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_SECURE                  0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_SCR                     0
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_WORD_COUNT                      0x1
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_GOLDEN_CRC_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_GOLDEN_CRC_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_RG_REGION_GOLDEN_CRC_2_0_GOLDEN_CRC_SHIFT)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_GOLDEN_CRC_RANGE                        31:0
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_GOLDEN_CRC_WOFFSET                      0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_GOLDEN_CRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_GOLDEN_CRC_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_GOLDEN_CRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_2_0_GOLDEN_CRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_GOLDEN_CRC_3_0
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0                 _MK_ADDR_CONST(0x3b9)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_SECURE                  0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_SCR                     0
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_WORD_COUNT                      0x1
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_GOLDEN_CRC_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_GOLDEN_CRC_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_RG_REGION_GOLDEN_CRC_3_0_GOLDEN_CRC_SHIFT)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_GOLDEN_CRC_RANGE                        31:0
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_GOLDEN_CRC_WOFFSET                      0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_GOLDEN_CRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_GOLDEN_CRC_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_GOLDEN_CRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_3_0_GOLDEN_CRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_GOLDEN_CRC_4_0
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0                 _MK_ADDR_CONST(0x3ba)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_SECURE                  0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_SCR                     0
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_WORD_COUNT                      0x1
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_GOLDEN_CRC_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_GOLDEN_CRC_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_RG_REGION_GOLDEN_CRC_4_0_GOLDEN_CRC_SHIFT)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_GOLDEN_CRC_RANGE                        31:0
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_GOLDEN_CRC_WOFFSET                      0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_GOLDEN_CRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_GOLDEN_CRC_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_GOLDEN_CRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_4_0_GOLDEN_CRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_GOLDEN_CRC_5_0
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0                 _MK_ADDR_CONST(0x3bb)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_SECURE                  0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_SCR                     0
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_WORD_COUNT                      0x1
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_GOLDEN_CRC_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_GOLDEN_CRC_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_RG_REGION_GOLDEN_CRC_5_0_GOLDEN_CRC_SHIFT)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_GOLDEN_CRC_RANGE                        31:0
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_GOLDEN_CRC_WOFFSET                      0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_GOLDEN_CRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_GOLDEN_CRC_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_GOLDEN_CRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_5_0_GOLDEN_CRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_GOLDEN_CRC_6_0
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0                 _MK_ADDR_CONST(0x3bc)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_SECURE                  0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_SCR                     0
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_WORD_COUNT                      0x1
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_GOLDEN_CRC_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_GOLDEN_CRC_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_RG_REGION_GOLDEN_CRC_6_0_GOLDEN_CRC_SHIFT)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_GOLDEN_CRC_RANGE                        31:0
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_GOLDEN_CRC_WOFFSET                      0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_GOLDEN_CRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_GOLDEN_CRC_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_GOLDEN_CRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_6_0_GOLDEN_CRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_GOLDEN_CRC_7_0
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0                 _MK_ADDR_CONST(0x3bd)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_SECURE                  0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_SCR                     0
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_WORD_COUNT                      0x1
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_GOLDEN_CRC_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_GOLDEN_CRC_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_RG_REGION_GOLDEN_CRC_7_0_GOLDEN_CRC_SHIFT)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_GOLDEN_CRC_RANGE                        31:0
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_GOLDEN_CRC_WOFFSET                      0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_GOLDEN_CRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_GOLDEN_CRC_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_GOLDEN_CRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_7_0_GOLDEN_CRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_COM_RG_REGION_GOLDEN_CRC_8_0
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0                 _MK_ADDR_CONST(0x3be)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_SECURE                  0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_SCR                     0
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_WORD_COUNT                      0x1
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_GOLDEN_CRC_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_GOLDEN_CRC_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_COM_RG_REGION_GOLDEN_CRC_8_0_GOLDEN_CRC_SHIFT)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_GOLDEN_CRC_RANGE                        31:0
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_GOLDEN_CRC_WOFFSET                      0x0
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_GOLDEN_CRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_GOLDEN_CRC_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_GOLDEN_CRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_COM_RG_REGION_GOLDEN_CRC_8_0_GOLDEN_CRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_DISP_DISP_SIGNAL_OPTIONS0_0
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0                  _MK_ADDR_CONST(0x400)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_SECURE                   0x0
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_SCR                      0
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_WORD_COUNT                       0x1
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_RESET_MASK                       _MK_MASK_CONST(0x180000)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_READ_MASK                        _MK_MASK_CONST(0x180000)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_WRITE_MASK                       _MK_MASK_CONST(0x180000)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_SHIFT                    _MK_SHIFT_CONST(19)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_SHIFT)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_RANGE                    19:19
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_WOFFSET                  0x0
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_SHIFT                    _MK_SHIFT_CONST(20)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_SHIFT)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_RANGE                    20:20
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_WOFFSET                  0x0
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_ENABLE                   _MK_ENUM_CONST(1)


// Register DC_DISP_DISP_WIN_OPTIONS_0
#define DC_DISP_DISP_WIN_OPTIONS_0                      _MK_ADDR_CONST(0x402)
#define DC_DISP_DISP_WIN_OPTIONS_0_SECURE                       0x0
#define DC_DISP_DISP_WIN_OPTIONS_0_SCR                  0
#define DC_DISP_DISP_WIN_OPTIONS_0_WORD_COUNT                   0x1
#define DC_DISP_DISP_WIN_OPTIONS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_RESET_MASK                   _MK_MASK_CONST(0x2e010000)
#define DC_DISP_DISP_WIN_OPTIONS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_READ_MASK                    _MK_MASK_CONST(0x2e010000)
#define DC_DISP_DISP_WIN_OPTIONS_0_WRITE_MASK                   _MK_MASK_CONST(0x2e010000)
#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_SHIFT                  _MK_SHIFT_CONST(16)
#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_SHIFT)
#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_RANGE                  16:16
#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_WOFFSET                        0x0
#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT                     _MK_SHIFT_CONST(25)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_RANGE                     25:25
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_WOFFSET                   0x0
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_ENABLE_SHIFT                    _MK_SHIFT_CONST(26)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_DISP_WIN_OPTIONS_0_SOR1_ENABLE_SHIFT)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_ENABLE_RANGE                    26:26
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_ENABLE_WOFFSET                  0x0
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_SHIFT                        _MK_SHIFT_CONST(27)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_FIELD                        _MK_FIELD_CONST(0x1, DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_SHIFT)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_RANGE                        27:27
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_WOFFSET                      0x0
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_INIT_ENUM                    DP
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_DP                   _MK_ENUM_CONST(0)
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR1_TIMING_CYA_HDMI                 _MK_ENUM_CONST(1)

#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_SHIFT                     _MK_SHIFT_CONST(29)
#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_SHIFT)
#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_RANGE                     29:29
#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_WOFFSET                   0x0
#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_ENABLE                    _MK_ENUM_CONST(1)


// Register DC_DISP_CORE_SOR_SET_CONTROL_0
#define DC_DISP_CORE_SOR_SET_CONTROL_0                  _MK_ADDR_CONST(0x403)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_SECURE                   0x0
#define DC_DISP_CORE_SOR_SET_CONTROL_0_SCR                      0
#define DC_DISP_CORE_SOR_SET_CONTROL_0_WORD_COUNT                       0x1
#define DC_DISP_CORE_SOR_SET_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x600)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0xf00)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0xf00)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0xf00)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_SHIFT                   _MK_SHIFT_CONST(8)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_FIELD                   _MK_FIELD_CONST(0xf, DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_SHIFT)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_RANGE                   11:8
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_WOFFSET                 0x0
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_DEFAULT                 _MK_MASK_CONST(0x6)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_INIT_ENUM                       DP_A
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_LVDS_CUSTOM                     _MK_ENUM_CONST(0)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_SINGLE_TMDS_A                   _MK_ENUM_CONST(1)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_SINGLE_TMDS_B                   _MK_ENUM_CONST(2)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_DUAL_TMDS                       _MK_ENUM_CONST(3)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_DP_A                    _MK_ENUM_CONST(6)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_DP_B                    _MK_ENUM_CONST(7)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_DSI                     _MK_ENUM_CONST(8)
#define DC_DISP_CORE_SOR_SET_CONTROL_0_PROTOCOL_CUSTOM                  _MK_ENUM_CONST(15)


// Register DC_DISP_CORE_SOR1_SET_CONTROL_0
#define DC_DISP_CORE_SOR1_SET_CONTROL_0                 _MK_ADDR_CONST(0x404)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_SECURE                  0x0
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_SCR                     0
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_WORD_COUNT                      0x1
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x100)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0xf00)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0xf00)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0xf00)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_SHIFT                  _MK_SHIFT_CONST(8)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_FIELD                  _MK_FIELD_CONST(0xf, DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_SHIFT)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_RANGE                  11:8
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_WOFFSET                        0x0
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_DEFAULT                        _MK_MASK_CONST(0x1)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_INIT_ENUM                      SINGLE_TMDS_A
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_LVDS_CUSTOM                    _MK_ENUM_CONST(0)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_SINGLE_TMDS_A                  _MK_ENUM_CONST(1)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_SINGLE_TMDS_B                  _MK_ENUM_CONST(2)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_DUAL_TMDS                      _MK_ENUM_CONST(3)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_DP_A                   _MK_ENUM_CONST(6)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_DP_B                   _MK_ENUM_CONST(7)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_DSI                    _MK_ENUM_CONST(8)
#define DC_DISP_CORE_SOR1_SET_CONTROL_0_PROTOCOL_CUSTOM                 _MK_ENUM_CONST(15)


// Register DC_DISP_CORE_DSI_SET_CONTROL_0
#define DC_DISP_CORE_DSI_SET_CONTROL_0                  _MK_ADDR_CONST(0x405)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_SECURE                   0x0
#define DC_DISP_CORE_DSI_SET_CONTROL_0_SCR                      0
#define DC_DISP_CORE_DSI_SET_CONTROL_0_WORD_COUNT                       0x1
#define DC_DISP_CORE_DSI_SET_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x800)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0xf00)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0xf00)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0xf00)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_SHIFT                   _MK_SHIFT_CONST(8)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_FIELD                   _MK_FIELD_CONST(0xf, DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_SHIFT)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_RANGE                   11:8
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_WOFFSET                 0x0
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_DEFAULT                 _MK_MASK_CONST(0x8)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_INIT_ENUM                       DSI
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_LVDS_CUSTOM                     _MK_ENUM_CONST(0)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_SINGLE_TMDS_A                   _MK_ENUM_CONST(1)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_SINGLE_TMDS_B                   _MK_ENUM_CONST(2)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_DUAL_TMDS                       _MK_ENUM_CONST(3)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_DP_A                    _MK_ENUM_CONST(6)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_DP_B                    _MK_ENUM_CONST(7)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_DSI                     _MK_ENUM_CONST(8)
#define DC_DISP_CORE_DSI_SET_CONTROL_0_PROTOCOL_CUSTOM                  _MK_ENUM_CONST(15)


// Register DC_DISP_SYNC_WIDTH_0
#define DC_DISP_SYNC_WIDTH_0                    _MK_ADDR_CONST(0x407)
#define DC_DISP_SYNC_WIDTH_0_SECURE                     0x0
#define DC_DISP_SYNC_WIDTH_0_SCR                        0
#define DC_DISP_SYNC_WIDTH_0_WORD_COUNT                         0x1
#define DC_DISP_SYNC_WIDTH_0_RESET_VAL                  _MK_MASK_CONST(0x10001)
#define DC_DISP_SYNC_WIDTH_0_RESET_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_SYNC_WIDTH_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_SYNC_WIDTH_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_SYNC_WIDTH_0_READ_MASK                  _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_SYNC_WIDTH_0_WRITE_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_FIELD                 _MK_FIELD_CONST(0x7fff, DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_SHIFT)
#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_RANGE                 14:0
#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_WOFFSET                       0x0
#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_DEFAULT                       _MK_MASK_CONST(0x1)
#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_FIELD                 _MK_FIELD_CONST(0x7fff, DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_SHIFT)
#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_RANGE                 30:16
#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_WOFFSET                       0x0
#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_DEFAULT                       _MK_MASK_CONST(0x1)
#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_DISP_BACK_PORCH_0
#define DC_DISP_BACK_PORCH_0                    _MK_ADDR_CONST(0x408)
#define DC_DISP_BACK_PORCH_0_SECURE                     0x0
#define DC_DISP_BACK_PORCH_0_SCR                        0
#define DC_DISP_BACK_PORCH_0_WORD_COUNT                         0x1
#define DC_DISP_BACK_PORCH_0_RESET_VAL                  _MK_MASK_CONST(0x10001)
#define DC_DISP_BACK_PORCH_0_RESET_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_BACK_PORCH_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_BACK_PORCH_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_BACK_PORCH_0_READ_MASK                  _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_BACK_PORCH_0_WRITE_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_FIELD                 _MK_FIELD_CONST(0x7fff, DC_DISP_BACK_PORCH_0_H_BACK_PORCH_SHIFT)
#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_RANGE                 14:0
#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_WOFFSET                       0x0
#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_DEFAULT                       _MK_MASK_CONST(0x1)
#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_FIELD                 _MK_FIELD_CONST(0x7fff, DC_DISP_BACK_PORCH_0_V_BACK_PORCH_SHIFT)
#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_RANGE                 30:16
#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_WOFFSET                       0x0
#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_DEFAULT                       _MK_MASK_CONST(0x1)
#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_DISP_DISP_ACTIVE_0
#define DC_DISP_DISP_ACTIVE_0                   _MK_ADDR_CONST(0x409)
#define DC_DISP_DISP_ACTIVE_0_SECURE                    0x0
#define DC_DISP_DISP_ACTIVE_0_SCR                       0
#define DC_DISP_DISP_ACTIVE_0_WORD_COUNT                        0x1
#define DC_DISP_DISP_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x40008)
#define DC_DISP_DISP_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_DISP_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_DISP_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_FIELD                       _MK_FIELD_CONST(0x7fff, DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_SHIFT)
#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_RANGE                       14:0
#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_WOFFSET                     0x0
#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_DEFAULT                     _MK_MASK_CONST(0x8)
#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_DEFAULT_MASK                        _MK_MASK_CONST(0x7fff)
#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_SHIFT                       _MK_SHIFT_CONST(16)
#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_FIELD                       _MK_FIELD_CONST(0x7fff, DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_SHIFT)
#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_RANGE                       30:16
#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_WOFFSET                     0x0
#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_DEFAULT                     _MK_MASK_CONST(0x4)
#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_DEFAULT_MASK                        _MK_MASK_CONST(0x7fff)
#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_DISP_FRONT_PORCH_0
#define DC_DISP_FRONT_PORCH_0                   _MK_ADDR_CONST(0x40a)
#define DC_DISP_FRONT_PORCH_0_SECURE                    0x0
#define DC_DISP_FRONT_PORCH_0_SCR                       0
#define DC_DISP_FRONT_PORCH_0_WORD_COUNT                        0x1
#define DC_DISP_FRONT_PORCH_0_RESET_VAL                         _MK_MASK_CONST(0x10001)
#define DC_DISP_FRONT_PORCH_0_RESET_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_FRONT_PORCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_FRONT_PORCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_FRONT_PORCH_0_READ_MASK                         _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_FRONT_PORCH_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff7fff)
#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_FIELD                       _MK_FIELD_CONST(0x7fff, DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_SHIFT)
#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_RANGE                       14:0
#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_WOFFSET                     0x0
#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_DEFAULT                     _MK_MASK_CONST(0x1)
#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_DEFAULT_MASK                        _MK_MASK_CONST(0x7fff)
#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_SHIFT                       _MK_SHIFT_CONST(16)
#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_FIELD                       _MK_FIELD_CONST(0x7fff, DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_SHIFT)
#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_RANGE                       30:16
#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_WOFFSET                     0x0
#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_DEFAULT                     _MK_MASK_CONST(0x1)
#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_DEFAULT_MASK                        _MK_MASK_CONST(0x7fff)
#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0                 _MK_ADDR_CONST(0x410)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SECURE                  0x0
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SCR                     0
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_WORD_COUNT                      0x1
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_RESET_MASK                      _MK_MASK_CONST(0x7fffffff)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_READ_MASK                       _MK_MASK_CONST(0x7fffffff)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_WRITE_MASK                      _MK_MASK_CONST(0x7fff8000)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_HEIGHT_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_HEIGHT_FIELD                     _MK_FIELD_CONST(0x3fff, DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_HEIGHT_SHIFT)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_HEIGHT_RANGE                     13:0
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_HEIGHT_WOFFSET                   0x0
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_HEIGHT_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_HEIGHT_DEFAULT_MASK                      _MK_MASK_CONST(0x3fff)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_HEIGHT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_HEIGHT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_ENABLE_SHIFT                     _MK_SHIFT_CONST(14)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_ENABLE_SHIFT)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_ENABLE_RANGE                     14:14
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_ENABLE_WOFFSET                   0x0
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_ENABLE_NO                        _MK_ENUM_CONST(0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_EXTEND_ENABLE_YES                       _MK_ENUM_CONST(1)

#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_DBG_SHIFT                       _MK_SHIFT_CONST(15)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_DBG_FIELD                       _MK_FIELD_CONST(0x1, DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_DBG_SHIFT)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_DBG_RANGE                       15:15
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_DBG_WOFFSET                     0x0
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_DBG_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_DBG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_DBG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_DBG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_HEIGHT_SHIFT                        _MK_SHIFT_CONST(16)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_HEIGHT_FIELD                        _MK_FIELD_CONST(0x3fff, DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_HEIGHT_SHIFT)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_HEIGHT_RANGE                        29:16
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_HEIGHT_WOFFSET                      0x0
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_HEIGHT_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_HEIGHT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_HEIGHT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_HEIGHT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_ENABLE_SHIFT)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_ENABLE_RANGE                        30:30
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_ENABLE_WOFFSET                      0x0
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_ENABLE_NO                   _MK_ENUM_CONST(0)
#define DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0_SET_ENABLE_YES                  _MK_ENUM_CONST(1)


// Register DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0                        _MK_ADDR_CONST(0x411)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SECURE                         0x0
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SCR                    0
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_WORD_COUNT                     0x1
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_RESET_MASK                     _MK_MASK_CONST(0x7fffffff)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_READ_MASK                      _MK_MASK_CONST(0x7fffffff)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_WRITE_MASK                     _MK_MASK_CONST(0x7fff8000)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_HEIGHT_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_HEIGHT_FIELD                    _MK_FIELD_CONST(0x3fff, DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_HEIGHT_SHIFT)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_HEIGHT_RANGE                    13:0
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_HEIGHT_WOFFSET                  0x0
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_HEIGHT_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_HEIGHT_DEFAULT_MASK                     _MK_MASK_CONST(0x3fff)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_HEIGHT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_HEIGHT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_ENABLE_SHIFT                    _MK_SHIFT_CONST(14)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_ENABLE_SHIFT)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_ENABLE_RANGE                    14:14
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_ENABLE_WOFFSET                  0x0
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_ENABLE_NO                       _MK_ENUM_CONST(0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_EXTEND_ENABLE_YES                      _MK_ENUM_CONST(1)

#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_DBG_SHIFT                      _MK_SHIFT_CONST(15)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_DBG_FIELD                      _MK_FIELD_CONST(0x1, DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_DBG_SHIFT)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_DBG_RANGE                      15:15
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_DBG_WOFFSET                    0x0
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_DBG_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_DBG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_DBG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_DBG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_HEIGHT_SHIFT                       _MK_SHIFT_CONST(16)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_HEIGHT_FIELD                       _MK_FIELD_CONST(0x3fff, DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_HEIGHT_SHIFT)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_HEIGHT_RANGE                       29:16
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_HEIGHT_WOFFSET                     0x0
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_HEIGHT_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_HEIGHT_DEFAULT_MASK                        _MK_MASK_CONST(0x3fff)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_HEIGHT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_HEIGHT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_ENABLE_SHIFT                       _MK_SHIFT_CONST(30)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_ENABLE_SHIFT)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_ENABLE_RANGE                       30:30
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_ENABLE_WOFFSET                     0x0
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_ENABLE_NO                  _MK_ENUM_CONST(0)
#define DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0_SET_ENABLE_YES                 _MK_ENUM_CONST(1)


// Register DC_DISP_RG_RASTER_EXTEND_0
#define DC_DISP_RG_RASTER_EXTEND_0                      _MK_ADDR_CONST(0x412)
#define DC_DISP_RG_RASTER_EXTEND_0_SECURE                       0x0
#define DC_DISP_RG_RASTER_EXTEND_0_SCR                  0
#define DC_DISP_RG_RASTER_EXTEND_0_WORD_COUNT                   0x1
#define DC_DISP_RG_RASTER_EXTEND_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_RESET_MASK                   _MK_MASK_CONST(0x7fffffff)
#define DC_DISP_RG_RASTER_EXTEND_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
#define DC_DISP_RG_RASTER_EXTEND_0_WRITE_MASK                   _MK_MASK_CONST(0x7fff8000)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_WIDTH_FIELD                   _MK_FIELD_CONST(0x3fff, DC_DISP_RG_RASTER_EXTEND_0_EXTEND_WIDTH_SHIFT)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_WIDTH_RANGE                   13:0
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_WIDTH_WOFFSET                 0x0
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_ENABLE_SHIFT                  _MK_SHIFT_CONST(14)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, DC_DISP_RG_RASTER_EXTEND_0_EXTEND_ENABLE_SHIFT)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_ENABLE_RANGE                  14:14
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_ENABLE_WOFFSET                        0x0
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_ENABLE_NO                     _MK_ENUM_CONST(0)
#define DC_DISP_RG_RASTER_EXTEND_0_EXTEND_ENABLE_YES                    _MK_ENUM_CONST(1)

#define DC_DISP_RG_RASTER_EXTEND_0_DBG_SHIFT                    _MK_SHIFT_CONST(15)
#define DC_DISP_RG_RASTER_EXTEND_0_DBG_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_RG_RASTER_EXTEND_0_DBG_SHIFT)
#define DC_DISP_RG_RASTER_EXTEND_0_DBG_RANGE                    15:15
#define DC_DISP_RG_RASTER_EXTEND_0_DBG_WOFFSET                  0x0
#define DC_DISP_RG_RASTER_EXTEND_0_DBG_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_DBG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_RG_RASTER_EXTEND_0_DBG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_DBG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_DISP_RG_RASTER_EXTEND_0_SET_WIDTH_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_WIDTH_FIELD                      _MK_FIELD_CONST(0x3fff, DC_DISP_RG_RASTER_EXTEND_0_SET_WIDTH_SHIFT)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_WIDTH_RANGE                      29:16
#define DC_DISP_RG_RASTER_EXTEND_0_SET_WIDTH_WOFFSET                    0x0
#define DC_DISP_RG_RASTER_EXTEND_0_SET_WIDTH_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x3fff)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_DISP_RG_RASTER_EXTEND_0_SET_ENABLE_SHIFT                     _MK_SHIFT_CONST(30)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, DC_DISP_RG_RASTER_EXTEND_0_SET_ENABLE_SHIFT)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_ENABLE_RANGE                     30:30
#define DC_DISP_RG_RASTER_EXTEND_0_SET_ENABLE_WOFFSET                   0x0
#define DC_DISP_RG_RASTER_EXTEND_0_SET_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_ENABLE_NO                        _MK_ENUM_CONST(0)
#define DC_DISP_RG_RASTER_EXTEND_0_SET_ENABLE_YES                       _MK_ENUM_CONST(1)


// Register DC_DISP_RG_ELV_0
#define DC_DISP_RG_ELV_0                        _MK_ADDR_CONST(0x413)
#define DC_DISP_RG_ELV_0_SECURE                         0x0
#define DC_DISP_RG_ELV_0_SCR                    0
#define DC_DISP_RG_ELV_0_WORD_COUNT                     0x1
#define DC_DISP_RG_ELV_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_ELV_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_ELV_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_DISP_RG_ELV_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_ELV_0_READ_MASK                      _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_ELV_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_ELV_0_START_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_DISP_RG_ELV_0_START_FIELD                    _MK_FIELD_CONST(0xffff, DC_DISP_RG_ELV_0_START_SHIFT)
#define DC_DISP_RG_ELV_0_START_RANGE                    15:0
#define DC_DISP_RG_ELV_0_START_WOFFSET                  0x0
#define DC_DISP_RG_ELV_0_START_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_ELV_0_START_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_ELV_0_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_ELV_0_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_DISP_CORE_HEAD_SET_STALL_LOCK_0
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0                      _MK_ADDR_CONST(0x414)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_SECURE                       0x0
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_SCR                  0
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_WORD_COUNT                   0x1
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_RESET_VAL                    _MK_MASK_CONST(0x80)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_RESET_MASK                   _MK_MASK_CONST(0x80)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_READ_MASK                    _MK_MASK_CONST(0x80)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_WRITE_MASK                   _MK_MASK_CONST(0x80)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_SHIFT                   _MK_SHIFT_CONST(7)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_FIELD                   _MK_FIELD_CONST(0x1, DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_SHIFT)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_RANGE                   7:7
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_WOFFSET                 0x0
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_DEFAULT                 _MK_MASK_CONST(0x1)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_INIT_ENUM                       LINE_LOCK
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_CRASH_LOCK                      _MK_ENUM_CONST(0)
#define DC_DISP_CORE_HEAD_SET_STALL_LOCK_0_UNSTALL_MODE_LINE_LOCK                       _MK_ENUM_CONST(1)


// Register DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0                    _MK_ADDR_CONST(0x415)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_SECURE                     0x0
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_SCR                        0
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_WORD_COUNT                         0x1
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_RESET_MASK                         _MK_MASK_CONST(0xfffffe)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_READ_MASK                  _MK_MASK_CONST(0xfffffe)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffe)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_INTERVAL_SHIFT                 _MK_SHIFT_CONST(1)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_INTERVAL_FIELD                 _MK_FIELD_CONST(0x3fffff, DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_INTERVAL_SHIFT)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_INTERVAL_RANGE                 22:1
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_INTERVAL_WOFFSET                       0x0
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_INTERVAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_INTERVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3fffff)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_INTERVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_INTERVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_SHIFT                  _MK_SHIFT_CONST(23)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_FIELD                  _MK_FIELD_CONST(0x1, DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_SHIFT)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_RANGE                  23:23
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_WOFFSET                        0x0
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_DISABLE                        _MK_ENUM_CONST(0)
#define DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0_MIN_REFRESH_ENABLE                 _MK_ENUM_CONST(1)


// Register DC_DISP_RG_UNSTALL_SPOOLUP_0
#define DC_DISP_RG_UNSTALL_SPOOLUP_0                    _MK_ADDR_CONST(0x416)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_SECURE                     0x0
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_SCR                        0
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_WORD_COUNT                         0x1
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_VALUE_FIELD                        _MK_FIELD_CONST(0xfffff, DC_DISP_RG_UNSTALL_SPOOLUP_0_VALUE_SHIFT)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_VALUE_RANGE                        19:0
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_VALUE_WOFFSET                      0x0
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xfffff)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_UNSTALL_SPOOLUP_0_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_DISP_RG_STOP_FETCH_0
#define DC_DISP_RG_STOP_FETCH_0                 _MK_ADDR_CONST(0x417)
#define DC_DISP_RG_STOP_FETCH_0_SECURE                  0x0
#define DC_DISP_RG_STOP_FETCH_0_SCR                     0
#define DC_DISP_RG_STOP_FETCH_0_WORD_COUNT                      0x1
#define DC_DISP_RG_STOP_FETCH_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_STOP_FETCH_0_RESET_MASK                      _MK_MASK_CONST(0x3ffffff)
#define DC_DISP_RG_STOP_FETCH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_STOP_FETCH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_RG_STOP_FETCH_0_READ_MASK                       _MK_MASK_CONST(0x3ffffff)
#define DC_DISP_RG_STOP_FETCH_0_WRITE_MASK                      _MK_MASK_CONST(0x3ffffff)
#define DC_DISP_RG_STOP_FETCH_0_START_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_DISP_RG_STOP_FETCH_0_START_FIELD                     _MK_FIELD_CONST(0x3ffffff, DC_DISP_RG_STOP_FETCH_0_START_SHIFT)
#define DC_DISP_RG_STOP_FETCH_0_START_RANGE                     25:0
#define DC_DISP_RG_STOP_FETCH_0_START_WOFFSET                   0x0
#define DC_DISP_RG_STOP_FETCH_0_START_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_STOP_FETCH_0_START_DEFAULT_MASK                      _MK_MASK_CONST(0x3ffffff)
#define DC_DISP_RG_STOP_FETCH_0_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_STOP_FETCH_0_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_DISP_START_FETCH_DLY_0
#define DC_DISP_START_FETCH_DLY_0                       _MK_ADDR_CONST(0x418)
#define DC_DISP_START_FETCH_DLY_0_SECURE                        0x0
#define DC_DISP_START_FETCH_DLY_0_SCR                   0
#define DC_DISP_START_FETCH_DLY_0_WORD_COUNT                    0x1
#define DC_DISP_START_FETCH_DLY_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_START_FETCH_DLY_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define DC_DISP_START_FETCH_DLY_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_DISP_START_FETCH_DLY_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_START_FETCH_DLY_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define DC_DISP_START_FETCH_DLY_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define DC_DISP_START_FETCH_DLY_0_DELAY_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_DISP_START_FETCH_DLY_0_DELAY_FIELD                   _MK_FIELD_CONST(0xffff, DC_DISP_START_FETCH_DLY_0_DELAY_SHIFT)
#define DC_DISP_START_FETCH_DLY_0_DELAY_RANGE                   15:0
#define DC_DISP_START_FETCH_DLY_0_DELAY_WOFFSET                 0x0
#define DC_DISP_START_FETCH_DLY_0_DELAY_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_START_FETCH_DLY_0_DELAY_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define DC_DISP_START_FETCH_DLY_0_DELAY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_START_FETCH_DLY_0_DELAY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register DC_DISP_V_PULSE2_POSITION_A_0
#define DC_DISP_V_PULSE2_POSITION_A_0                   _MK_ADDR_CONST(0x423)
#define DC_DISP_V_PULSE2_POSITION_A_0_SECURE                    0x0
#define DC_DISP_V_PULSE2_POSITION_A_0_SCR                       0
#define DC_DISP_V_PULSE2_POSITION_A_0_WORD_COUNT                        0x1
#define DC_DISP_V_PULSE2_POSITION_A_0_RESET_VAL                         _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE2_POSITION_A_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE2_POSITION_A_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_V_PULSE2_POSITION_A_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_V_PULSE2_POSITION_A_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE2_POSITION_A_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_FIELD                    _MK_FIELD_CONST(0xffff, DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_SHIFT)
#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_RANGE                    15:0
#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_WOFFSET                  0x0
#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_DEFAULT                  _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_DISP_V_PULSE3_POSITION_A_0
#define DC_DISP_V_PULSE3_POSITION_A_0                   _MK_ADDR_CONST(0x425)
#define DC_DISP_V_PULSE3_POSITION_A_0_SECURE                    0x0
#define DC_DISP_V_PULSE3_POSITION_A_0_SCR                       0
#define DC_DISP_V_PULSE3_POSITION_A_0_WORD_COUNT                        0x1
#define DC_DISP_V_PULSE3_POSITION_A_0_RESET_VAL                         _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE3_POSITION_A_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE3_POSITION_A_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_V_PULSE3_POSITION_A_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_V_PULSE3_POSITION_A_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE3_POSITION_A_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_FIELD                    _MK_FIELD_CONST(0xffff, DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_SHIFT)
#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_RANGE                    15:0
#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_WOFFSET                  0x0
#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_DEFAULT                  _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_DISP_DISP_COLOR_CONTROL_0
#define DC_DISP_DISP_COLOR_CONTROL_0                    _MK_ADDR_CONST(0x430)
#define DC_DISP_DISP_COLOR_CONTROL_0_SECURE                     0x0
#define DC_DISP_DISP_COLOR_CONTROL_0_SCR                        0
#define DC_DISP_DISP_COLOR_CONTROL_0_WORD_COUNT                         0x1
#define DC_DISP_DISP_COLOR_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x1833cf)
#define DC_DISP_DISP_COLOR_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x1833cf)
#define DC_DISP_DISP_COLOR_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x1833cf)
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_FIELD                      _MK_FIELD_CONST(0xf, DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_SHIFT)
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_RANGE                      3:0
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_WOFFSET                    0x0
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE666                    _MK_ENUM_CONST(0)
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE888                    _MK_ENUM_CONST(8)
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE101010                 _MK_ENUM_CONST(10)
#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE121212                 _MK_ENUM_CONST(12)

#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_SHIFT                        _MK_SHIFT_CONST(6)
#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_FIELD                        _MK_FIELD_CONST(0x3, DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_SHIFT)
#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_RANGE                        7:6
#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_WOFFSET                      0x0
#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_SHIFT                       _MK_SHIFT_CONST(8)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_FIELD                       _MK_FIELD_CONST(0x3, DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_SHIFT)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_RANGE                       9:8
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_WOFFSET                     0x0
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_INIT_ENUM                   DISABLE
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_DISABLE                     _MK_ENUM_CONST(0)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_ERR_ACC                     _MK_ENUM_CONST(1)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_ORDERED                     _MK_ENUM_CONST(2)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_TEMPORAL                    _MK_ENUM_CONST(3)

#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_SHIFT                  _MK_SHIFT_CONST(12)
#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_FIELD                  _MK_FIELD_CONST(0x3, DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_SHIFT)
#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_RANGE                  13:12
#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_WOFFSET                        0x0
#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_SHIFT                        _MK_SHIFT_CONST(19)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_FIELD                        _MK_FIELD_CONST(0x1, DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_SHIFT)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_RANGE                        19:19
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_WOFFSET                      0x0
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_INIT_ENUM                    DISABLE
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_DISABLE                      _MK_ENUM_CONST(0)
#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_OFFSET_ENABLE                       _MK_ENUM_CONST(1)

#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_SHIFT                   _MK_SHIFT_CONST(20)
#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_SHIFT)
#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_RANGE                   20:20
#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_WOFFSET                 0x0
#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_INIT_ENUM                       DISABLE
#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_ENABLE                  _MK_ENUM_CONST(1)


// Register DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0                      _MK_ADDR_CONST(0x431)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SECURE                       0x0
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SCR                  0
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_WORD_COUNT                   0x1
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RESET_VAL                    _MK_MASK_CONST(0x20)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RESET_MASK                   _MK_MASK_CONST(0x7e)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_READ_MASK                    _MK_MASK_CONST(0x7e)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_WRITE_MASK                   _MK_MASK_CONST(0x7e)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SIZE_SHIFT                   _MK_SHIFT_CONST(1)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SIZE_FIELD                   _MK_FIELD_CONST(0x3, DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SIZE_SHIFT)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SIZE_RANGE                   2:1
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SIZE_WOFFSET                 0x0
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SIZE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SIZE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SIZE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SIZE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SIZE_SIZE_257                        _MK_ENUM_CONST(0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_SIZE_SIZE_1025                       _MK_ENUM_CONST(2)

#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_SHIFT                  _MK_SHIFT_CONST(3)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_FIELD                  _MK_FIELD_CONST(0x3, DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_SHIFT)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_RANGE                  4:3
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_WOFFSET                        0x0
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_UNITY                  _MK_ENUM_CONST(0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_XRBIAS                 _MK_ENUM_CONST(1)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_RANGE_XVYCC                  _MK_ENUM_CONST(2)

#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_OUTPUT_MODE_SHIFT                    _MK_SHIFT_CONST(5)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_OUTPUT_MODE_FIELD                    _MK_FIELD_CONST(0x3, DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_OUTPUT_MODE_SHIFT)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_OUTPUT_MODE_RANGE                    6:5
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_OUTPUT_MODE_WOFFSET                  0x0
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_OUTPUT_MODE_DEFAULT                  _MK_MASK_CONST(0x1)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_OUTPUT_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_OUTPUT_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_OUTPUT_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_OUTPUT_MODE_INDEX                    _MK_ENUM_CONST(0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0_OUTPUT_MODE_INTERPOLATE                      _MK_ENUM_CONST(1)


// Register DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0                      _MK_ADDR_CONST(0x432)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_SECURE                       0x0
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_SCR                  0
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_WORD_COUNT                   0x1
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_ADDRESS_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_ADDRESS_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_ADDRESS_SHIFT)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_ADDRESS_RANGE                        31:0
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_ADDRESS_WOFFSET                      0x0
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_ADDRESS_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_ADDRESS_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_ADDRESS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0_ADDRESS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0                   _MK_ADDR_CONST(0x433)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_SECURE                    0x0
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_SCR                       0
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_WORD_COUNT                        0x1
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_ADDRESS_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_ADDRESS_FIELD                     _MK_FIELD_CONST(0xff, DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_ADDRESS_SHIFT)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_ADDRESS_RANGE                     7:0
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_ADDRESS_WOFFSET                   0x0
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_ADDRESS_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_ADDRESS_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_ADDRESS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0_ADDRESS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_DISP_CORE_HEAD_SET_PROCAMP_0
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0                 _MK_ADDR_CONST(0x434)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SECURE                  0x0
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SCR                     0
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_WORD_COUNT                      0x1
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_RESET_VAL                       _MK_MASK_CONST(0x2000)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_RESET_MASK                      _MK_MASK_CONST(0x7fffffc)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_READ_MASK                       _MK_MASK_CONST(0x7fffffc)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_WRITE_MASK                      _MK_MASK_CONST(0x7fffffc)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_CHROMA_LPF_SHIFT                        _MK_SHIFT_CONST(2)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_CHROMA_LPF_FIELD                        _MK_FIELD_CONST(0x1, DC_DISP_CORE_HEAD_SET_PROCAMP_0_CHROMA_LPF_SHIFT)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_CHROMA_LPF_RANGE                        2:2
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_CHROMA_LPF_WOFFSET                      0x0
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_CHROMA_LPF_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_CHROMA_LPF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_CHROMA_LPF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_CHROMA_LPF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_CHROMA_LPF_DISABLE                      _MK_ENUM_CONST(0)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_CHROMA_LPF_ENABLE                       _MK_ENUM_CONST(1)

#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_COS_SHIFT                   _MK_SHIFT_CONST(3)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_COS_FIELD                   _MK_FIELD_CONST(0xfff, DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_COS_SHIFT)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_COS_RANGE                   14:3
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_COS_WOFFSET                 0x0
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_COS_DEFAULT                 _MK_MASK_CONST(0x400)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_COS_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_COS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_COS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_SINE_SHIFT                  _MK_SHIFT_CONST(15)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_SINE_FIELD                  _MK_FIELD_CONST(0xfff, DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_SINE_SHIFT)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_SINE_RANGE                  26:15
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_SINE_WOFFSET                        0x0
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_SINE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_SINE_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_SINE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_PROCAMP_0_SAT_SINE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_DISP_COLOR_KEY0_LOWER0_0
#define DC_DISP_COLOR_KEY0_LOWER0_0                     _MK_ADDR_CONST(0x436)
#define DC_DISP_COLOR_KEY0_LOWER0_0_SECURE                      0x0
#define DC_DISP_COLOR_KEY0_LOWER0_0_SCR                         0
#define DC_DISP_COLOR_KEY0_LOWER0_0_WORD_COUNT                  0x1
#define DC_DISP_COLOR_KEY0_LOWER0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_LOWER0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_LOWER0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_R_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_R_FIELD                        _MK_FIELD_CONST(0xffff, DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_R_SHIFT)
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_R_RANGE                        15:0
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_R_WOFFSET                      0x0
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_R_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_R_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_G_SHIFT                        _MK_SHIFT_CONST(16)
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_G_FIELD                        _MK_FIELD_CONST(0xffff, DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_G_SHIFT)
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_G_RANGE                        31:16
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_G_WOFFSET                      0x0
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_G_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_G_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_G_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER0_0_COLOR_KEY0_L_G_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_DISP_COLOR_KEY0_LOWER1_0
#define DC_DISP_COLOR_KEY0_LOWER1_0                     _MK_ADDR_CONST(0x437)
#define DC_DISP_COLOR_KEY0_LOWER1_0_SECURE                      0x0
#define DC_DISP_COLOR_KEY0_LOWER1_0_SCR                         0
#define DC_DISP_COLOR_KEY0_LOWER1_0_WORD_COUNT                  0x1
#define DC_DISP_COLOR_KEY0_LOWER1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_LOWER1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_LOWER1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_B_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_B_FIELD                        _MK_FIELD_CONST(0xffff, DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_B_SHIFT)
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_B_RANGE                        15:0
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_B_WOFFSET                      0x0
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_B_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_A_SHIFT                        _MK_SHIFT_CONST(16)
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_A_FIELD                        _MK_FIELD_CONST(0xffff, DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_A_SHIFT)
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_A_RANGE                        31:16
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_A_WOFFSET                      0x0
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_A_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_LOWER1_0_COLOR_KEY0_L_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_DISP_COLOR_KEY0_UPPER0_0
#define DC_DISP_COLOR_KEY0_UPPER0_0                     _MK_ADDR_CONST(0x438)
#define DC_DISP_COLOR_KEY0_UPPER0_0_SECURE                      0x0
#define DC_DISP_COLOR_KEY0_UPPER0_0_SCR                         0
#define DC_DISP_COLOR_KEY0_UPPER0_0_WORD_COUNT                  0x1
#define DC_DISP_COLOR_KEY0_UPPER0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_UPPER0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_UPPER0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_R_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_R_FIELD                        _MK_FIELD_CONST(0xffff, DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_R_SHIFT)
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_R_RANGE                        15:0
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_R_WOFFSET                      0x0
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_R_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_R_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_R_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_R_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_G_SHIFT                        _MK_SHIFT_CONST(16)
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_G_FIELD                        _MK_FIELD_CONST(0xffff, DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_G_SHIFT)
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_G_RANGE                        31:16
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_G_WOFFSET                      0x0
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_G_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_G_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_G_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER0_0_COLOR_KEY0_U_G_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_DISP_COLOR_KEY0_UPPER1_0
#define DC_DISP_COLOR_KEY0_UPPER1_0                     _MK_ADDR_CONST(0x439)
#define DC_DISP_COLOR_KEY0_UPPER1_0_SECURE                      0x0
#define DC_DISP_COLOR_KEY0_UPPER1_0_SCR                         0
#define DC_DISP_COLOR_KEY0_UPPER1_0_WORD_COUNT                  0x1
#define DC_DISP_COLOR_KEY0_UPPER1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_UPPER1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_UPPER1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_B_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_B_FIELD                        _MK_FIELD_CONST(0xffff, DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_B_SHIFT)
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_B_RANGE                        15:0
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_B_WOFFSET                      0x0
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_B_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_A_SHIFT                        _MK_SHIFT_CONST(16)
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_A_FIELD                        _MK_FIELD_CONST(0xffff, DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_A_SHIFT)
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_A_RANGE                        31:16
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_A_WOFFSET                      0x0
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_A_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_COLOR_KEY0_UPPER1_0_COLOR_KEY0_U_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0                  _MK_ADDR_CONST(0x43b)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_SECURE                   0x0
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_SCR                      0
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_WORD_COUNT                       0x1
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_RESET_VAL                        _MK_MASK_CONST(0x19e)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_RESET_MASK                       _MK_MASK_CONST(0x180001fe)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_READ_MASK                        _MK_MASK_CONST(0x180001fe)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_WRITE_MASK                       _MK_MASK_CONST(0x180001fe)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_FORMAT_SHIFT                     _MK_SHIFT_CONST(1)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_FORMAT_FIELD                     _MK_FIELD_CONST(0xff, DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_FORMAT_SHIFT)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_FORMAT_RANGE                     8:1
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_FORMAT_WOFFSET                   0x0
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_FORMAT_DEFAULT                   _MK_MASK_CONST(0xcf)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_FORMAT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_FORMAT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_FORMAT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_FORMAT_T_A1R5G5B5                        _MK_ENUM_CONST(233)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_FORMAT_T_A8R8G8B8                        _MK_ENUM_CONST(207)

#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_SHIFT                   _MK_SHIFT_CONST(27)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_FIELD                   _MK_FIELD_CONST(0x3, DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_SHIFT)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_RANGE                   28:27
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_WOFFSET                 0x0
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_NONE                    _MK_ENUM_CONST(0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_SRGB                    _MK_ENUM_CONST(1)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0_DE_GAMMA_YUV                     _MK_ENUM_CONST(2)


// Register DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0                       _MK_ADDR_CONST(0x43c)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_SECURE                        0x0
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_SCR                   0
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_WORD_COUNT                    0x1
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_RESET_VAL                     _MK_MASK_CONST(0x19e)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_RESET_MASK                    _MK_MASK_CONST(0x180001fe)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_READ_MASK                     _MK_MASK_CONST(0x180001fe)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_WRITE_MASK                    _MK_MASK_CONST(0x180001fe)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_FORMAT_NS_SHIFT                       _MK_SHIFT_CONST(1)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_FORMAT_NS_FIELD                       _MK_FIELD_CONST(0xff, DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_FORMAT_NS_SHIFT)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_FORMAT_NS_RANGE                       8:1
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_FORMAT_NS_WOFFSET                     0x0
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_FORMAT_NS_DEFAULT                     _MK_MASK_CONST(0xcf)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_FORMAT_NS_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_FORMAT_NS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_FORMAT_NS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_FORMAT_NS_T_A1R5G5B5                  _MK_ENUM_CONST(233)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_FORMAT_NS_T_A8R8G8B8                  _MK_ENUM_CONST(207)

#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_SHIFT                     _MK_SHIFT_CONST(27)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_FIELD                     _MK_FIELD_CONST(0x3, DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_SHIFT)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_RANGE                     28:27
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_WOFFSET                   0x0
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_NONE                      _MK_ENUM_CONST(0)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_sRGB                      _MK_ENUM_CONST(1)
#define DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0_DE_GAMMA_NS_YUV                       _MK_ENUM_CONST(2)


// Register DC_DISP_CURSOR_START_ADDR_0
#define DC_DISP_CURSOR_START_ADDR_0                     _MK_ADDR_CONST(0x43e)
#define DC_DISP_CURSOR_START_ADDR_0_SECURE                      0x0
#define DC_DISP_CURSOR_START_ADDR_0_SCR                         0
#define DC_DISP_CURSOR_START_ADDR_0_WORD_COUNT                  0x1
#define DC_DISP_CURSOR_START_ADDR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_0_RESET_MASK                  _MK_MASK_CONST(0x33fffff)
#define DC_DISP_CURSOR_START_ADDR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_0_READ_MASK                   _MK_MASK_CONST(0x33fffff)
#define DC_DISP_CURSOR_START_ADDR_0_WRITE_MASK                  _MK_MASK_CONST(0x33fffff)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_FIELD                     _MK_FIELD_CONST(0x3fffff, DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_SHIFT)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_RANGE                     21:0
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_WOFFSET                   0x0
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0x3fffff)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_SHIFT                   _MK_SHIFT_CONST(24)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_FIELD                   _MK_FIELD_CONST(0x3, DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_SHIFT)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_RANGE                   25:24
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_WOFFSET                 0x0
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_C32X32                  _MK_ENUM_CONST(0)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_C64X64                  _MK_ENUM_CONST(1)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_C128X128                        _MK_ENUM_CONST(2)
#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_C256X256                        _MK_ENUM_CONST(3)


// Register DC_DISP_CURSOR_START_ADDR_NS_0
#define DC_DISP_CURSOR_START_ADDR_NS_0                  _MK_ADDR_CONST(0x43f)
#define DC_DISP_CURSOR_START_ADDR_NS_0_SECURE                   0x0
#define DC_DISP_CURSOR_START_ADDR_NS_0_SCR                      0
#define DC_DISP_CURSOR_START_ADDR_NS_0_WORD_COUNT                       0x1
#define DC_DISP_CURSOR_START_ADDR_NS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_NS_0_RESET_MASK                       _MK_MASK_CONST(0x33fffff)
#define DC_DISP_CURSOR_START_ADDR_NS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_NS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_NS_0_READ_MASK                        _MK_MASK_CONST(0x33fffff)
#define DC_DISP_CURSOR_START_ADDR_NS_0_WRITE_MASK                       _MK_MASK_CONST(0x33fffff)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_FIELD                       _MK_FIELD_CONST(0x3fffff, DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_SHIFT)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_RANGE                       21:0
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_WOFFSET                     0x0
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_DEFAULT_MASK                        _MK_MASK_CONST(0x3fffff)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_SHIFT                     _MK_SHIFT_CONST(24)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_FIELD                     _MK_FIELD_CONST(0x3, DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_SHIFT)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_RANGE                     25:24
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_WOFFSET                   0x0
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_C32X32                    _MK_ENUM_CONST(0)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_C64X64                    _MK_ENUM_CONST(1)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_C128X128                  _MK_ENUM_CONST(2)
#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_C256X256                  _MK_ENUM_CONST(3)


// Register DC_DISP_CURSOR_POSITION_0
#define DC_DISP_CURSOR_POSITION_0                       _MK_ADDR_CONST(0x440)
#define DC_DISP_CURSOR_POSITION_0_SECURE                        0x0
#define DC_DISP_CURSOR_POSITION_0_SCR                   0
#define DC_DISP_CURSOR_POSITION_0_WORD_COUNT                    0x1
#define DC_DISP_CURSOR_POSITION_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_DISP_CURSOR_POSITION_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_DISP_CURSOR_POSITION_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_FIELD                       _MK_FIELD_CONST(0xffff, DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_SHIFT)
#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_RANGE                       15:0
#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_WOFFSET                     0x0
#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_SHIFT                       _MK_SHIFT_CONST(16)
#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_FIELD                       _MK_FIELD_CONST(0xffff, DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_SHIFT)
#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_RANGE                       31:16
#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_WOFFSET                     0x0
#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_DISP_CURSOR_POSITION_NS_0
#define DC_DISP_CURSOR_POSITION_NS_0                    _MK_ADDR_CONST(0x441)
#define DC_DISP_CURSOR_POSITION_NS_0_SECURE                     0x0
#define DC_DISP_CURSOR_POSITION_NS_0_SCR                        0
#define DC_DISP_CURSOR_POSITION_NS_0_WORD_COUNT                         0x1
#define DC_DISP_CURSOR_POSITION_NS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_NS_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_DISP_CURSOR_POSITION_NS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_NS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_NS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_CURSOR_POSITION_NS_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_FIELD                 _MK_FIELD_CONST(0xffff, DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_SHIFT)
#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_RANGE                 15:0
#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_WOFFSET                       0x0
#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_FIELD                 _MK_FIELD_CONST(0xffff, DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_SHIFT)
#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_RANGE                 31:16
#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_WOFFSET                       0x0
#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0                        _MK_ADDR_CONST(0x442)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_SECURE                         0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_SCR                    0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_WORD_COUNT                     0x1
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_X_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_X_FIELD                        _MK_FIELD_CONST(0xffff, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_X_SHIFT)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_X_RANGE                        15:0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_X_WOFFSET                      0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_X_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_X_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_X_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_X_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_Y_SHIFT                        _MK_SHIFT_CONST(16)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_Y_FIELD                        _MK_FIELD_CONST(0xffff, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_Y_SHIFT)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_Y_RANGE                        31:16
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_Y_WOFFSET                      0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_Y_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_Y_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_Y_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0_Y_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0                     _MK_ADDR_CONST(0x443)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_SECURE                      0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_SCR                         0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_WORD_COUNT                  0x1
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_X_NS_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_X_NS_FIELD                  _MK_FIELD_CONST(0xffff, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_X_NS_SHIFT)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_X_NS_RANGE                  15:0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_X_NS_WOFFSET                        0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_X_NS_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_X_NS_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_X_NS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_X_NS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_Y_NS_SHIFT                  _MK_SHIFT_CONST(16)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_Y_NS_FIELD                  _MK_FIELD_CONST(0xffff, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_Y_NS_SHIFT)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_Y_NS_RANGE                  31:16
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_Y_NS_WOFFSET                        0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_Y_NS_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_Y_NS_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_Y_NS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0_Y_NS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0                 _MK_ADDR_CONST(0x446)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_SECURE                  0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_SCR                     0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_WORD_COUNT                      0x1
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_WIDTH_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_WIDTH_FIELD                     _MK_FIELD_CONST(0xffff, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_WIDTH_SHIFT)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_WIDTH_RANGE                     15:0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_WIDTH_WOFFSET                   0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_WIDTH_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_HEIGHT_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_HEIGHT_FIELD                    _MK_FIELD_CONST(0xffff, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_HEIGHT_SHIFT)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_HEIGHT_RANGE                    31:16
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_HEIGHT_WOFFSET                  0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_HEIGHT_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_HEIGHT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_HEIGHT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0_HEIGHT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0                      _MK_ADDR_CONST(0x447)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_SECURE                       0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_SCR                  0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_WORD_COUNT                   0x1
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_WIDTH_NS_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_WIDTH_NS_FIELD                       _MK_FIELD_CONST(0xffff, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_WIDTH_NS_SHIFT)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_WIDTH_NS_RANGE                       15:0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_WIDTH_NS_WOFFSET                     0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_WIDTH_NS_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_WIDTH_NS_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_WIDTH_NS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_WIDTH_NS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_HEIGHT_NS_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_HEIGHT_NS_FIELD                      _MK_FIELD_CONST(0xffff, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_HEIGHT_NS_SHIFT)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_HEIGHT_NS_RANGE                      31:16
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_HEIGHT_NS_WOFFSET                    0x0
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_HEIGHT_NS_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_HEIGHT_NS_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_HEIGHT_NS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0_HEIGHT_NS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_DISP_CURSOR_PIPE_METER_0
#define DC_DISP_CURSOR_PIPE_METER_0                     _MK_ADDR_CONST(0x450)
#define DC_DISP_CURSOR_PIPE_METER_0_SECURE                      0x0
#define DC_DISP_CURSOR_PIPE_METER_0_SCR                         0
#define DC_DISP_CURSOR_PIPE_METER_0_WORD_COUNT                  0x1
#define DC_DISP_CURSOR_PIPE_METER_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_PIPE_METER_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define DC_DISP_CURSOR_PIPE_METER_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_PIPE_METER_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_PIPE_METER_0_READ_MASK                   _MK_MASK_CONST(0xc000ffff)
#define DC_DISP_CURSOR_PIPE_METER_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define DC_DISP_CURSOR_PIPE_METER_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_DISP_CURSOR_PIPE_METER_0_VAL_FIELD                   _MK_FIELD_CONST(0xffff, DC_DISP_CURSOR_PIPE_METER_0_VAL_SHIFT)
#define DC_DISP_CURSOR_PIPE_METER_0_VAL_RANGE                   15:0
#define DC_DISP_CURSOR_PIPE_METER_0_VAL_WOFFSET                 0x0
#define DC_DISP_CURSOR_PIPE_METER_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_PIPE_METER_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define DC_DISP_CURSOR_PIPE_METER_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_PIPE_METER_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_DISP_CURSOR_PIPE_METER_0_STATUS_SHIFT                        _MK_SHIFT_CONST(30)
#define DC_DISP_CURSOR_PIPE_METER_0_STATUS_FIELD                        _MK_FIELD_CONST(0x3, DC_DISP_CURSOR_PIPE_METER_0_STATUS_SHIFT)
#define DC_DISP_CURSOR_PIPE_METER_0_STATUS_RANGE                        31:30
#define DC_DISP_CURSOR_PIPE_METER_0_STATUS_WOFFSET                      0x0
#define DC_DISP_CURSOR_PIPE_METER_0_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_PIPE_METER_0_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_PIPE_METER_0_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_PIPE_METER_0_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_PIPE_METER_0_STATUS_ACTIVE                       _MK_ENUM_CONST(0)
#define DC_DISP_CURSOR_PIPE_METER_0_STATUS_ARMED                        _MK_ENUM_CONST(1)
#define DC_DISP_CURSOR_PIPE_METER_0_STATUS_ASSEMBLY                     _MK_ENUM_CONST(2)


// Register DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0                       _MK_ADDR_CONST(0x451)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_SECURE                        0x0
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_SCR                   0
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_WORD_COUNT                    0x1
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_RESET_VAL                     _MK_MASK_CONST(0x101)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_WGRP_SLOTS_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_WGRP_SLOTS_FIELD                      _MK_FIELD_CONST(0xff, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_WGRP_SLOTS_SHIFT)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_WGRP_SLOTS_RANGE                      7:0
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_WGRP_SLOTS_WOFFSET                    0x0
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_WGRP_SLOTS_DEFAULT                    _MK_MASK_CONST(0x1)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_WGRP_SLOTS_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_WGRP_SLOTS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_WGRP_SLOTS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_CURS_SLOTS_SHIFT                      _MK_SHIFT_CONST(8)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_CURS_SLOTS_FIELD                      _MK_FIELD_CONST(0xff, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_CURS_SLOTS_SHIFT)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_CURS_SLOTS_RANGE                      15:8
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_CURS_SLOTS_WOFFSET                    0x0
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_CURS_SLOTS_DEFAULT                    _MK_MASK_CONST(0x1)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_CURS_SLOTS_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_CURS_SLOTS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0_CURS_SLOTS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_DISP_IHUB_CURS_POOL_CONFIG_0
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0                 _MK_ADDR_CONST(0x452)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_SECURE                  0x0
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_SCR                     0
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_WORD_COUNT                      0x1
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_RESET_VAL                       _MK_MASK_CONST(0x10)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_READ_MASK                       _MK_MASK_CONST(0x8000ffff)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_ENTRIES_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_ENTRIES_FIELD                   _MK_FIELD_CONST(0xffff, DC_DISP_IHUB_CURS_POOL_CONFIG_0_ENTRIES_SHIFT)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_ENTRIES_RANGE                   15:0
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_ENTRIES_WOFFSET                 0x0
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_ENTRIES_DEFAULT                 _MK_MASK_CONST(0x10)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_ENTRIES_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_ENTRIES_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_ENTRIES_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_STATUS_SHIFT                    _MK_SHIFT_CONST(31)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_STATUS_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_IHUB_CURS_POOL_CONFIG_0_STATUS_SHIFT)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_STATUS_RANGE                    31:31
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_STATUS_WOFFSET                  0x0
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_STATUS_DONE                     _MK_ENUM_CONST(0)
#define DC_DISP_IHUB_CURS_POOL_CONFIG_0_STATUS_PENDING                  _MK_ENUM_CONST(1)


// Register DC_DISP_IHUB_CURS_FETCH_METER_0
#define DC_DISP_IHUB_CURS_FETCH_METER_0                 _MK_ADDR_CONST(0x453)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SECURE                  0x0
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SCR                     0
#define DC_DISP_IHUB_CURS_FETCH_METER_0_WORD_COUNT                      0x1
#define DC_DISP_IHUB_CURS_FETCH_METER_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SLOTS_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SLOTS_FIELD                     _MK_FIELD_CONST(0xff, DC_DISP_IHUB_CURS_FETCH_METER_0_SLOTS_SHIFT)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SLOTS_RANGE                     7:0
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SLOTS_WOFFSET                   0x0
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SLOTS_DEFAULT                   _MK_MASK_CONST(0x1)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SLOTS_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SLOTS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_FETCH_METER_0_SLOTS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_DISP_IHUB_CURS_REQ_LIMIT_0
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0                   _MK_ADDR_CONST(0x455)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_SECURE                    0x0
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_SCR                       0
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_WORD_COUNT                        0x1
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_RESET_VAL                         _MK_MASK_CONST(0xfff)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_RESET_MASK                        _MK_MASK_CONST(0xfff)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_READ_MASK                         _MK_MASK_CONST(0xfff)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_WRITE_MASK                        _MK_MASK_CONST(0xfff)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_LIMIT_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_LIMIT_FIELD                       _MK_FIELD_CONST(0xfff, DC_DISP_IHUB_CURS_REQ_LIMIT_0_LIMIT_SHIFT)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_LIMIT_RANGE                       11:0
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_LIMIT_WOFFSET                     0x0
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_LIMIT_DEFAULT                     _MK_MASK_CONST(0xfff)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_LIMIT_DEFAULT_MASK                        _MK_MASK_CONST(0xfff)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_LIMIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_REQ_LIMIT_0_LIMIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0                     _MK_ADDR_CONST(0x456)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_SECURE                      0x0
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_SCR                         0
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_WORD_COUNT                  0x1
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_READ_MASK                   _MK_MASK_CONST(0xfff)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_STATUS_FIELD                        _MK_FIELD_CONST(0xfff, DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_STATUS_SHIFT)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_STATUS_RANGE                        11:0
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_STATUS_WOFFSET                      0x0
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_DISP_IHUB_CURS_STATUS_0
#define DC_DISP_IHUB_CURS_STATUS_0                      _MK_ADDR_CONST(0x457)
#define DC_DISP_IHUB_CURS_STATUS_0_SECURE                       0x0
#define DC_DISP_IHUB_CURS_STATUS_0_SCR                  0
#define DC_DISP_IHUB_CURS_STATUS_0_WORD_COUNT                   0x1
#define DC_DISP_IHUB_CURS_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x3f0000)
#define DC_DISP_IHUB_CURS_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_READ_MASK                    _MK_MASK_CONST(0x803fffff)
#define DC_DISP_IHUB_CURS_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x3f0000)
#define DC_DISP_IHUB_CURS_STATUS_0_ENTRIES_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_IHUB_CURS_STATUS_0_ENTRIES_FIELD                        _MK_FIELD_CONST(0xffff, DC_DISP_IHUB_CURS_STATUS_0_ENTRIES_SHIFT)
#define DC_DISP_IHUB_CURS_STATUS_0_ENTRIES_RANGE                        15:0
#define DC_DISP_IHUB_CURS_STATUS_0_ENTRIES_WOFFSET                      0x0
#define DC_DISP_IHUB_CURS_STATUS_0_ENTRIES_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_ENTRIES_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_ENTRIES_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_ENTRIES_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_SHIFT)
#define DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_RANGE                    16:16
#define DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_WOFFSET                  0x0
#define DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_NO                       _MK_ENUM_CONST(0)
#define DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_YES                      _MK_ENUM_CONST(1)
#define DC_DISP_IHUB_CURS_STATUS_0_DP_FETCH_ORDER_ERR_DETECTED_CLEAR                    _MK_ENUM_CONST(1)

#define DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_SHIFT                    _MK_SHIFT_CONST(17)
#define DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_SHIFT)
#define DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_RANGE                    17:17
#define DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_WOFFSET                  0x0
#define DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_NO                       _MK_ENUM_CONST(0)
#define DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_YES                      _MK_ENUM_CONST(1)
#define DC_DISP_IHUB_CURS_STATUS_0_POOL_NOT_EMPTY_AT_FRAME_END_CLEAR                    _MK_ENUM_CONST(1)

#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_SHIFT                        _MK_SHIFT_CONST(18)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_FIELD                        _MK_FIELD_CONST(0x1, DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_SHIFT)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_RANGE                        18:18
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_WOFFSET                      0x0
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_NO                   _MK_ENUM_CONST(0)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_YES                  _MK_ENUM_CONST(1)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_NOT_IN_SPOOLUP_AT_FRAME_START_CLEAR                        _MK_ENUM_CONST(1)

#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_SHIFT                    _MK_SHIFT_CONST(19)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_SHIFT)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_RANGE                    19:19
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_WOFFSET                  0x0
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_NO                       _MK_ENUM_CONST(0)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_YES                      _MK_ENUM_CONST(1)
#define DC_DISP_IHUB_CURS_STATUS_0_FORMATTER_FIFO_OVERFLOW_ERR_CLEAR                    _MK_ENUM_CONST(1)

#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_SHIFT                       _MK_SHIFT_CONST(20)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_FIELD                       _MK_FIELD_CONST(0x1, DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_SHIFT)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_RANGE                       20:20
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_WOFFSET                     0x0
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_NO                  _MK_ENUM_CONST(0)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_YES                 _MK_ENUM_CONST(1)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_REQUESTS_AT_END_OF_FRAME_CLEAR                       _MK_ENUM_CONST(1)

#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_SHIFT                        _MK_SHIFT_CONST(21)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_FIELD                        _MK_FIELD_CONST(0x1, DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_SHIFT)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_RANGE                        21:21
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_WOFFSET                      0x0
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_NO                   _MK_ENUM_CONST(0)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_YES                  _MK_ENUM_CONST(1)
#define DC_DISP_IHUB_CURS_STATUS_0_PENDING_CREDITS_AT_END_OF_FRAME_CLEAR                        _MK_ENUM_CONST(1)

#define DC_DISP_IHUB_CURS_STATUS_0_STATE_SHIFT                  _MK_SHIFT_CONST(31)
#define DC_DISP_IHUB_CURS_STATUS_0_STATE_FIELD                  _MK_FIELD_CONST(0x1, DC_DISP_IHUB_CURS_STATUS_0_STATE_SHIFT)
#define DC_DISP_IHUB_CURS_STATUS_0_STATE_RANGE                  31:31
#define DC_DISP_IHUB_CURS_STATUS_0_STATE_WOFFSET                        0x0
#define DC_DISP_IHUB_CURS_STATUS_0_STATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_IHUB_CURS_STATUS_0_STATE_IDLE                   _MK_ENUM_CONST(0)
#define DC_DISP_IHUB_CURS_STATUS_0_STATE_ACTIVE                 _MK_ENUM_CONST(1)


// Register DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0                        _MK_ADDR_CONST(0x4c2)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SECURE                         0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SCR                    0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_WORD_COUNT                     0x1
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0xf8ffffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_READ_MASK                      _MK_MASK_CONST(0xf8ffffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xd8ffffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_MAX_SATURATED_PIXELS_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_MAX_SATURATED_PIXELS_FIELD                     _MK_FIELD_CONST(0xffffff, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_MAX_SATURATED_PIXELS_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_MAX_SATURATED_PIXELS_RANGE                     23:0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_MAX_SATURATED_PIXELS_WOFFSET                   0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_MAX_SATURATED_PIXELS_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_MAX_SATURATED_PIXELS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_MAX_SATURATED_PIXELS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_MAX_SATURATED_PIXELS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SD_WINDOW_ENABLE_SHIFT                 _MK_SHIFT_CONST(27)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SD_WINDOW_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SD_WINDOW_ENABLE_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SD_WINDOW_ENABLE_RANGE                 27:27
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SD_WINDOW_ENABLE_WOFFSET                       0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SD_WINDOW_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SD_WINDOW_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SD_WINDOW_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SD_WINDOW_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SD_WINDOW_ENABLE_DISABLE                       _MK_ENUM_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_SD_WINDOW_ENABLE_ENABLE                        _MK_ENUM_CONST(1)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_VID_LUMA_SHIFT                 _MK_SHIFT_CONST(28)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_VID_LUMA_FIELD                 _MK_FIELD_CONST(0x1, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_VID_LUMA_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_VID_LUMA_RANGE                 28:28
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_VID_LUMA_WOFFSET                       0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_VID_LUMA_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_VID_LUMA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_VID_LUMA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_VID_LUMA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_VID_LUMA_DISABLE                       _MK_ENUM_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_VID_LUMA_ENABLE                        _MK_ENUM_CONST(1)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RAM_STATUS_SHIFT                       _MK_SHIFT_CONST(29)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RAM_STATUS_FIELD                       _MK_FIELD_CONST(0x1, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RAM_STATUS_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RAM_STATUS_RANGE                       29:29
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RAM_STATUS_WOFFSET                     0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RAM_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RAM_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RAM_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RAM_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RAM_STATUS_IDLE                        _MK_ENUM_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_RAM_STATUS_BUSY                        _MK_ENUM_CONST(1)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_SHIFT                       _MK_SHIFT_CONST(30)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_FIELD                       _MK_FIELD_CONST(0x1, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_RANGE                       30:30
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_WOFFSET                     0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_DONE                        _MK_ENUM_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_BUSY                        _MK_ENUM_CONST(1)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_START                       _MK_ENUM_CONST(1)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_TRIGGER                     _MK_ENUM_CONST(1)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ADDR_RESET_PENDING                     _MK_ENUM_CONST(1)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ENABLE_SHIFT                   _MK_SHIFT_CONST(31)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ENABLE_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ENABLE_RANGE                   31:31
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ENABLE_WOFFSET                 0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ENABLE_FALSE                   _MK_ENUM_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0_ENABLE_TRUE                    _MK_ENUM_CONST(1)


// Register DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0                   _MK_ADDR_CONST(0x4c3)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_SECURE                    0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_SCR                       0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_WORD_COUNT                        0x1
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_READ_MASK                         _MK_MASK_CONST(0x83ffffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_NUMBER_OF_PIXELS_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_NUMBER_OF_PIXELS_FIELD                    _MK_FIELD_CONST(0x3ffffff, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_NUMBER_OF_PIXELS_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_NUMBER_OF_PIXELS_RANGE                    25:0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_NUMBER_OF_PIXELS_WOFFSET                  0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_NUMBER_OF_PIXELS_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_NUMBER_OF_PIXELS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_NUMBER_OF_PIXELS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_NUMBER_OF_PIXELS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_VALID_SHIFT                       _MK_SHIFT_CONST(31)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_VALID_FIELD                       _MK_FIELD_CONST(0x1, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_VALID_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_VALID_RANGE                       31:31
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_VALID_WOFFSET                     0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_VALID_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_VALID_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_VALID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_VALID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_VALID_NO                  _MK_ENUM_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0_VALID_YES                 _MK_ENUM_CONST(1)


// Register DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0                       _MK_ADDR_CONST(0x4c4)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_SECURE                        0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_SCR                   0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_WORD_COUNT                    0x1
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_NUM_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_NUM_FIELD                     _MK_FIELD_CONST(0xff, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_NUM_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_NUM_RANGE                     7:0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_NUM_WOFFSET                   0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0                     _MK_ADDR_CONST(0x4c5)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_SECURE                      0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_SCR                         0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_WORD_COUNT                  0x1
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_RESET_MASK                  _MK_MASK_CONST(0x80ff00ff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_READ_MASK                   _MK_MASK_CONST(0x80ff00ff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_WRITE_MASK                  _MK_MASK_CONST(0x80ff00ff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_LOWER_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_LOWER_FIELD                 _MK_FIELD_CONST(0xff, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_LOWER_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_LOWER_RANGE                 7:0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_LOWER_WOFFSET                       0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_LOWER_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_LOWER_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_LOWER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_LOWER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_UPPER_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_UPPER_FIELD                 _MK_FIELD_CONST(0xff, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_UPPER_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_UPPER_RANGE                 23:16
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_UPPER_WOFFSET                       0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_UPPER_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_UPPER_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_UPPER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_UPPER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_RANGE                        31:31
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_WOFFSET                      0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_INIT_ENUM                    NO
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_NO                   _MK_ENUM_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0_ENABLE_YES                  _MK_ENUM_CONST(1)


// Register DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0                    _MK_ADDR_CONST(0x4c6)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_SECURE                     0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_SCR                        0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_WORD_COUNT                         0x1
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_RESET_MASK                         _MK_MASK_CONST(0xfff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_READ_MASK                  _MK_MASK_CONST(0xfff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_WRITE_MASK                         _MK_MASK_CONST(0xfff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_R_COEFF_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_R_COEFF_FIELD                      _MK_FIELD_CONST(0xf, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_R_COEFF_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_R_COEFF_RANGE                      3:0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_R_COEFF_WOFFSET                    0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_R_COEFF_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_R_COEFF_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_R_COEFF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_R_COEFF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_G_COEFF_SHIFT                      _MK_SHIFT_CONST(4)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_G_COEFF_FIELD                      _MK_FIELD_CONST(0xf, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_G_COEFF_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_G_COEFF_RANGE                      7:4
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_G_COEFF_WOFFSET                    0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_G_COEFF_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_G_COEFF_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_G_COEFF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_G_COEFF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_B_COEFF_SHIFT                      _MK_SHIFT_CONST(8)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_B_COEFF_FIELD                      _MK_FIELD_CONST(0xf, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_B_COEFF_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_B_COEFF_RANGE                      11:8
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_B_COEFF_WOFFSET                    0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_B_COEFF_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_B_COEFF_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_B_COEFF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0_B_COEFF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0                     _MK_ADDR_CONST(0x4c7)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_SECURE                      0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_SCR                         0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_WORD_COUNT                  0x1
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_RESET_VAL                   _MK_MASK_CONST(0x20000000)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_RESET_MASK                  _MK_MASK_CONST(0xb0000000)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_READ_MASK                   _MK_MASK_CONST(0xf0000000)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf0000000)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_SHIFT                    _MK_SHIFT_CONST(28)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_RANGE                    28:28
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_WOFFSET                  0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_DONE                     _MK_ENUM_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_BUSY                     _MK_ENUM_CONST(1)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_START                    _MK_ENUM_CONST(1)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_PENDING                  _MK_ENUM_CONST(1)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ADDR_RESET_TRIGGER                  _MK_ENUM_CONST(1)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_TIMING_SHIFT                        _MK_SHIFT_CONST(29)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_TIMING_FIELD                        _MK_FIELD_CONST(0x1, DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_TIMING_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_TIMING_RANGE                        29:29
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_TIMING_WOFFSET                      0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_TIMING_DEFAULT                      _MK_MASK_CONST(0x1)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_TIMING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_TIMING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_TIMING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_TIMING_INSTANTLY                    _MK_ENUM_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_TIMING_AT_VBLANK                    _MK_ENUM_CONST(1)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_SHIFT                        _MK_SHIFT_CONST(30)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_FIELD                        _MK_FIELD_CONST(0x1, DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_RANGE                        30:30
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_WOFFSET                      0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_DONE                 _MK_ENUM_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_BUSY                 _MK_ENUM_CONST(1)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_START                        _MK_ENUM_CONST(1)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_PENDING                      _MK_ENUM_CONST(1)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_UPDATE_TRIGGER                      _MK_ENUM_CONST(1)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ENABLE_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ENABLE_RANGE                        31:31
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ENABLE_WOFFSET                      0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ENABLE_FALSE                        _MK_ENUM_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0_ENABLE_TRUE                 _MK_ENUM_CONST(1)


// Register DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0                      _MK_ADDR_CONST(0x4c8)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_SECURE                       0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_SCR                  0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_WORD_COUNT                   0x1
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_VALUE_FIELD                      _MK_FIELD_CONST(0xffff, DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_VALUE_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_VALUE_RANGE                      15:0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_VALUE_WOFFSET                    0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_RSVD_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_RSVD_FIELD                       _MK_FIELD_CONST(0x3, DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_RSVD_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_RSVD_RANGE                       1:0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_RSVD_WOFFSET                     0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_RSVD_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_RSVD_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_RSVD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_RSVD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_FRC_SHIFT                        _MK_SHIFT_CONST(2)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_FRC_FIELD                        _MK_FIELD_CONST(0xfff, DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_FRC_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_FRC_RANGE                        13:2
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_FRC_WOFFSET                      0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_FRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_FRC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_FRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_FRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_INT_SHIFT                        _MK_SHIFT_CONST(14)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_INT_FIELD                        _MK_FIELD_CONST(0x3, DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_INT_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_INT_RANGE                        15:14
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_INT_WOFFSET                      0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_INT_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_INT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_INT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_RED_INT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_VALUE_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_VALUE_FIELD                    _MK_FIELD_CONST(0xffff, DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_VALUE_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_VALUE_RANGE                    31:16
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_VALUE_WOFFSET                  0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_RSVD_SHIFT                     _MK_SHIFT_CONST(16)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_RSVD_FIELD                     _MK_FIELD_CONST(0x3, DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_RSVD_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_RSVD_RANGE                     17:16
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_RSVD_WOFFSET                   0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_RSVD_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_RSVD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_RSVD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_RSVD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_FRC_SHIFT                      _MK_SHIFT_CONST(18)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_FRC_FIELD                      _MK_FIELD_CONST(0xfff, DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_FRC_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_FRC_RANGE                      29:18
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_FRC_WOFFSET                    0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_FRC_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_FRC_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_FRC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_FRC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_INT_SHIFT                      _MK_SHIFT_CONST(30)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_INT_FIELD                      _MK_FIELD_CONST(0x3, DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_INT_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_INT_RANGE                      31:30
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_INT_WOFFSET                    0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_INT_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0_GREEN_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0                    _MK_ADDR_CONST(0x4c9)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_SECURE                     0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_SCR                        0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_WORD_COUNT                         0x1
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_READ_MASK                  _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_VALUE_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_VALUE_FIELD                   _MK_FIELD_CONST(0xffff, DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_VALUE_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_VALUE_RANGE                   15:0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_VALUE_WOFFSET                 0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_VALUE_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_VALUE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_VALUE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_VALUE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_RSVD_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_RSVD_FIELD                    _MK_FIELD_CONST(0x3, DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_RSVD_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_RSVD_RANGE                    1:0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_RSVD_WOFFSET                  0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_RSVD_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_RSVD_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_RSVD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_RSVD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_FRC_SHIFT                     _MK_SHIFT_CONST(2)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_FRC_FIELD                     _MK_FIELD_CONST(0xfff, DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_FRC_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_FRC_RANGE                     13:2
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_FRC_WOFFSET                   0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_FRC_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_FRC_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_FRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_FRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_INT_SHIFT                     _MK_SHIFT_CONST(14)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_INT_FIELD                     _MK_FIELD_CONST(0x3, DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_INT_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_INT_RANGE                     15:14
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_INT_WOFFSET                   0x0
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_INT_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0_BLUE_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0                     _MK_ADDR_CONST(0x4cb)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_SECURE                      0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_SCR                         0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_WORD_COUNT                  0x1
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_H_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_H_FIELD                     _MK_FIELD_CONST(0xffff, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_H_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_H_RANGE                     15:0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_H_WOFFSET                   0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_H_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_H_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_H_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_H_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_V_SHIFT                     _MK_SHIFT_CONST(16)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_V_FIELD                     _MK_FIELD_CONST(0xffff, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_V_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_V_RANGE                     31:16
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_V_WOFFSET                   0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_V_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_V_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_V_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0_V_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0                 _MK_ADDR_CONST(0x4cc)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_SECURE                  0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_SCR                     0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_WORD_COUNT                      0x1
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_WIDTH_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_WIDTH_FIELD                     _MK_FIELD_CONST(0xffff, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_WIDTH_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_WIDTH_RANGE                     15:0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_WIDTH_WOFFSET                   0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_WIDTH_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_HEIGHT_SHIFT                    _MK_SHIFT_CONST(16)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_HEIGHT_FIELD                    _MK_FIELD_CONST(0xffff, DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_HEIGHT_SHIFT)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_HEIGHT_RANGE                    31:16
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_HEIGHT_WOFFSET                  0x0
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_HEIGHT_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_HEIGHT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_HEIGHT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0_HEIGHT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_DISP_BLEND_BACKGROUND_COLOR_0
#define DC_DISP_BLEND_BACKGROUND_COLOR_0                        _MK_ADDR_CONST(0x4e4)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_SECURE                         0x0
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_SCR                    0
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_WORD_COUNT                     0x1
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_RESET_VAL                      _MK_MASK_CONST(0xff000000)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_FIELD                        _MK_FIELD_CONST(0xff, DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_SHIFT)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_RANGE                        7:0
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_WOFFSET                      0x0
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_SHIFT                      _MK_SHIFT_CONST(8)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_FIELD                      _MK_FIELD_CONST(0xff, DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_SHIFT)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_RANGE                      15:8
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_WOFFSET                    0x0
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_SHIFT                       _MK_SHIFT_CONST(16)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_FIELD                       _MK_FIELD_CONST(0xff, DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_SHIFT)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_RANGE                       23:16
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_WOFFSET                     0x0
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_SHIFT                      _MK_SHIFT_CONST(24)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_FIELD                      _MK_FIELD_CONST(0xff, DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_SHIFT)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_RANGE                      31:24
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_WOFFSET                    0x0
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_DEFAULT                    _MK_MASK_CONST(0xff)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_DISP_INTERLACE_CONTROL_0
#define DC_DISP_INTERLACE_CONTROL_0                     _MK_ADDR_CONST(0x4e5)
#define DC_DISP_INTERLACE_CONTROL_0_SECURE                      0x0
#define DC_DISP_INTERLACE_CONTROL_0_SCR                         0
#define DC_DISP_INTERLACE_CONTROL_0_WORD_COUNT                  0x1
#define DC_DISP_INTERLACE_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define DC_DISP_INTERLACE_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define DC_DISP_INTERLACE_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_SHIFT)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_RANGE                      0:0
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_WOFFSET                    0x0
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_SHIFT                       _MK_SHIFT_CONST(1)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_FIELD                       _MK_FIELD_CONST(0x1, DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_SHIFT)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_RANGE                       1:1
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_WOFFSET                     0x0
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_FIELD1                      _MK_ENUM_CONST(0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_FIELD2                      _MK_ENUM_CONST(1)

#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_SHIFT                      _MK_SHIFT_CONST(2)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_FIELD                      _MK_FIELD_CONST(0x1, DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_SHIFT)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_RANGE                      2:2
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_WOFFSET                    0x0
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_FIELD1                     _MK_ENUM_CONST(0)
#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_FIELD2                     _MK_ENUM_CONST(1)


// Register DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0                   _MK_ADDR_CONST(0x4e7)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_SECURE                    0x0
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_SCR                       0
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_WORD_COUNT                        0x1
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_RESET_VAL                         _MK_MASK_CONST(0x10000)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_RESET_MASK                        _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_READ_MASK                         _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_FIELD                 _MK_FIELD_CONST(0x7fff, DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_SHIFT)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_RANGE                 30:16
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_WOFFSET                       0x0
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_DEFAULT                       _MK_MASK_CONST(0x1)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0                   _MK_ADDR_CONST(0x4e8)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_SECURE                    0x0
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_SCR                       0
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_WORD_COUNT                        0x1
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_RESET_VAL                         _MK_MASK_CONST(0x10000)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_RESET_MASK                        _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_READ_MASK                         _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_SHIFT                 _MK_SHIFT_CONST(16)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_FIELD                 _MK_FIELD_CONST(0x7fff, DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_SHIFT)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_RANGE                 30:16
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_WOFFSET                       0x0
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_DEFAULT                       _MK_MASK_CONST(0x1)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0                  _MK_ADDR_CONST(0x4e9)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_SECURE                   0x0
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_SCR                      0
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_WORD_COUNT                       0x1
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_RESET_VAL                        _MK_MASK_CONST(0x10000)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_RESET_MASK                       _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_READ_MASK                        _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_WRITE_MASK                       _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_SHIFT                       _MK_SHIFT_CONST(16)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_FIELD                       _MK_FIELD_CONST(0x7fff, DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_SHIFT)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_RANGE                       30:16
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_WOFFSET                     0x0
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_DEFAULT                     _MK_MASK_CONST(0x1)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_DEFAULT_MASK                        _MK_MASK_CONST(0x7fff)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0                  _MK_ADDR_CONST(0x4ea)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_SECURE                   0x0
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_SCR                      0
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_WORD_COUNT                       0x1
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_RESET_VAL                        _MK_MASK_CONST(0x80000)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_RESET_MASK                       _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_READ_MASK                        _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_WRITE_MASK                       _MK_MASK_CONST(0x7fff0000)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_SHIFT                       _MK_SHIFT_CONST(16)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_FIELD                       _MK_FIELD_CONST(0x7fff, DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_SHIFT)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_RANGE                       30:16
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_WOFFSET                     0x0
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_DEFAULT                     _MK_MASK_CONST(0x8)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_DEFAULT_MASK                        _MK_MASK_CONST(0x7fff)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_DISP_CURSOR_START_ADDR_HI_0
#define DC_DISP_CURSOR_START_ADDR_HI_0                  _MK_ADDR_CONST(0x4ec)
#define DC_DISP_CURSOR_START_ADDR_HI_0_SECURE                   0x0
#define DC_DISP_CURSOR_START_ADDR_HI_0_SCR                      0
#define DC_DISP_CURSOR_START_ADDR_HI_0_WORD_COUNT                       0x1
#define DC_DISP_CURSOR_START_ADDR_HI_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_HI_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define DC_DISP_CURSOR_START_ADDR_HI_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_HI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_HI_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define DC_DISP_CURSOR_START_ADDR_HI_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_FIELD                       _MK_FIELD_CONST(0xff, DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_SHIFT)
#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_RANGE                       7:0
#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_WOFFSET                     0x0
#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register DC_DISP_CURSOR_START_ADDR_HI_NS_0
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0                       _MK_ADDR_CONST(0x4ed)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_SECURE                        0x0
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_SCR                   0
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_WORD_COUNT                    0x1
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_FIELD                 _MK_FIELD_CONST(0xff, DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_SHIFT)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_RANGE                 7:0
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_WOFFSET                       0x0
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_DISP_CSC2_CONTROL_0
#define DC_DISP_CSC2_CONTROL_0                  _MK_ADDR_CONST(0x4ef)
#define DC_DISP_CSC2_CONTROL_0_SECURE                   0x0
#define DC_DISP_CSC2_CONTROL_0_SCR                      0
#define DC_DISP_CSC2_CONTROL_0_WORD_COUNT                       0x1
#define DC_DISP_CSC2_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_DISP_CSC2_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define DC_DISP_CSC2_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_CSC2_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_CSC2_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define DC_DISP_CSC2_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_FIELD                        _MK_FIELD_CONST(0x3, DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_SHIFT)
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_RANGE                        1:0
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_WOFFSET                      0x0
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_INIT_ENUM                    RGB
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_RGB                  _MK_ENUM_CONST(0)
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_YCBCR709                     _MK_ENUM_CONST(1)
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_YCBCR601                     _MK_ENUM_CONST(2)
#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_YCBCR2020                    _MK_ENUM_CONST(3)

#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_SHIFT                    _MK_SHIFT_CONST(2)
#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_SHIFT)
#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_RANGE                    2:2
#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_WOFFSET                  0x0
#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_DISABLE                  _MK_ENUM_CONST(0)
#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_ENABLE                   _MK_ENUM_CONST(1)


// Register DC_DISP_BLEND_CURSOR_CONTROL_0
#define DC_DISP_BLEND_CURSOR_CONTROL_0                  _MK_ADDR_CONST(0x4f1)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_SECURE                   0x0
#define DC_DISP_BLEND_CURSOR_CONTROL_0_SCR                      0
#define DC_DISP_BLEND_CURSOR_CONTROL_0_WORD_COUNT                       0x1
#define DC_DISP_BLEND_CURSOR_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0xff)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x20303ff)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x20303ff)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x20303ff)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_FIELD                       _MK_FIELD_CONST(0xff, DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_SHIFT)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_RANGE                       7:0
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_WOFFSET                     0x0
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_DEFAULT                     _MK_MASK_CONST(0xff)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_SHIFT                     _MK_SHIFT_CONST(8)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_FIELD                     _MK_FIELD_CONST(0x3, DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_SHIFT)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_RANGE                     9:8
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_WOFFSET                   0x0
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_K1                        _MK_ENUM_CONST(0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_K1_TIMES_SRC                      _MK_ENUM_CONST(1)

#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_SHIFT                     _MK_SHIFT_CONST(16)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_FIELD                     _MK_FIELD_CONST(0x3, DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_SHIFT)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_RANGE                     17:16
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_WOFFSET                   0x0
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_ZERO                      _MK_ENUM_CONST(0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_K1                        _MK_ENUM_CONST(1)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_NEG_K1_TIMES_SRC                  _MK_ENUM_CONST(2)

#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_SHIFT                    _MK_SHIFT_CONST(25)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_SHIFT)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_RANGE                    25:25
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_WOFFSET                  0x0
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_INIT_ENUM                        BLEND
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_BLEND                    _MK_ENUM_CONST(0)
#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_COMPOSITION_MODE_XOR                      _MK_ENUM_CONST(1)


// Register DC_DISP_CURSOR_CGCTL_0
#define DC_DISP_CURSOR_CGCTL_0                  _MK_ADDR_CONST(0x4f2)
#define DC_DISP_CURSOR_CGCTL_0_SECURE                   0x0
#define DC_DISP_CURSOR_CGCTL_0_SCR                      0
#define DC_DISP_CURSOR_CGCTL_0_WORD_COUNT                       0x1
#define DC_DISP_CURSOR_CGCTL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_CGCTL_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_DISP_CURSOR_CGCTL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_CGCTL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_CGCTL_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_DISP_CURSOR_CGCTL_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_DISP_CURSOR_CGCTL_0_VAL_SHIFT                        _MK_SHIFT_CONST(0)
#define DC_DISP_CURSOR_CGCTL_0_VAL_FIELD                        _MK_FIELD_CONST(0xffffffff, DC_DISP_CURSOR_CGCTL_0_VAL_SHIFT)
#define DC_DISP_CURSOR_CGCTL_0_VAL_RANGE                        31:0
#define DC_DISP_CURSOR_CGCTL_0_VAL_WOFFSET                      0x0
#define DC_DISP_CURSOR_CGCTL_0_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_CGCTL_0_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define DC_DISP_CURSOR_CGCTL_0_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_CURSOR_CGCTL_0_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register DC_DISP_POSTCOMP_HEAD_CGCTL_0
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0                   _MK_ADDR_CONST(0x4f3)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_SECURE                    0x0
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_SCR                       0
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_WORD_COUNT                        0x1
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_VAL_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_VAL_FIELD                 _MK_FIELD_CONST(0xffffffff, DC_DISP_POSTCOMP_HEAD_CGCTL_0_VAL_SHIFT)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_VAL_RANGE                 31:0
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_VAL_WOFFSET                       0x0
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_POSTCOMP_HEAD_CGCTL_0_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0                        _MK_ADDR_CONST(0x4f4)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_SECURE                         0x0
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_SCR                    0
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_WORD_COUNT                     0x1
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_FIELD                       _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_SHIFT)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_RANGE                       0:0
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_WOFFSET                     0x0
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_INIT_ENUM                   DISABLE
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_HEAD_GATE_OVERRIDE_ENABLE                      _MK_ENUM_CONST(1)

#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(1)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_FIELD                 _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_SHIFT)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_RANGE                 1:1
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_WOFFSET                       0x0
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_INIT_ENUM                     DISABLE
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_DISABLE                       _MK_ENUM_CONST(0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_DISPCLK_RG_GATE_OVERRIDE_ENABLE                        _MK_ENUM_CONST(1)

#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(2)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_FIELD                       _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_SHIFT)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_RANGE                       2:2
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_WOFFSET                     0x0
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_INIT_ENUM                   DISABLE
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_DISABLE                     _MK_ENUM_CONST(0)
#define DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0_PCLK_GATE_OVERRIDE_ENABLE                      _MK_ENUM_CONST(1)


// Register DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0                     _MK_ADDR_CONST(0x4f5)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_SECURE                      0x0
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_SCR                         0
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_WORD_COUNT                  0x1
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_SHIFT)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_RANGE                    0:0
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_WOFFSET                  0x0
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_INIT_ENUM                        DISABLE
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_DISABLE                  _MK_ENUM_CONST(0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_DISPCLK_COMP_GATE_OVERRIDE_ENABLE                   _MK_ENUM_CONST(1)

#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(1)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_SHIFT)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_RANGE                  1:1
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_WOFFSET                        0x0
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_INIT_ENUM                      DISABLE
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_DISABLE                        _MK_ENUM_CONST(0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_HUBCLK_GATE_OVERRIDE_ENABLE                 _MK_ENUM_CONST(1)

#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(2)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_FIELD                    _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_SHIFT)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_RANGE                    2:2
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_WOFFSET                  0x0
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_INIT_ENUM                        DISABLE
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_DISABLE                  _MK_ENUM_CONST(0)
#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CLK_OVR_ON_ENABLE                   _MK_ENUM_CONST(1)


// Register DC_DISP_DISPLAY_DBG_TIMING_0
#define DC_DISP_DISPLAY_DBG_TIMING_0                    _MK_ADDR_CONST(0x4f6)
#define DC_DISP_DISPLAY_DBG_TIMING_0_SECURE                     0x0
#define DC_DISP_DISPLAY_DBG_TIMING_0_SCR                        0
#define DC_DISP_DISPLAY_DBG_TIMING_0_WORD_COUNT                         0x1
#define DC_DISP_DISPLAY_DBG_TIMING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_RESET_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_READ_MASK                  _MK_MASK_CONST(0x9fff9fff)
#define DC_DISP_DISPLAY_DBG_TIMING_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_FIELD                      _MK_FIELD_CONST(0x1fff, DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_SHIFT)
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_RANGE                      12:0
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_WOFFSET                    0x0
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_SHIFT                      _MK_SHIFT_CONST(15)
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_FIELD                      _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_SHIFT)
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_RANGE                      15:15
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_WOFFSET                    0x0
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_SHIFT                      _MK_SHIFT_CONST(16)
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_FIELD                      _MK_FIELD_CONST(0x1fff, DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_SHIFT)
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_RANGE                      28:16
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_WOFFSET                    0x0
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_SHIFT                      _MK_SHIFT_CONST(31)
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_FIELD                      _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_SHIFT)
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_RANGE                      31:31
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_WOFFSET                    0x0
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register DC_DISP_COM_CDE_CG_SW_OVR_0
#define DC_DISP_COM_CDE_CG_SW_OVR_0                     _MK_ADDR_CONST(0x4f8)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_SECURE                      0x0
#define DC_DISP_COM_CDE_CG_SW_OVR_0_SCR                         0
#define DC_DISP_COM_CDE_CG_SW_OVR_0_WORD_COUNT                  0x1
#define DC_DISP_COM_CDE_CG_SW_OVR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_COM_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_COM_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, DC_DISP_COM_CDE_CG_SW_OVR_0_COM_OVERRIDE_SHIFT)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_COM_OVERRIDE_RANGE                  0:0
#define DC_DISP_COM_CDE_CG_SW_OVR_0_COM_OVERRIDE_WOFFSET                        0x0
#define DC_DISP_COM_CDE_CG_SW_OVR_0_COM_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_COM_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_COM_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_COM_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_COM_OVERRIDE_OFF                    _MK_ENUM_CONST(0)
#define DC_DISP_COM_CDE_CG_SW_OVR_0_COM_OVERRIDE_ON                     _MK_ENUM_CONST(1)


// Register DC_DISP_COM_CDE_PM_CONTROL_0
#define DC_DISP_COM_CDE_PM_CONTROL_0                    _MK_ADDR_CONST(0x4f9)
#define DC_DISP_COM_CDE_PM_CONTROL_0_SECURE                     0x0
#define DC_DISP_COM_CDE_PM_CONTROL_0_SCR                        0
#define DC_DISP_COM_CDE_PM_CONTROL_0_WORD_COUNT                         0x1
#define DC_DISP_COM_CDE_PM_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0xff0f)
#define DC_DISP_COM_CDE_PM_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0xff0f)
#define DC_DISP_COM_CDE_PM_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0xff0f)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_SHIFT                       _MK_SHIFT_CONST(0)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_FIELD                       _MK_FIELD_CONST(0xf, DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_SHIFT)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_RANGE                       3:0
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_WOFFSET                     0x0
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_CTB_LOOKUP_HIT                      _MK_ENUM_CONST(0)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_CTB_LOOKUP_MISS                     _MK_ENUM_CONST(1)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_UNCOMP_1TO1                 _MK_ENUM_CONST(2)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_ARITHMETIC_2TO1                     _MK_ENUM_CONST(3)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_REDUCTION_4TO1                      _MK_ENUM_CONST(4)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_REDUCTION_8TO1                      _MK_ENUM_CONST(5)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_ZBC                 _MK_ENUM_CONST(6)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_CSR_FETCH_64B                       _MK_ENUM_CONST(7)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_CSR_FETCH_32B_BP                    _MK_ENUM_CONST(8)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_CTB_FETCH_64B                       _MK_ENUM_CONST(9)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_PIXEL_FETCH_64B                     _MK_ENUM_CONST(10)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_PIXEL_FETCH_32B                     _MK_ENUM_CONST(11)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_CTB_READS_SAMPLED                   _MK_ENUM_CONST(12)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_CTB_READ_RSP_LATENCY                        _MK_ENUM_CONST(13)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_PIXEL_READS_SAMPLED                 _MK_ENUM_CONST(14)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SIGNAL_SEL_PIXEL_READ_RSP_LATENCY                      _MK_ENUM_CONST(15)

#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SURFACE_SEL_SHIFT                      _MK_SHIFT_CONST(8)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SURFACE_SEL_FIELD                      _MK_FIELD_CONST(0xff, DC_DISP_COM_CDE_PM_CONTROL_0_COM_SURFACE_SEL_SHIFT)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SURFACE_SEL_RANGE                      15:8
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SURFACE_SEL_WOFFSET                    0x0
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SURFACE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SURFACE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SURFACE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SURFACE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_CONTROL_0_COM_SURFACE_SEL_ALL_SLOTS                  _MK_ENUM_CONST(0)


// Register DC_DISP_COM_CDE_PM_SIGNALS_0
#define DC_DISP_COM_CDE_PM_SIGNALS_0                    _MK_ADDR_CONST(0x4fa)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_SECURE                     0x0
#define DC_DISP_COM_CDE_PM_SIGNALS_0_SCR                        0
#define DC_DISP_COM_CDE_PM_SIGNALS_0_WORD_COUNT                         0x1
#define DC_DISP_COM_CDE_PM_SIGNALS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_COM_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_COM_VALUE_FIELD                    _MK_FIELD_CONST(0xffffffff, DC_DISP_COM_CDE_PM_SIGNALS_0_COM_VALUE_SHIFT)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_COM_VALUE_RANGE                    31:0
#define DC_DISP_COM_CDE_PM_SIGNALS_0_COM_VALUE_WOFFSET                  0x0
#define DC_DISP_COM_CDE_PM_SIGNALS_0_COM_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_COM_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_COM_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_PM_SIGNALS_0_COM_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register DC_DISP_COM_CDE_DEBUG_CONTROL_0
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0                 _MK_ADDR_CONST(0x4fb)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_SECURE                  0x0
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_SCR                     0
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_WORD_COUNT                      0x1
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0xf)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0xf)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_COM_SEL_SHIFT                   _MK_SHIFT_CONST(0)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_COM_SEL_FIELD                   _MK_FIELD_CONST(0xf, DC_DISP_COM_CDE_DEBUG_CONTROL_0_COM_SEL_SHIFT)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_COM_SEL_RANGE                   3:0
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_COM_SEL_WOFFSET                 0x0
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_COM_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_COM_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_COM_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_DEBUG_CONTROL_0_COM_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register DC_DISP_COM_CDE_DEBUG_VAL_0
#define DC_DISP_COM_CDE_DEBUG_VAL_0                     _MK_ADDR_CONST(0x4fc)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_SECURE                      0x0
#define DC_DISP_COM_CDE_DEBUG_VAL_0_SCR                         0
#define DC_DISP_COM_CDE_DEBUG_VAL_0_WORD_COUNT                  0x1
#define DC_DISP_COM_CDE_DEBUG_VAL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_COM_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_COM_VALUE_FIELD                     _MK_FIELD_CONST(0xffffffff, DC_DISP_COM_CDE_DEBUG_VAL_0_COM_VALUE_SHIFT)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_COM_VALUE_RANGE                     31:0
#define DC_DISP_COM_CDE_DEBUG_VAL_0_COM_VALUE_WOFFSET                   0x0
#define DC_DISP_COM_CDE_DEBUG_VAL_0_COM_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_COM_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_COM_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_DEBUG_VAL_0_COM_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register DC_DISP_COM_CDE_SPARE_0
#define DC_DISP_COM_CDE_SPARE_0                 _MK_ADDR_CONST(0x4fd)
#define DC_DISP_COM_CDE_SPARE_0_SECURE                  0x0
#define DC_DISP_COM_CDE_SPARE_0_SCR                     0
#define DC_DISP_COM_CDE_SPARE_0_WORD_COUNT                      0x1
#define DC_DISP_COM_CDE_SPARE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_SPARE_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COM_CDE_SPARE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_SPARE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_SPARE_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COM_CDE_SPARE_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COM_CDE_SPARE_0_COM_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define DC_DISP_COM_CDE_SPARE_0_COM_VALUE_FIELD                 _MK_FIELD_CONST(0xffffffff, DC_DISP_COM_CDE_SPARE_0_COM_VALUE_SHIFT)
#define DC_DISP_COM_CDE_SPARE_0_COM_VALUE_RANGE                 31:0
#define DC_DISP_COM_CDE_SPARE_0_COM_VALUE_WOFFSET                       0x0
#define DC_DISP_COM_CDE_SPARE_0_COM_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_SPARE_0_COM_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define DC_DISP_COM_CDE_SPARE_0_COM_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define DC_DISP_COM_CDE_SPARE_0_COM_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 1278 [0x4fe]

// Reserved address 1279 [0x4ff]

// Reserved address 1280 [0x500]

// Reserved address 1281 [0x501]

// Reserved address 1282 [0x502]

//
// REGISTER LIST
//
#define LIST_ARDISPLAY_REGS(_op_) \
_op_(DC_CMD_GENERAL_INCR_SYNCPT_0) \
_op_(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0) \
_op_(DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0) \
_op_(DC_CMD_WIN_A_INCR_SYNCPT_0) \
_op_(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0) \
_op_(DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0) \
_op_(DC_CMD_WIN_B_INCR_SYNCPT_0) \
_op_(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0) \
_op_(DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0) \
_op_(DC_CMD_WIN_C_INCR_SYNCPT_0) \
_op_(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0) \
_op_(DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0) \
_op_(DC_CMD_CONT_SYNCPT_VSYNC_0) \
_op_(DC_CMD_CTXSW_NEXT_0) \
_op_(DC_CMD_CTXSW_0) \
_op_(DC_CMD_DISPLAY_COMMAND_OPTION0_0) \
_op_(DC_CMD_DISPLAY_COMMAND_0) \
_op_(DC_CMD_REG_PFE_HEAD_DEBUG_0) \
_op_(DC_CMD_INT_STATUS_0) \
_op_(DC_CMD_INT_MASK_0) \
_op_(DC_CMD_INT_ENABLE_0) \
_op_(DC_CMD_INT_TYPE_0) \
_op_(DC_CMD_INT_POLARITY_0) \
_op_(DC_CMD_STATE_ACCESS_0) \
_op_(DC_CMD_STATE_CONTROL_0) \
_op_(DC_CMD_DISPLAY_WINDOW_HEADER_0) \
_op_(DC_CMD_WIN_T_STATE_CONTROL_0) \
_op_(DC_CMD_SECURE_CONTROL_0) \
_op_(DC_CMD_REG_ACCESS_CONTROL_0) \
_op_(DC_CMD_REG_WINDOW_ACCESS_VIOLATION_INFO_0) \
_op_(DC_CMD_REG_PFE_DEBUG_0) \
_op_(DC_CMD_REG_PFE_DEBUG_CHN_MASK_0) \
_op_(DC_CMD_WIN_D_INCR_SYNCPT_0) \
_op_(DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0) \
_op_(DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0) \
_op_(DC_CMD_POSTCOMP_HEAD_CAPA_0) \
_op_(DC_CMD_POSTCOMP_HEAD_CAPB_0) \
_op_(DC_CMD_POSTCOMP_HEAD_CAPC_0) \
_op_(DC_CMD_POSTCOMP_HEAD_CAPD_0) \
_op_(DC_CMD_POSTCOMP_HEAD_CAPE_0) \
_op_(DC_CMD_POSTCOMP_HEAD_CAPF_0) \
_op_(DC_CMD_IHUB_COMMON_CAPA_0) \
_op_(DC_CMD_IHUB_COMMON_CAPB_0) \
_op_(DC_CMD_IHUB_COMMON_CAPC_0) \
_op_(DC_CMD_IHUB_COMMON_CAPD_0) \
_op_(DC_CMD_IHUB_COMMON_CONFIG_0) \
_op_(DC_CMD_IHUB_COMMON_MISC_CTL_0) \
_op_(DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0) \
_op_(DC_CMD_IHUB_COMMON_SPARE_0_0) \
_op_(DC_CMD_IHUB_COMMON_SPARE_1_0) \
_op_(DC_CMD_IHUB_COMMON_CGCTL_0) \
_op_(DC_CMD_IHUB_COMMON_DEBUG_SPARE_0_0) \
_op_(DC_CMD_IHUB_COMMON_DEBUG_SPARE_1_0) \
_op_(DC_CMD_IHUB_COMMON_RO_SPARE_0_0) \
_op_(DC_CMD_IHUB_COMMON_RO_SPARE_1_0) \
_op_(DC_CMD_WIN_E_INCR_SYNCPT_0) \
_op_(DC_CMD_WIN_E_INCR_SYNCPT_CNTRL_0) \
_op_(DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0) \
_op_(DC_CMD_WIN_F_INCR_SYNCPT_0) \
_op_(DC_CMD_WIN_F_INCR_SYNCPT_CNTRL_0) \
_op_(DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0) \
_op_(DC_CMD_SECURE_INT_STATUS_0) \
_op_(DC_CMD_SECURE_INT_MASK_0) \
_op_(DC_CMD_SECURE_INT_ENABLE_0) \
_op_(DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0) \
_op_(DC_CMD_SECURE_ACCESS_VIOLATION_INFO2_0) \
_op_(DC_CMD_SECURE_ACCESS_VIOLATION_INFO3_0) \
_op_(DC_CMD_SECURE_LOCKDOWN_0) \
_op_(DC_CMD_SECURE_LOCKDOWN) \
_op_(DC_CMD_SECURE_LOCKDOWN_1) \
_op_(DC_CMD_SECURE_LOCKDOWN_2) \
_op_(DC_CMD_SECURE_LOCKDOWN_3) \
_op_(DC_CMD_SECURE_LOCKDOWN_4) \
_op_(DC_CMD_SECURE_LOCKDOWN_5) \
_op_(DC_CMD_SECURE_LOCKDOWN_6) \
_op_(DC_CMD_SECURE_LOCKDOWN_7) \
_op_(DC_CMD_STREAMID_HEAD_0) \
_op_(DC_CMD_RSB_HEAD_0) \
_op_(DC_CMD_DISPLAY_MONITOR_ADDR_0) \
_op_(DC_CMD_DISPLAY_MONITOR_DATA_0) \
_op_(DC_CMD_HSM_INT_STATUS_0) \
_op_(DC_CMD_HSM_INT_MASK_0) \
_op_(DC_CMD_HSM_INT_ENABLE_0) \
_op_(DC_CMD_HSM_INT_TYPE_0) \
_op_(DC_CMD_HSM_INT_POLARITY_0) \
_op_(DC_COM_CRC_CONTROL_0) \
_op_(DC_COM_CORE_HEAD_SET_CRC_CONTROL_0) \
_op_(DC_COM_SCRATCH_REGISTER_A_0) \
_op_(DC_COM_SCRATCH_REGISTER_B_0) \
_op_(DC_COM_COMP_CRCA_0) \
_op_(DC_COM_COMP_CRCB_0) \
_op_(DC_COM_RG_CRCA_0) \
_op_(DC_COM_RG_CRCB_0) \
_op_(DC_COM_DSC_TOP_CTL_0) \
_op_(DC_COM_DSC_DELAY_0) \
_op_(DC_COM_DSC_COMMON_CTL_0) \
_op_(DC_COM_DSC_SLICE_INFO_0) \
_op_(DC_COM_DSC_RC_DELAY_INFO_0) \
_op_(DC_COM_DSC_RC_SCALE_INFO_0) \
_op_(DC_COM_DSC_RC_SCALE_INFO_2_0) \
_op_(DC_COM_DSC_RC_BPGOFF_INFO_0) \
_op_(DC_COM_DSC_RC_OFFSET_INFO_0) \
_op_(DC_COM_DSC_RC_FLATNESS_INFO_0) \
_op_(DC_COM_DSC_RC_PARAM_SET_0) \
_op_(DC_COM_DSC_RC_BUF_THRESH0_0) \
_op_(DC_COM_DSC_RC_BUF_THRESH1_0) \
_op_(DC_COM_DSC_RC_BUF_THRESH2_0) \
_op_(DC_COM_DSC_RC_BUF_THRESH3_0) \
_op_(DC_COM_DSC_RC_RANGE_CFG0_0) \
_op_(DC_COM_DSC_RC_RANGE_CFG1_0) \
_op_(DC_COM_DSC_RC_RANGE_CFG2_0) \
_op_(DC_COM_DSC_RC_RANGE_CFG3_0) \
_op_(DC_COM_DSC_RC_RANGE_CFG4_0) \
_op_(DC_COM_DSC_RC_RANGE_CFG5_0) \
_op_(DC_COM_DSC_RC_RANGE_CFG6_0) \
_op_(DC_COM_DSC_RC_RANGE_CFG7_0) \
_op_(DC_COM_DSC_UNIT_SET_0) \
_op_(DC_COM_DSC_STATUS0_0) \
_op_(DC_COM_DSC_STATUS1_0) \
_op_(DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0) \
_op_(DC_COM_POSTCOMP_HEAD_SPARE0_0) \
_op_(DC_COM_RG_STATUS_0) \
_op_(DC_COM_RG_IN_LOADV_COUNTER_0) \
_op_(DC_COM_RG_DCLK_0) \
_op_(DC_COM_RG_UNDERFLOW_0) \
_op_(DC_COM_RG_DPCA_0) \
_op_(DC_COM_RG_DPCB_0) \
_op_(DC_COM_RG_VPCA_0) \
_op_(DC_COM_RG_VPCB_0) \
_op_(DC_COM_RG_SNAPSHOT_RASTER_0) \
_op_(DC_COM_RG_DEBUG_0) \
_op_(DC_COM_RG_TEST_0) \
_op_(DC_COM_RG_UNDERFLOW_PIXEL_0) \
_op_(DC_COM_RG_SPARE0_0) \
_op_(DC_COM_CURSOR_LOADV_COUNTER_0) \
_op_(DC_COM_CURSOR_SPARE0_0) \
_op_(DC_COM_CURSOR_PIX_RCVD_0) \
_op_(DC_COM_CURSOR_DFLT_RGB_COLOR_0) \
_op_(DC_COM_COMP_CURSOR_CGCTL_0) \
_op_(DC_COM_CURSOR_DEBUG0_0) \
_op_(DC_COM_CURSOR_DEBUG1_0) \
_op_(DC_COM_COMP_CURSOR_DEBUG0_0) \
_op_(DC_COM_IHUB_CURS_ASR_CTLA_0) \
_op_(DC_COM_IHUB_CURS_ASR_CTLB_0) \
_op_(DC_COM_IHUB_CURS_ASR_CTLC_0) \
_op_(DC_COM_IHUB_CURS_OCC_0) \
_op_(DC_COM_IHUB_CURS_MEMACC_0) \
_op_(DC_COM_IHUB_CURS_LATENCY_CTLA_0) \
_op_(DC_COM_IHUB_CURS_LATENCY_CTLB_0) \
_op_(DC_COM_IHUB_CURS_REQ_SENT_0) \
_op_(DC_COM_IHUB_CURS_RSP_RCVD_0) \
_op_(DC_COM_IHUB_CURS_REQ_0) \
_op_(DC_COM_COMP_SPARE0_0) \
_op_(DC_COM_RG_REGION_CRC_0) \
_op_(DC_COM_RG_REGION_CRC_CONTROL_0) \
_op_(DC_COM_RG_REGION_CRC_POINT_IN_0_0) \
_op_(DC_COM_RG_REGION_CRC_POINT_IN_1_0) \
_op_(DC_COM_RG_REGION_CRC_POINT_IN_2_0) \
_op_(DC_COM_RG_REGION_CRC_POINT_IN_3_0) \
_op_(DC_COM_RG_REGION_CRC_POINT_IN_4_0) \
_op_(DC_COM_RG_REGION_CRC_POINT_IN_5_0) \
_op_(DC_COM_RG_REGION_CRC_POINT_IN_6_0) \
_op_(DC_COM_RG_REGION_CRC_POINT_IN_7_0) \
_op_(DC_COM_RG_REGION_CRC_POINT_IN_8_0) \
_op_(DC_COM_RG_REGION_CRC_SIZE_0_0) \
_op_(DC_COM_RG_REGION_CRC_SIZE_1_0) \
_op_(DC_COM_RG_REGION_CRC_SIZE_2_0) \
_op_(DC_COM_RG_REGION_CRC_SIZE_3_0) \
_op_(DC_COM_RG_REGION_CRC_SIZE_4_0) \
_op_(DC_COM_RG_REGION_CRC_SIZE_5_0) \
_op_(DC_COM_RG_REGION_CRC_SIZE_6_0) \
_op_(DC_COM_RG_REGION_CRC_SIZE_7_0) \
_op_(DC_COM_RG_REGION_CRC_SIZE_8_0) \
_op_(DC_COM_RG_REGION_GOLDEN_CRC_0_0) \
_op_(DC_COM_RG_REGION_GOLDEN_CRC_1_0) \
_op_(DC_COM_RG_REGION_GOLDEN_CRC_2_0) \
_op_(DC_COM_RG_REGION_GOLDEN_CRC_3_0) \
_op_(DC_COM_RG_REGION_GOLDEN_CRC_4_0) \
_op_(DC_COM_RG_REGION_GOLDEN_CRC_5_0) \
_op_(DC_COM_RG_REGION_GOLDEN_CRC_6_0) \
_op_(DC_COM_RG_REGION_GOLDEN_CRC_7_0) \
_op_(DC_COM_RG_REGION_GOLDEN_CRC_8_0) \
_op_(DC_DISP_DISP_SIGNAL_OPTIONS0_0) \
_op_(DC_DISP_DISP_WIN_OPTIONS_0) \
_op_(DC_DISP_CORE_SOR_SET_CONTROL_0) \
_op_(DC_DISP_CORE_SOR1_SET_CONTROL_0) \
_op_(DC_DISP_CORE_DSI_SET_CONTROL_0) \
_op_(DC_DISP_SYNC_WIDTH_0) \
_op_(DC_DISP_BACK_PORCH_0) \
_op_(DC_DISP_DISP_ACTIVE_0) \
_op_(DC_DISP_FRONT_PORCH_0) \
_op_(DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0) \
_op_(DC_DISP_RG_RASTER_V_EXTEND_FRONT_PORCH_0) \
_op_(DC_DISP_RG_RASTER_EXTEND_0) \
_op_(DC_DISP_RG_ELV_0) \
_op_(DC_DISP_CORE_HEAD_SET_STALL_LOCK_0) \
_op_(DC_DISP_CORE_HEAD_SET_DISPLAY_RATE_0) \
_op_(DC_DISP_RG_UNSTALL_SPOOLUP_0) \
_op_(DC_DISP_RG_STOP_FETCH_0) \
_op_(DC_DISP_START_FETCH_DLY_0) \
_op_(DC_DISP_V_PULSE2_POSITION_A_0) \
_op_(DC_DISP_V_PULSE3_POSITION_A_0) \
_op_(DC_DISP_DISP_COLOR_CONTROL_0) \
_op_(DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT_0) \
_op_(DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_0) \
_op_(DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI_0) \
_op_(DC_DISP_CORE_HEAD_SET_PROCAMP_0) \
_op_(DC_DISP_COLOR_KEY0_LOWER0_0) \
_op_(DC_DISP_COLOR_KEY0_LOWER1_0) \
_op_(DC_DISP_COLOR_KEY0_UPPER0_0) \
_op_(DC_DISP_COLOR_KEY0_UPPER1_0) \
_op_(DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0) \
_op_(DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0) \
_op_(DC_DISP_CURSOR_START_ADDR_0) \
_op_(DC_DISP_CURSOR_START_ADDR_NS_0) \
_op_(DC_DISP_CURSOR_POSITION_0) \
_op_(DC_DISP_CURSOR_POSITION_NS_0) \
_op_(DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_0) \
_op_(DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0) \
_op_(DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0) \
_op_(DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0) \
_op_(DC_DISP_CURSOR_PIPE_METER_0) \
_op_(DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER_0) \
_op_(DC_DISP_IHUB_CURS_POOL_CONFIG_0) \
_op_(DC_DISP_IHUB_CURS_FETCH_METER_0) \
_op_(DC_DISP_IHUB_CURS_REQ_LIMIT_0) \
_op_(DC_DISP_IHUB_CURS_DEBUG_REQ_LIMIT_0) \
_op_(DC_DISP_IHUB_CURS_STATUS_0) \
_op_(DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0) \
_op_(DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_LUMINANCE_0) \
_op_(DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_OVER_SATURATED_BUCKET_0) \
_op_(DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_BUCKET_INTERRUPT_BOUNDS_0) \
_op_(DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_VID_LUMA_0) \
_op_(DC_DISP_RG_SMARTDIMMER3_GAIN_CTRL_0) \
_op_(DC_DISP_RG_SMARTDIMMER3_GAIN_R_G_0) \
_op_(DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0) \
_op_(DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0) \
_op_(DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0) \
_op_(DC_DISP_BLEND_BACKGROUND_COLOR_0) \
_op_(DC_DISP_INTERLACE_CONTROL_0) \
_op_(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0) \
_op_(DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0) \
_op_(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0) \
_op_(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0) \
_op_(DC_DISP_CURSOR_START_ADDR_HI_0) \
_op_(DC_DISP_CURSOR_START_ADDR_HI_NS_0) \
_op_(DC_DISP_CSC2_CONTROL_0) \
_op_(DC_DISP_BLEND_CURSOR_CONTROL_0) \
_op_(DC_DISP_CURSOR_CGCTL_0) \
_op_(DC_DISP_POSTCOMP_HEAD_CGCTL_0) \
_op_(DC_DISP_DISPLAY_HEAD_CLK_GATE_OVERRIDE_0) \
_op_(DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0) \
_op_(DC_DISP_DISPLAY_DBG_TIMING_0) \
_op_(DC_DISP_COM_CDE_CG_SW_OVR_0) \
_op_(DC_DISP_COM_CDE_PM_CONTROL_0) \
_op_(DC_DISP_COM_CDE_PM_SIGNALS_0) \
_op_(DC_DISP_COM_CDE_DEBUG_CONTROL_0) \
_op_(DC_DISP_COM_CDE_DEBUG_VAL_0) \
_op_(DC_DISP_COM_CDE_SPARE_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_DC_CMD     0x00000000
#define BASE_ADDRESS_DC_COM     0x00000300
#define BASE_ADDRESS_DC_DISP    0x00000400

//
// ARDISPLAY REGISTER BANKS
//

#define DC_CMD0_FIRST_REG 0x0000 // DC_CMD_GENERAL_INCR_SYNCPT_0
#define DC_CMD0_LAST_REG 0x0002 // DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0
#define DC_CMD1_FIRST_REG 0x0008 // DC_CMD_WIN_A_INCR_SYNCPT_0
#define DC_CMD1_LAST_REG 0x000a // DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0
#define DC_CMD2_FIRST_REG 0x0010 // DC_CMD_WIN_B_INCR_SYNCPT_0
#define DC_CMD2_LAST_REG 0x0012 // DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0
#define DC_CMD3_FIRST_REG 0x0018 // DC_CMD_WIN_C_INCR_SYNCPT_0
#define DC_CMD3_LAST_REG 0x001a // DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0
#define DC_CMD4_FIRST_REG 0x0028 // DC_CMD_CONT_SYNCPT_VSYNC_0
#define DC_CMD4_LAST_REG 0x0028 // DC_CMD_CONT_SYNCPT_VSYNC_0
#define DC_CMD5_FIRST_REG 0x002f // DC_CMD_CTXSW_NEXT_0
#define DC_CMD5_LAST_REG 0x0033 // DC_CMD_REG_PFE_HEAD_DEBUG_0
#define DC_CMD6_FIRST_REG 0x0037 // DC_CMD_INT_STATUS_0
#define DC_CMD6_LAST_REG 0x003b // DC_CMD_INT_POLARITY_0
#define DC_CMD7_FIRST_REG 0x0040 // DC_CMD_STATE_ACCESS_0
#define DC_CMD7_LAST_REG 0x0042 // DC_CMD_DISPLAY_WINDOW_HEADER_0
#define DC_CMD8_FIRST_REG 0x0044 // DC_CMD_WIN_T_STATE_CONTROL_0
#define DC_CMD8_LAST_REG 0x0049 // DC_CMD_REG_PFE_DEBUG_CHN_MASK_0
#define DC_CMD9_FIRST_REG 0x004c // DC_CMD_WIN_D_INCR_SYNCPT_0
#define DC_CMD9_LAST_REG 0x004e // DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0
#define DC_CMD10_FIRST_REG 0x0050 // DC_CMD_POSTCOMP_HEAD_CAPA_0
#define DC_CMD10_LAST_REG 0x0055 // DC_CMD_POSTCOMP_HEAD_CAPF_0
#define DC_CMD11_FIRST_REG 0x0060 // DC_CMD_IHUB_COMMON_CAPA_0
#define DC_CMD11_LAST_REG 0x0063 // DC_CMD_IHUB_COMMON_CAPD_0
#define DC_CMD12_FIRST_REG 0x0067 // DC_CMD_IHUB_COMMON_CONFIG_0
#define DC_CMD12_LAST_REG 0x0069 // DC_CMD_IHUB_COMMON_MISC_EMERGENCY_0
#define DC_CMD13_FIRST_REG 0x0070 // DC_CMD_IHUB_COMMON_SPARE_0_0
#define DC_CMD13_LAST_REG 0x0076 // DC_CMD_IHUB_COMMON_RO_SPARE_1_0
#define DC_CMD14_FIRST_REG 0x0078 // DC_CMD_WIN_E_INCR_SYNCPT_0
#define DC_CMD14_LAST_REG 0x007a // DC_CMD_WIN_E_INCR_SYNCPT_ERROR_0
#define DC_CMD15_FIRST_REG 0x0080 // DC_CMD_WIN_F_INCR_SYNCPT_0
#define DC_CMD15_LAST_REG 0x0082 // DC_CMD_WIN_F_INCR_SYNCPT_ERROR_0
#define DC_CMD16_FIRST_REG 0x0088 // DC_CMD_SECURE_INT_STATUS_0
#define DC_CMD16_LAST_REG 0x008a // DC_CMD_SECURE_INT_ENABLE_0
#define DC_CMD17_FIRST_REG 0x008d // DC_CMD_SECURE_ACCESS_VIOLATION_INFO1_0
#define DC_CMD17_LAST_REG 0x0097 // DC_CMD_SECURE_LOCKDOWN_7
#define DC_CMD18_FIRST_REG 0x00a0 // DC_CMD_STREAMID_HEAD_0
#define DC_CMD18_LAST_REG 0x00a1 // DC_CMD_RSB_HEAD_0
#define DC_CMD19_FIRST_REG 0x00b0 // DC_CMD_DISPLAY_MONITOR_ADDR_0
#define DC_CMD19_LAST_REG 0x00b1 // DC_CMD_DISPLAY_MONITOR_DATA_0
#define DC_CMD20_FIRST_REG 0x00c0 // DC_CMD_HSM_INT_STATUS_0
#define DC_CMD20_LAST_REG 0x00c4 // DC_CMD_HSM_INT_POLARITY_0
#define DC_COM0_FIRST_REG 0x0300 // DC_COM_CRC_CONTROL_0
#define DC_COM0_LAST_REG 0x0301 // DC_COM_CORE_HEAD_SET_CRC_CONTROL_0
#define DC_COM1_FIRST_REG 0x0325 // DC_COM_SCRATCH_REGISTER_A_0
#define DC_COM1_LAST_REG 0x0326 // DC_COM_SCRATCH_REGISTER_B_0
#define DC_COM2_FIRST_REG 0x032a // DC_COM_COMP_CRCA_0
#define DC_COM2_LAST_REG 0x032d // DC_COM_RG_CRCB_0
#define DC_COM3_FIRST_REG 0x033e // DC_COM_DSC_TOP_CTL_0
#define DC_COM3_LAST_REG 0x0355 // DC_COM_DSC_UNIT_SET_0
#define DC_COM4_FIRST_REG 0x0358 // DC_COM_DSC_STATUS0_0
#define DC_COM4_LAST_REG 0x0359 // DC_COM_DSC_STATUS1_0
#define DC_COM5_FIRST_REG 0x035f // DC_COM_POSTCOMP_HEAD_LOADV_COUNTER_0
#define DC_COM5_LAST_REG 0x0360 // DC_COM_POSTCOMP_HEAD_SPARE0_0
#define DC_COM6_FIRST_REG 0x0362 // DC_COM_RG_STATUS_0
#define DC_COM6_LAST_REG 0x036d // DC_COM_RG_UNDERFLOW_PIXEL_0
#define DC_COM7_FIRST_REG 0x036f // DC_COM_RG_SPARE0_0
#define DC_COM7_LAST_REG 0x037a // DC_COM_IHUB_CURS_ASR_CTLC_0
#define DC_COM8_FIRST_REG 0x037e // DC_COM_IHUB_CURS_OCC_0
#define DC_COM8_LAST_REG 0x037e // DC_COM_IHUB_CURS_OCC_0
#define DC_COM9_FIRST_REG 0x0381 // DC_COM_IHUB_CURS_MEMACC_0
#define DC_COM9_LAST_REG 0x0387 // DC_COM_COMP_SPARE0_0
#define DC_COM10_FIRST_REG 0x03a2 // DC_COM_RG_REGION_CRC_0
#define DC_COM10_LAST_REG 0x03be // DC_COM_RG_REGION_GOLDEN_CRC_8_0
#define DC_DISP0_FIRST_REG 0x0400 // DC_DISP_DISP_SIGNAL_OPTIONS0_0
#define DC_DISP0_LAST_REG 0x0400 // DC_DISP_DISP_SIGNAL_OPTIONS0_0
#define DC_DISP1_FIRST_REG 0x0402 // DC_DISP_DISP_WIN_OPTIONS_0
#define DC_DISP1_LAST_REG 0x0405 // DC_DISP_CORE_DSI_SET_CONTROL_0
#define DC_DISP2_FIRST_REG 0x0407 // DC_DISP_SYNC_WIDTH_0
#define DC_DISP2_LAST_REG 0x040a // DC_DISP_FRONT_PORCH_0
#define DC_DISP3_FIRST_REG 0x0410 // DC_DISP_RG_RASTER_V_EXTEND_BACK_PORCH_0
#define DC_DISP3_LAST_REG 0x0418 // DC_DISP_START_FETCH_DLY_0
#define DC_DISP4_FIRST_REG 0x0423 // DC_DISP_V_PULSE2_POSITION_A_0
#define DC_DISP4_LAST_REG 0x0423 // DC_DISP_V_PULSE2_POSITION_A_0
#define DC_DISP5_FIRST_REG 0x0425 // DC_DISP_V_PULSE3_POSITION_A_0
#define DC_DISP5_LAST_REG 0x0425 // DC_DISP_V_PULSE3_POSITION_A_0
#define DC_DISP6_FIRST_REG 0x0430 // DC_DISP_DISP_COLOR_CONTROL_0
#define DC_DISP6_LAST_REG 0x0434 // DC_DISP_CORE_HEAD_SET_PROCAMP_0
#define DC_DISP7_FIRST_REG 0x0436 // DC_DISP_COLOR_KEY0_LOWER0_0
#define DC_DISP7_LAST_REG 0x0439 // DC_DISP_COLOR_KEY0_UPPER1_0
#define DC_DISP8_FIRST_REG 0x043b // DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_0
#define DC_DISP8_LAST_REG 0x043c // DC_DISP_CORE_HEAD_SET_CONTROL_CURSOR_NS_0
#define DC_DISP9_FIRST_REG 0x043e // DC_DISP_CURSOR_START_ADDR_0
#define DC_DISP9_LAST_REG 0x0443 // DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR_NS_0
#define DC_DISP10_FIRST_REG 0x0446 // DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_0
#define DC_DISP10_LAST_REG 0x0447 // DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR_NS_0
#define DC_DISP11_FIRST_REG 0x0450 // DC_DISP_CURSOR_PIPE_METER_0
#define DC_DISP11_LAST_REG 0x0453 // DC_DISP_IHUB_CURS_FETCH_METER_0
#define DC_DISP12_FIRST_REG 0x0455 // DC_DISP_IHUB_CURS_REQ_LIMIT_0
#define DC_DISP12_LAST_REG 0x0457 // DC_DISP_IHUB_CURS_STATUS_0
#define DC_DISP13_FIRST_REG 0x04c2 // DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_CTRL_0
#define DC_DISP13_LAST_REG 0x04c9 // DC_DISP_RG_SMARTDIMMER3_GAIN_B_INC_0
#define DC_DISP14_FIRST_REG 0x04cb // DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_POSITION_0
#define DC_DISP14_LAST_REG 0x04cc // DC_DISP_RG_SMARTDIMMER3_HISTOGRAM_WINDOW_SIZE_0
#define DC_DISP15_FIRST_REG 0x04e4 // DC_DISP_BLEND_BACKGROUND_COLOR_0
#define DC_DISP15_LAST_REG 0x04e5 // DC_DISP_INTERLACE_CONTROL_0
#define DC_DISP16_FIRST_REG 0x04e7 // DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0
#define DC_DISP16_LAST_REG 0x04ea // DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0
#define DC_DISP17_FIRST_REG 0x04ec // DC_DISP_CURSOR_START_ADDR_HI_0
#define DC_DISP17_LAST_REG 0x04ed // DC_DISP_CURSOR_START_ADDR_HI_NS_0
#define DC_DISP18_FIRST_REG 0x04ef // DC_DISP_CSC2_CONTROL_0
#define DC_DISP18_LAST_REG 0x04ef // DC_DISP_CSC2_CONTROL_0
#define DC_DISP19_FIRST_REG 0x04f1 // DC_DISP_BLEND_CURSOR_CONTROL_0
#define DC_DISP19_LAST_REG 0x04f6 // DC_DISP_DISPLAY_DBG_TIMING_0
#define DC_DISP20_FIRST_REG 0x04f8 // DC_DISP_COM_CDE_CG_SW_OVR_0
#define DC_DISP20_LAST_REG 0x04fd // DC_DISP_COM_CDE_SPARE_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARDISPLAY_H_INC_
