//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARPADCTL_EDP_H_INC_
#define ___ARPADCTL_EDP_H_INC_
#define NV_MOBILE_ARPADCTL_EDP_H_UNIT_OF_OFFSET 1B


// Register PADCTL_EDP_SOC_GPIO50_0
#define PADCTL_EDP_SOC_GPIO50_0                 _MK_ADDR_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_SECURE                  0x0
#define PADCTL_EDP_SOC_GPIO50_0_DUAL                    0x0
#define PADCTL_EDP_SOC_GPIO50_0_SCR                     SCR_SOC_GPIO50_0
#define PADCTL_EDP_SOC_GPIO50_0_WORD_COUNT                      0x1
#define PADCTL_EDP_SOC_GPIO50_0_RESET_VAL                       _MK_MASK_CONST(0x454)
#define PADCTL_EDP_SOC_GPIO50_0_RESET_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO50_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_READ_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO50_0_WRITE_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO50_0_PM_SHIFT                        _MK_SHIFT_CONST(0)
#define PADCTL_EDP_SOC_GPIO50_0_PM_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO50_0_PM_SHIFT)
#define PADCTL_EDP_SOC_GPIO50_0_PM_RANGE                        1:0
#define PADCTL_EDP_SOC_GPIO50_0_PM_WOFFSET                      0x0
#define PADCTL_EDP_SOC_GPIO50_0_PM_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_PM_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO50_0_PM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_PM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_PM_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_PM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_PM_INIT_ENUM                    RSVD0
#define PADCTL_EDP_SOC_GPIO50_0_PM_RSVD0                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO50_0_PM_DCA                  _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO50_0_PM_RSVD2                        _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO50_0_PM_RSVD3                        _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_RANGE                       10:10
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_WOFFSET                     0x0
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_INIT_ENUM                   SFIO
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_GPIO                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO50_0_GPIO_SF_SEL_SFIO                        _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_SHIFT                  _MK_SHIFT_CONST(4)
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO50_0_TRISTATE_SHIFT)
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_RANGE                  4:4
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_WOFFSET                        0x0
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_INIT_ENUM                      TRISTATE
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_PASSTHROUGH                    _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO50_0_TRISTATE_TRISTATE                       _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO50_0_PUPD_SHIFT                      _MK_SHIFT_CONST(2)
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_FIELD                      _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO50_0_PUPD_SHIFT)
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_RANGE                      3:2
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_WOFFSET                    0x0
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_INIT_ENUM                  PULL_DOWN
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_NONE                       _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_PULL_UP                    _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO50_0_PUPD_RSVD                       _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_SHIFT                   _MK_SHIFT_CONST(6)
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO50_0_E_INPUT_SHIFT)
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_RANGE                   6:6
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_INIT_ENUM                       ENABLE
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO50_0_E_INPUT_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_SHIFT                    _MK_SHIFT_CONST(8)
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO50_0_E_LPDR_SHIFT)
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_RANGE                    8:8
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_WOFFSET                  0x0
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_INIT_ENUM                        DISABLE
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO50_0_E_LPDR_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_SHIFT                   _MK_SHIFT_CONST(12)
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_SHIFT)
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_RANGE                   12:12
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_INIT_ENUM                       DISABLE
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO50_0_E_SCHMT_ENABLE                  _MK_ENUM_CONST(1)


// Register PADCTL_EDP_CFG2TMC_SOC_GPIO50_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0                 _MK_ADDR_CONST(0x4)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_SECURE                  0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_DUAL                    0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_SCR                     SCR_SOC_GPIO50_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_WORD_COUNT                      0x1
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_RESET_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_READ_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_WRITE_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVDN_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVDN_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVDN_RANGE                     16:12
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVDN_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVDN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVDN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVDN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVDN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVUP_SHIFT                     _MK_SHIFT_CONST(20)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVUP_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVUP_RANGE                     24:20
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVUP_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVUP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO50_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_SOC_GPIO51_0
#define PADCTL_EDP_SOC_GPIO51_0                 _MK_ADDR_CONST(0x8)
#define PADCTL_EDP_SOC_GPIO51_0_SECURE                  0x0
#define PADCTL_EDP_SOC_GPIO51_0_DUAL                    0x0
#define PADCTL_EDP_SOC_GPIO51_0_SCR                     SCR_SOC_GPIO51_0
#define PADCTL_EDP_SOC_GPIO51_0_WORD_COUNT                      0x1
#define PADCTL_EDP_SOC_GPIO51_0_RESET_VAL                       _MK_MASK_CONST(0x454)
#define PADCTL_EDP_SOC_GPIO51_0_RESET_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO51_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_READ_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO51_0_WRITE_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO51_0_PM_SHIFT                        _MK_SHIFT_CONST(0)
#define PADCTL_EDP_SOC_GPIO51_0_PM_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO51_0_PM_SHIFT)
#define PADCTL_EDP_SOC_GPIO51_0_PM_RANGE                        1:0
#define PADCTL_EDP_SOC_GPIO51_0_PM_WOFFSET                      0x0
#define PADCTL_EDP_SOC_GPIO51_0_PM_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_PM_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO51_0_PM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_PM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_PM_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_PM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_PM_INIT_ENUM                    RSVD0
#define PADCTL_EDP_SOC_GPIO51_0_PM_RSVD0                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO51_0_PM_DCA                  _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO51_0_PM_RSVD2                        _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO51_0_PM_RSVD3                        _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_RANGE                       10:10
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_WOFFSET                     0x0
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_INIT_ENUM                   SFIO
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_GPIO                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO51_0_GPIO_SF_SEL_SFIO                        _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_SHIFT                  _MK_SHIFT_CONST(4)
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO51_0_TRISTATE_SHIFT)
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_RANGE                  4:4
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_WOFFSET                        0x0
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_INIT_ENUM                      TRISTATE
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_PASSTHROUGH                    _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO51_0_TRISTATE_TRISTATE                       _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO51_0_PUPD_SHIFT                      _MK_SHIFT_CONST(2)
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_FIELD                      _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO51_0_PUPD_SHIFT)
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_RANGE                      3:2
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_WOFFSET                    0x0
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_INIT_ENUM                  PULL_DOWN
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_NONE                       _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_PULL_UP                    _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO51_0_PUPD_RSVD                       _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_SHIFT                   _MK_SHIFT_CONST(6)
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO51_0_E_INPUT_SHIFT)
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_RANGE                   6:6
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_INIT_ENUM                       ENABLE
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO51_0_E_INPUT_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_SHIFT                    _MK_SHIFT_CONST(8)
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO51_0_E_LPDR_SHIFT)
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_RANGE                    8:8
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_WOFFSET                  0x0
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_INIT_ENUM                        DISABLE
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO51_0_E_LPDR_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_SHIFT                   _MK_SHIFT_CONST(12)
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_SHIFT)
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_RANGE                   12:12
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_INIT_ENUM                       DISABLE
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO51_0_E_SCHMT_ENABLE                  _MK_ENUM_CONST(1)


// Register PADCTL_EDP_CFG2TMC_SOC_GPIO51_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0                 _MK_ADDR_CONST(0xc)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_SECURE                  0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_DUAL                    0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_SCR                     SCR_SOC_GPIO51_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_WORD_COUNT                      0x1
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_RESET_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_READ_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_WRITE_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVDN_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVDN_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVDN_RANGE                     16:12
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVDN_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVDN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVDN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVDN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVDN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVUP_SHIFT                     _MK_SHIFT_CONST(20)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVUP_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVUP_RANGE                     24:20
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVUP_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVUP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO51_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_SOC_GPIO52_0
#define PADCTL_EDP_SOC_GPIO52_0                 _MK_ADDR_CONST(0x10)
#define PADCTL_EDP_SOC_GPIO52_0_SECURE                  0x0
#define PADCTL_EDP_SOC_GPIO52_0_DUAL                    0x0
#define PADCTL_EDP_SOC_GPIO52_0_SCR                     SCR_SOC_GPIO52_0
#define PADCTL_EDP_SOC_GPIO52_0_WORD_COUNT                      0x1
#define PADCTL_EDP_SOC_GPIO52_0_RESET_VAL                       _MK_MASK_CONST(0x454)
#define PADCTL_EDP_SOC_GPIO52_0_RESET_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO52_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_READ_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO52_0_WRITE_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO52_0_PM_SHIFT                        _MK_SHIFT_CONST(0)
#define PADCTL_EDP_SOC_GPIO52_0_PM_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO52_0_PM_SHIFT)
#define PADCTL_EDP_SOC_GPIO52_0_PM_RANGE                        1:0
#define PADCTL_EDP_SOC_GPIO52_0_PM_WOFFSET                      0x0
#define PADCTL_EDP_SOC_GPIO52_0_PM_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_PM_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO52_0_PM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_PM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_PM_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_PM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_PM_INIT_ENUM                    RSVD0
#define PADCTL_EDP_SOC_GPIO52_0_PM_RSVD0                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO52_0_PM_DCB                  _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO52_0_PM_DGPU                 _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO52_0_PM_RSVD3                        _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_RANGE                       10:10
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_WOFFSET                     0x0
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_INIT_ENUM                   SFIO
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_GPIO                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO52_0_GPIO_SF_SEL_SFIO                        _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_SHIFT                  _MK_SHIFT_CONST(4)
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO52_0_TRISTATE_SHIFT)
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_RANGE                  4:4
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_WOFFSET                        0x0
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_INIT_ENUM                      TRISTATE
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_PASSTHROUGH                    _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO52_0_TRISTATE_TRISTATE                       _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO52_0_PUPD_SHIFT                      _MK_SHIFT_CONST(2)
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_FIELD                      _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO52_0_PUPD_SHIFT)
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_RANGE                      3:2
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_WOFFSET                    0x0
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_INIT_ENUM                  PULL_DOWN
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_NONE                       _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_PULL_UP                    _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO52_0_PUPD_RSVD                       _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_SHIFT                   _MK_SHIFT_CONST(6)
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO52_0_E_INPUT_SHIFT)
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_RANGE                   6:6
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_INIT_ENUM                       ENABLE
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO52_0_E_INPUT_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_SHIFT                    _MK_SHIFT_CONST(8)
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO52_0_E_LPDR_SHIFT)
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_RANGE                    8:8
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_WOFFSET                  0x0
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_INIT_ENUM                        DISABLE
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO52_0_E_LPDR_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_SHIFT                   _MK_SHIFT_CONST(12)
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_SHIFT)
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_RANGE                   12:12
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_INIT_ENUM                       DISABLE
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO52_0_E_SCHMT_ENABLE                  _MK_ENUM_CONST(1)


// Register PADCTL_EDP_CFG2TMC_SOC_GPIO52_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0                 _MK_ADDR_CONST(0x14)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_SECURE                  0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_DUAL                    0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_SCR                     SCR_SOC_GPIO52_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_WORD_COUNT                      0x1
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_RESET_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_READ_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_WRITE_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVDN_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVDN_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVDN_RANGE                     16:12
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVDN_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVDN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVDN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVDN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVDN_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVUP_SHIFT                     _MK_SHIFT_CONST(20)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVUP_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVUP_RANGE                     24:20
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVUP_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVUP_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO52_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_SOC_GPIO53_0
#define PADCTL_EDP_SOC_GPIO53_0                 _MK_ADDR_CONST(0x18)
#define PADCTL_EDP_SOC_GPIO53_0_SECURE                  0x0
#define PADCTL_EDP_SOC_GPIO53_0_DUAL                    0x0
#define PADCTL_EDP_SOC_GPIO53_0_SCR                     SCR_SOC_GPIO53_0
#define PADCTL_EDP_SOC_GPIO53_0_WORD_COUNT                      0x1
#define PADCTL_EDP_SOC_GPIO53_0_RESET_VAL                       _MK_MASK_CONST(0x454)
#define PADCTL_EDP_SOC_GPIO53_0_RESET_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO53_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_READ_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO53_0_WRITE_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO53_0_PM_SHIFT                        _MK_SHIFT_CONST(0)
#define PADCTL_EDP_SOC_GPIO53_0_PM_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO53_0_PM_SHIFT)
#define PADCTL_EDP_SOC_GPIO53_0_PM_RANGE                        1:0
#define PADCTL_EDP_SOC_GPIO53_0_PM_WOFFSET                      0x0
#define PADCTL_EDP_SOC_GPIO53_0_PM_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_PM_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO53_0_PM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_PM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_PM_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_PM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_PM_INIT_ENUM                    RSVD0
#define PADCTL_EDP_SOC_GPIO53_0_PM_RSVD0                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO53_0_PM_DCB                  _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO53_0_PM_RSVD2                        _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO53_0_PM_ISTCTRL                      _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_RANGE                       10:10
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_WOFFSET                     0x0
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_INIT_ENUM                   SFIO
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_GPIO                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO53_0_GPIO_SF_SEL_SFIO                        _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_SHIFT                  _MK_SHIFT_CONST(4)
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO53_0_TRISTATE_SHIFT)
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_RANGE                  4:4
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_WOFFSET                        0x0
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_INIT_ENUM                      TRISTATE
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_PASSTHROUGH                    _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO53_0_TRISTATE_TRISTATE                       _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO53_0_PUPD_SHIFT                      _MK_SHIFT_CONST(2)
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_FIELD                      _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO53_0_PUPD_SHIFT)
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_RANGE                      3:2
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_WOFFSET                    0x0
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_INIT_ENUM                  PULL_DOWN
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_NONE                       _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_PULL_UP                    _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO53_0_PUPD_RSVD                       _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_SHIFT                   _MK_SHIFT_CONST(6)
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO53_0_E_INPUT_SHIFT)
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_RANGE                   6:6
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_INIT_ENUM                       ENABLE
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO53_0_E_INPUT_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_SHIFT                    _MK_SHIFT_CONST(8)
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO53_0_E_LPDR_SHIFT)
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_RANGE                    8:8
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_WOFFSET                  0x0
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_INIT_ENUM                        DISABLE
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO53_0_E_LPDR_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_SHIFT                   _MK_SHIFT_CONST(12)
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_SHIFT)
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_RANGE                   12:12
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_INIT_ENUM                       DISABLE
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO53_0_E_SCHMT_ENABLE                  _MK_ENUM_CONST(1)


// Register PADCTL_EDP_CFG2TMC_SOC_GPIO53_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0                 _MK_ADDR_CONST(0x1c)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_SECURE                  0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_DUAL                    0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_SCR                     SCR_SOC_GPIO53_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_WORD_COUNT                      0x1
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_RESET_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_READ_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_WRITE_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVDN_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVDN_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVDN_RANGE                     16:12
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVDN_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVDN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVDN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVDN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVDN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVUP_SHIFT                     _MK_SHIFT_CONST(20)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVUP_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVUP_RANGE                     24:20
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVUP_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVUP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO53_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_SOC_GPIO54_0
#define PADCTL_EDP_SOC_GPIO54_0                 _MK_ADDR_CONST(0x20)
#define PADCTL_EDP_SOC_GPIO54_0_SECURE                  0x0
#define PADCTL_EDP_SOC_GPIO54_0_DUAL                    0x0
#define PADCTL_EDP_SOC_GPIO54_0_SCR                     SCR_SOC_GPIO54_0
#define PADCTL_EDP_SOC_GPIO54_0_WORD_COUNT                      0x1
#define PADCTL_EDP_SOC_GPIO54_0_RESET_VAL                       _MK_MASK_CONST(0x454)
#define PADCTL_EDP_SOC_GPIO54_0_RESET_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO54_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_READ_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO54_0_WRITE_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO54_0_PM_SHIFT                        _MK_SHIFT_CONST(0)
#define PADCTL_EDP_SOC_GPIO54_0_PM_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO54_0_PM_SHIFT)
#define PADCTL_EDP_SOC_GPIO54_0_PM_RANGE                        1:0
#define PADCTL_EDP_SOC_GPIO54_0_PM_WOFFSET                      0x0
#define PADCTL_EDP_SOC_GPIO54_0_PM_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_PM_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO54_0_PM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_PM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_PM_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_PM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_PM_INIT_ENUM                    RSVD0
#define PADCTL_EDP_SOC_GPIO54_0_PM_RSVD0                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO54_0_PM_SDMMC3                       _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO54_0_PM_GP                   _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO54_0_PM_RSVD3                        _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_RANGE                       10:10
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_WOFFSET                     0x0
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_INIT_ENUM                   SFIO
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_GPIO                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO54_0_GPIO_SF_SEL_SFIO                        _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_SHIFT                  _MK_SHIFT_CONST(4)
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO54_0_TRISTATE_SHIFT)
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_RANGE                  4:4
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_WOFFSET                        0x0
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_INIT_ENUM                      TRISTATE
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_PASSTHROUGH                    _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO54_0_TRISTATE_TRISTATE                       _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO54_0_PUPD_SHIFT                      _MK_SHIFT_CONST(2)
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_FIELD                      _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO54_0_PUPD_SHIFT)
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_RANGE                      3:2
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_WOFFSET                    0x0
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_INIT_ENUM                  PULL_DOWN
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_NONE                       _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_PULL_UP                    _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO54_0_PUPD_RSVD                       _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_SHIFT                   _MK_SHIFT_CONST(6)
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO54_0_E_INPUT_SHIFT)
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_RANGE                   6:6
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_INIT_ENUM                       ENABLE
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO54_0_E_INPUT_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_SHIFT                    _MK_SHIFT_CONST(8)
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO54_0_E_LPDR_SHIFT)
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_RANGE                    8:8
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_WOFFSET                  0x0
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_INIT_ENUM                        DISABLE
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO54_0_E_LPDR_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_SHIFT                   _MK_SHIFT_CONST(12)
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_SHIFT)
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_RANGE                   12:12
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_INIT_ENUM                       DISABLE
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO54_0_E_SCHMT_ENABLE                  _MK_ENUM_CONST(1)


// Register PADCTL_EDP_CFG2TMC_SOC_GPIO54_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0                 _MK_ADDR_CONST(0x24)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_SECURE                  0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_DUAL                    0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_SCR                     SCR_SOC_GPIO54_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_WORD_COUNT                      0x1
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_RESET_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_READ_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_WRITE_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVDN_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVDN_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVDN_RANGE                     16:12
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVDN_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVDN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVDN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVDN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVDN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVUP_SHIFT                     _MK_SHIFT_CONST(20)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVUP_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVUP_RANGE                     24:20
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVUP_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVUP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO54_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_SOC_GPIO55_0
#define PADCTL_EDP_SOC_GPIO55_0                 _MK_ADDR_CONST(0x28)
#define PADCTL_EDP_SOC_GPIO55_0_SECURE                  0x0
#define PADCTL_EDP_SOC_GPIO55_0_DUAL                    0x0
#define PADCTL_EDP_SOC_GPIO55_0_SCR                     SCR_SOC_GPIO55_0
#define PADCTL_EDP_SOC_GPIO55_0_WORD_COUNT                      0x1
#define PADCTL_EDP_SOC_GPIO55_0_RESET_VAL                       _MK_MASK_CONST(0x454)
#define PADCTL_EDP_SOC_GPIO55_0_RESET_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO55_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_READ_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO55_0_WRITE_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_EDP_SOC_GPIO55_0_PM_SHIFT                        _MK_SHIFT_CONST(0)
#define PADCTL_EDP_SOC_GPIO55_0_PM_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO55_0_PM_SHIFT)
#define PADCTL_EDP_SOC_GPIO55_0_PM_RANGE                        1:0
#define PADCTL_EDP_SOC_GPIO55_0_PM_WOFFSET                      0x0
#define PADCTL_EDP_SOC_GPIO55_0_PM_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_PM_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO55_0_PM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_PM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_PM_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_PM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_PM_INIT_ENUM                    RSVD0
#define PADCTL_EDP_SOC_GPIO55_0_PM_RSVD0                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO55_0_PM_SDMMC3                       _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO55_0_PM_RSVD2                        _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO55_0_PM_RSVD3                        _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_RANGE                       10:10
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_WOFFSET                     0x0
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_INIT_ENUM                   SFIO
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_GPIO                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO55_0_GPIO_SF_SEL_SFIO                        _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_SHIFT                  _MK_SHIFT_CONST(4)
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO55_0_TRISTATE_SHIFT)
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_RANGE                  4:4
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_WOFFSET                        0x0
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_INIT_ENUM                      TRISTATE
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_PASSTHROUGH                    _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO55_0_TRISTATE_TRISTATE                       _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO55_0_PUPD_SHIFT                      _MK_SHIFT_CONST(2)
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_FIELD                      _MK_FIELD_CONST(0x3, PADCTL_EDP_SOC_GPIO55_0_PUPD_SHIFT)
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_RANGE                      3:2
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_WOFFSET                    0x0
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_INIT_ENUM                  PULL_DOWN
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_NONE                       _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_PULL_UP                    _MK_ENUM_CONST(2)
#define PADCTL_EDP_SOC_GPIO55_0_PUPD_RSVD                       _MK_ENUM_CONST(3)

#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_SHIFT                   _MK_SHIFT_CONST(6)
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO55_0_E_INPUT_SHIFT)
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_RANGE                   6:6
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_INIT_ENUM                       ENABLE
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO55_0_E_INPUT_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_SHIFT                    _MK_SHIFT_CONST(8)
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO55_0_E_LPDR_SHIFT)
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_RANGE                    8:8
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_WOFFSET                  0x0
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_INIT_ENUM                        DISABLE
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO55_0_E_LPDR_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_SHIFT                   _MK_SHIFT_CONST(12)
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_SHIFT)
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_RANGE                   12:12
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_WOFFSET                 0x0
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_INIT_ENUM                       DISABLE
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_SOC_GPIO55_0_E_SCHMT_ENABLE                  _MK_ENUM_CONST(1)


// Register PADCTL_EDP_CFG2TMC_SOC_GPIO55_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0                 _MK_ADDR_CONST(0x2c)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_SECURE                  0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_DUAL                    0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_SCR                     SCR_SOC_GPIO55_0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_WORD_COUNT                      0x1
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_RESET_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_READ_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_WRITE_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVDN_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVDN_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVDN_RANGE                     16:12
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVDN_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVDN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVDN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVDN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVDN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVUP_SHIFT                     _MK_SHIFT_CONST(20)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVUP_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVUP_RANGE                     24:20
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVUP_WOFFSET                   0x0
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVUP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_SOC_GPIO55_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_DP_AUX_CH0_HPD_0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0                     _MK_ADDR_CONST(0x30)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_SECURE                      0x0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_DUAL                        0x0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_SCR                         SCR_DP_AUX_CH0_HPD_0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_WORD_COUNT                  0x1
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_RESET_VAL                   _MK_MASK_CONST(0x474)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_RESET_MASK                  _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_READ_MASK                   _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_WRITE_MASK                  _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_SHIFT                    _MK_SHIFT_CONST(0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_FIELD                    _MK_FIELD_CONST(0x3, PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_SHIFT)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_RANGE                    1:0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_WOFFSET                  0x0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_INIT_ENUM                        DP
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_DP                       _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_RSVD1                    _MK_ENUM_CONST(1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_RSVD2                    _MK_ENUM_CONST(2)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PM_RSVD3                    _MK_ENUM_CONST(3)

#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_SHIFT                   _MK_SHIFT_CONST(10)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_RANGE                   10:10
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_WOFFSET                 0x0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_INIT_ENUM                       SFIO
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_GPIO                    _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_GPIO_SF_SEL_SFIO                    _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_SHIFT                      _MK_SHIFT_CONST(4)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_SHIFT)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_RANGE                      4:4
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_WOFFSET                    0x0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_INIT_ENUM                  TRISTATE
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_PASSTHROUGH                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_TRISTATE_TRISTATE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_SHIFT                  _MK_SHIFT_CONST(2)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_FIELD                  _MK_FIELD_CONST(0x3, PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_SHIFT)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_RANGE                  3:2
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_WOFFSET                        0x0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_INIT_ENUM                      PULL_DOWN
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_NONE                   _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_PULL_UP                        _MK_ENUM_CONST(2)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_PUPD_RSVD                   _MK_ENUM_CONST(3)

#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_SHIFT                       _MK_SHIFT_CONST(6)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_SHIFT)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_RANGE                       6:6
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_INIT_ENUM                   ENABLE
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_INPUT_ENABLE                      _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_SHIFT                        _MK_SHIFT_CONST(8)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_SHIFT)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_RANGE                        8:8
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_WOFFSET                      0x0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_INIT_ENUM                    DISABLE
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_DISABLE                      _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_LPDR_ENABLE                       _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_SHIFT                       _MK_SHIFT_CONST(5)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_SHIFT)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_RANGE                       5:5
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_INIT_ENUM                   ENABLE
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_IO_HV_ENABLE                      _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_SHIFT                       _MK_SHIFT_CONST(12)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_SHIFT)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_RANGE                       12:12
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_INIT_ENUM                   DISABLE
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH0_HPD_0_E_SCHMT_ENABLE                      _MK_ENUM_CONST(1)


// Register PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0                     _MK_ADDR_CONST(0x34)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_SECURE                      0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_DUAL                        0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_SCR                         SCR_DP_AUX_CH0_HPD_0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_WORD_COUNT                  0x1
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_RESET_MASK                  _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_READ_MASK                   _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_WRITE_MASK                  _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVDN_SHIFT                 _MK_SHIFT_CONST(12)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVDN_FIELD                 _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVDN_RANGE                 16:12
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVDN_WOFFSET                       0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVDN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVDN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVDN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVDN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVUP_SHIFT                 _MK_SHIFT_CONST(20)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVUP_FIELD                 _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVUP_RANGE                 24:20
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVUP_WOFFSET                       0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVUP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVUP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_DP_AUX_CH1_HPD_0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0                     _MK_ADDR_CONST(0x38)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_SECURE                      0x0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_DUAL                        0x0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_SCR                         SCR_DP_AUX_CH1_HPD_0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_WORD_COUNT                  0x1
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_RESET_VAL                   _MK_MASK_CONST(0x474)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_RESET_MASK                  _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_READ_MASK                   _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_WRITE_MASK                  _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_SHIFT                    _MK_SHIFT_CONST(0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_FIELD                    _MK_FIELD_CONST(0x3, PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_SHIFT)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_RANGE                    1:0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_WOFFSET                  0x0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_INIT_ENUM                        DP
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_DP                       _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_RSVD1                    _MK_ENUM_CONST(1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_RSVD2                    _MK_ENUM_CONST(2)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PM_RSVD3                    _MK_ENUM_CONST(3)

#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_SHIFT                   _MK_SHIFT_CONST(10)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_RANGE                   10:10
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_WOFFSET                 0x0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_INIT_ENUM                       SFIO
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_GPIO                    _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_GPIO_SF_SEL_SFIO                    _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_SHIFT                      _MK_SHIFT_CONST(4)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_SHIFT)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_RANGE                      4:4
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_WOFFSET                    0x0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_INIT_ENUM                  TRISTATE
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_PASSTHROUGH                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_TRISTATE_TRISTATE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_SHIFT                  _MK_SHIFT_CONST(2)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_FIELD                  _MK_FIELD_CONST(0x3, PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_SHIFT)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_RANGE                  3:2
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_WOFFSET                        0x0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_INIT_ENUM                      PULL_DOWN
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_NONE                   _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_PULL_UP                        _MK_ENUM_CONST(2)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_PUPD_RSVD                   _MK_ENUM_CONST(3)

#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_SHIFT                       _MK_SHIFT_CONST(6)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_SHIFT)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_RANGE                       6:6
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_INIT_ENUM                   ENABLE
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_INPUT_ENABLE                      _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_SHIFT                        _MK_SHIFT_CONST(8)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_SHIFT)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_RANGE                        8:8
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_WOFFSET                      0x0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_INIT_ENUM                    DISABLE
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_DISABLE                      _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_LPDR_ENABLE                       _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_SHIFT                       _MK_SHIFT_CONST(5)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_SHIFT)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_RANGE                       5:5
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_INIT_ENUM                   ENABLE
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_IO_HV_ENABLE                      _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_SHIFT                       _MK_SHIFT_CONST(12)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_SHIFT)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_RANGE                       12:12
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_INIT_ENUM                   DISABLE
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH1_HPD_0_E_SCHMT_ENABLE                      _MK_ENUM_CONST(1)


// Register PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0                     _MK_ADDR_CONST(0x3c)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_SECURE                      0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_DUAL                        0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_SCR                         SCR_DP_AUX_CH1_HPD_0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_WORD_COUNT                  0x1
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_RESET_MASK                  _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_READ_MASK                   _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_WRITE_MASK                  _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVDN_SHIFT                 _MK_SHIFT_CONST(12)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVDN_FIELD                 _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVDN_RANGE                 16:12
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVDN_WOFFSET                       0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVDN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVDN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVDN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVDN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVUP_SHIFT                 _MK_SHIFT_CONST(20)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVUP_FIELD                 _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVUP_RANGE                 24:20
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVUP_WOFFSET                       0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVUP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVUP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_DP_AUX_CH2_HPD_0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0                     _MK_ADDR_CONST(0x40)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_SECURE                      0x0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_DUAL                        0x0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_SCR                         SCR_DP_AUX_CH2_HPD_0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_WORD_COUNT                  0x1
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_RESET_VAL                   _MK_MASK_CONST(0x474)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_RESET_MASK                  _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_READ_MASK                   _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_WRITE_MASK                  _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_SHIFT                    _MK_SHIFT_CONST(0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_FIELD                    _MK_FIELD_CONST(0x3, PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_SHIFT)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_RANGE                    1:0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_WOFFSET                  0x0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_INIT_ENUM                        DP
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_DP                       _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_DISPLAYA                 _MK_ENUM_CONST(1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_RSVD2                    _MK_ENUM_CONST(2)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PM_RSVD3                    _MK_ENUM_CONST(3)

#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_SHIFT                   _MK_SHIFT_CONST(10)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_RANGE                   10:10
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_WOFFSET                 0x0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_INIT_ENUM                       SFIO
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_GPIO                    _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_GPIO_SF_SEL_SFIO                    _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_SHIFT                      _MK_SHIFT_CONST(4)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_SHIFT)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_RANGE                      4:4
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_WOFFSET                    0x0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_INIT_ENUM                  TRISTATE
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_PASSTHROUGH                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_TRISTATE_TRISTATE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_SHIFT                  _MK_SHIFT_CONST(2)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_FIELD                  _MK_FIELD_CONST(0x3, PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_SHIFT)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_RANGE                  3:2
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_WOFFSET                        0x0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_INIT_ENUM                      PULL_DOWN
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_NONE                   _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_PULL_UP                        _MK_ENUM_CONST(2)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_PUPD_RSVD                   _MK_ENUM_CONST(3)

#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_SHIFT                       _MK_SHIFT_CONST(6)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_SHIFT)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_RANGE                       6:6
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_INIT_ENUM                   ENABLE
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_INPUT_ENABLE                      _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_SHIFT                        _MK_SHIFT_CONST(8)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_SHIFT)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_RANGE                        8:8
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_WOFFSET                      0x0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_INIT_ENUM                    DISABLE
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_DISABLE                      _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_LPDR_ENABLE                       _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_SHIFT                       _MK_SHIFT_CONST(5)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_SHIFT)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_RANGE                       5:5
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_INIT_ENUM                   ENABLE
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_IO_HV_ENABLE                      _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_SHIFT                       _MK_SHIFT_CONST(12)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_SHIFT)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_RANGE                       12:12
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_INIT_ENUM                   DISABLE
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH2_HPD_0_E_SCHMT_ENABLE                      _MK_ENUM_CONST(1)


// Register PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0                     _MK_ADDR_CONST(0x44)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_SECURE                      0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_DUAL                        0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_SCR                         SCR_DP_AUX_CH2_HPD_0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_WORD_COUNT                  0x1
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_RESET_MASK                  _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_READ_MASK                   _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_WRITE_MASK                  _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVDN_SHIFT                 _MK_SHIFT_CONST(12)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVDN_FIELD                 _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVDN_RANGE                 16:12
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVDN_WOFFSET                       0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVDN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVDN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVDN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVDN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVUP_SHIFT                 _MK_SHIFT_CONST(20)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVUP_FIELD                 _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVUP_RANGE                 24:20
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVUP_WOFFSET                       0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVUP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVUP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_DP_AUX_CH3_HPD_0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0                     _MK_ADDR_CONST(0x48)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_SECURE                      0x0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_DUAL                        0x0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_SCR                         SCR_DP_AUX_CH3_HPD_0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_WORD_COUNT                  0x1
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_RESET_VAL                   _MK_MASK_CONST(0x474)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_RESET_MASK                  _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_READ_MASK                   _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_WRITE_MASK                  _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_SHIFT                    _MK_SHIFT_CONST(0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_FIELD                    _MK_FIELD_CONST(0x3, PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_SHIFT)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_RANGE                    1:0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_WOFFSET                  0x0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_INIT_ENUM                        DP
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_DP                       _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_DISPLAYB                 _MK_ENUM_CONST(1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_RSVD2                    _MK_ENUM_CONST(2)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PM_RSVD3                    _MK_ENUM_CONST(3)

#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_SHIFT                   _MK_SHIFT_CONST(10)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_RANGE                   10:10
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_WOFFSET                 0x0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_INIT_ENUM                       SFIO
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_GPIO                    _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_GPIO_SF_SEL_SFIO                    _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_SHIFT                      _MK_SHIFT_CONST(4)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_SHIFT)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_RANGE                      4:4
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_WOFFSET                    0x0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_INIT_ENUM                  TRISTATE
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_PASSTHROUGH                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_TRISTATE_TRISTATE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_SHIFT                  _MK_SHIFT_CONST(2)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_FIELD                  _MK_FIELD_CONST(0x3, PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_SHIFT)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_RANGE                  3:2
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_WOFFSET                        0x0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_INIT_ENUM                      PULL_DOWN
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_NONE                   _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_PULL_UP                        _MK_ENUM_CONST(2)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_PUPD_RSVD                   _MK_ENUM_CONST(3)

#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_SHIFT                       _MK_SHIFT_CONST(6)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_SHIFT)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_RANGE                       6:6
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_INIT_ENUM                   ENABLE
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_INPUT_ENABLE                      _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_SHIFT                        _MK_SHIFT_CONST(8)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_SHIFT)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_RANGE                        8:8
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_WOFFSET                      0x0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_INIT_ENUM                    DISABLE
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_DISABLE                      _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_LPDR_ENABLE                       _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_SHIFT                       _MK_SHIFT_CONST(5)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_SHIFT)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_RANGE                       5:5
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_INIT_ENUM                   ENABLE
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_IO_HV_ENABLE                      _MK_ENUM_CONST(1)

#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_SHIFT                       _MK_SHIFT_CONST(12)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_SHIFT)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_RANGE                       12:12
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_WOFFSET                     0x0
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_INIT_ENUM                   DISABLE
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_DISABLE                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_DP_AUX_CH3_HPD_0_E_SCHMT_ENABLE                      _MK_ENUM_CONST(1)


// Register PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0                     _MK_ADDR_CONST(0x4c)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_SECURE                      0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_DUAL                        0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_SCR                         SCR_DP_AUX_CH3_HPD_0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_WORD_COUNT                  0x1
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_RESET_MASK                  _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_READ_MASK                   _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_WRITE_MASK                  _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVDN_SHIFT                 _MK_SHIFT_CONST(12)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVDN_FIELD                 _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVDN_RANGE                 16:12
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVDN_WOFFSET                       0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVDN_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVDN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVDN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVDN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVUP_SHIFT                 _MK_SHIFT_CONST(20)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVUP_FIELD                 _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVUP_RANGE                 24:20
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVUP_WOFFSET                       0x0
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVUP_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVUP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_HDMI_CEC_0
#define PADCTL_EDP_HDMI_CEC_0                   _MK_ADDR_CONST(0x50)
#define PADCTL_EDP_HDMI_CEC_0_SECURE                    0x0
#define PADCTL_EDP_HDMI_CEC_0_DUAL                      0x0
#define PADCTL_EDP_HDMI_CEC_0_SCR                       SCR_HDMI_CEC_0
#define PADCTL_EDP_HDMI_CEC_0_WORD_COUNT                        0x1
#define PADCTL_EDP_HDMI_CEC_0_RESET_VAL                         _MK_MASK_CONST(0x470)
#define PADCTL_EDP_HDMI_CEC_0_RESET_MASK                        _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_HDMI_CEC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_READ_MASK                         _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_HDMI_CEC_0_WRITE_MASK                        _MK_MASK_CONST(0x157f)
#define PADCTL_EDP_HDMI_CEC_0_PM_SHIFT                  _MK_SHIFT_CONST(0)
#define PADCTL_EDP_HDMI_CEC_0_PM_FIELD                  _MK_FIELD_CONST(0x3, PADCTL_EDP_HDMI_CEC_0_PM_SHIFT)
#define PADCTL_EDP_HDMI_CEC_0_PM_RANGE                  1:0
#define PADCTL_EDP_HDMI_CEC_0_PM_WOFFSET                        0x0
#define PADCTL_EDP_HDMI_CEC_0_PM_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_PM_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define PADCTL_EDP_HDMI_CEC_0_PM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_PM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_PM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_PM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_PM_INIT_ENUM                      HDMI
#define PADCTL_EDP_HDMI_CEC_0_PM_HDMI                   _MK_ENUM_CONST(0)
#define PADCTL_EDP_HDMI_CEC_0_PM_RSVD1                  _MK_ENUM_CONST(1)
#define PADCTL_EDP_HDMI_CEC_0_PM_RSVD2                  _MK_ENUM_CONST(2)
#define PADCTL_EDP_HDMI_CEC_0_PM_RSVD3                  _MK_ENUM_CONST(3)

#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_SHIFT                 _MK_SHIFT_CONST(10)
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_RANGE                 10:10
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_WOFFSET                       0x0
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_INIT_ENUM                     SFIO
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_GPIO                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_HDMI_CEC_0_GPIO_SF_SEL_SFIO                  _MK_ENUM_CONST(1)

#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_SHIFT                    _MK_SHIFT_CONST(4)
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_EDP_HDMI_CEC_0_TRISTATE_SHIFT)
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_RANGE                    4:4
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_WOFFSET                  0x0
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_DEFAULT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_INIT_ENUM                        TRISTATE
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_PASSTHROUGH                      _MK_ENUM_CONST(0)
#define PADCTL_EDP_HDMI_CEC_0_TRISTATE_TRISTATE                 _MK_ENUM_CONST(1)

#define PADCTL_EDP_HDMI_CEC_0_PUPD_SHIFT                        _MK_SHIFT_CONST(2)
#define PADCTL_EDP_HDMI_CEC_0_PUPD_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_EDP_HDMI_CEC_0_PUPD_SHIFT)
#define PADCTL_EDP_HDMI_CEC_0_PUPD_RANGE                        3:2
#define PADCTL_EDP_HDMI_CEC_0_PUPD_WOFFSET                      0x0
#define PADCTL_EDP_HDMI_CEC_0_PUPD_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_PUPD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_EDP_HDMI_CEC_0_PUPD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_PUPD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_PUPD_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_PUPD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_PUPD_INIT_ENUM                    NONE
#define PADCTL_EDP_HDMI_CEC_0_PUPD_NONE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_HDMI_CEC_0_PUPD_PULL_DOWN                    _MK_ENUM_CONST(1)
#define PADCTL_EDP_HDMI_CEC_0_PUPD_PULL_UP                      _MK_ENUM_CONST(2)
#define PADCTL_EDP_HDMI_CEC_0_PUPD_RSVD                 _MK_ENUM_CONST(3)

#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_SHIFT                     _MK_SHIFT_CONST(6)
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_EDP_HDMI_CEC_0_E_INPUT_SHIFT)
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_RANGE                     6:6
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_WOFFSET                   0x0
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_DEFAULT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_INIT_ENUM                 ENABLE
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_DISABLE                   _MK_ENUM_CONST(0)
#define PADCTL_EDP_HDMI_CEC_0_E_INPUT_ENABLE                    _MK_ENUM_CONST(1)

#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_SHIFT                      _MK_SHIFT_CONST(8)
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_EDP_HDMI_CEC_0_E_LPDR_SHIFT)
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_RANGE                      8:8
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_WOFFSET                    0x0
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_INIT_ENUM                  DISABLE
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_DISABLE                    _MK_ENUM_CONST(0)
#define PADCTL_EDP_HDMI_CEC_0_E_LPDR_ENABLE                     _MK_ENUM_CONST(1)

#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_SHIFT                     _MK_SHIFT_CONST(5)
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_EDP_HDMI_CEC_0_E_IO_HV_SHIFT)
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_RANGE                     5:5
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_WOFFSET                   0x0
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_DEFAULT                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_INIT_ENUM                 ENABLE
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_DISABLE                   _MK_ENUM_CONST(0)
#define PADCTL_EDP_HDMI_CEC_0_E_IO_HV_ENABLE                    _MK_ENUM_CONST(1)

#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_EDP_HDMI_CEC_0_E_SCHMT_SHIFT)
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_RANGE                     12:12
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_WOFFSET                   0x0
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_INIT_ENUM                 DISABLE
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_DISABLE                   _MK_ENUM_CONST(0)
#define PADCTL_EDP_HDMI_CEC_0_E_SCHMT_ENABLE                    _MK_ENUM_CONST(1)


// Register PADCTL_EDP_CFG2TMC_HDMI_CEC_0
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0                   _MK_ADDR_CONST(0x54)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_SECURE                    0x0
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_DUAL                      0x0
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_SCR                       SCR_HDMI_CEC_0
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_WORD_COUNT                        0x1
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_RESET_MASK                        _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_READ_MASK                         _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_WRITE_MASK                        _MK_MASK_CONST(0x1f1f000)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVDN_SHIFT                       _MK_SHIFT_CONST(12)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVDN_FIELD                       _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVDN_RANGE                       16:12
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVDN_WOFFSET                     0x0
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVDN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVDN_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVDN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVDN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVUP_SHIFT                       _MK_SHIFT_CONST(20)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVUP_FIELD                       _MK_FIELD_CONST(0x1f, PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVUP_RANGE                       24:20
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVUP_WOFFSET                     0x0
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVUP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_CFG2TMC_HDMI_CEC_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_EC_FEATURE_0
#define PADCTL_EDP_EC_FEATURE_0                 _MK_ADDR_CONST(0x400)
#define PADCTL_EDP_EC_FEATURE_0_SECURE                  0x0
#define PADCTL_EDP_EC_FEATURE_0_DUAL                    0x0
#define PADCTL_EDP_EC_FEATURE_0_SCR                     EC_SCR_0
#define PADCTL_EDP_EC_FEATURE_0_WORD_COUNT                      0x1
#define PADCTL_EDP_EC_FEATURE_0_RESET_VAL                       _MK_MASK_CONST(0x20001)
#define PADCTL_EDP_EC_FEATURE_0_RESET_MASK                      _MK_MASK_CONST(0xffff003f)
#define PADCTL_EDP_EC_FEATURE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_FEATURE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_FEATURE_0_READ_MASK                       _MK_MASK_CONST(0xffff003f)
#define PADCTL_EDP_EC_FEATURE_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SHIFT                   _MK_SHIFT_CONST(16)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_FIELD                   _MK_FIELD_CONST(0xffff, PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SHIFT)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_RANGE                   31:16
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_WOFFSET                 0x0
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_DEFAULT                 _MK_MASK_CONST(0x2)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SLICES_SHIFT                    _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SLICES_FIELD                    _MK_FIELD_CONST(0x3f, PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SLICES_SHIFT)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SLICES_RANGE                    5:0
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SLICES_WOFFSET                  0x0
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SLICES_DEFAULT                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_EC_SWRESET_0
#define PADCTL_EDP_EC_SWRESET_0                 _MK_ADDR_CONST(0x404)
#define PADCTL_EDP_EC_SWRESET_0_SECURE                  0x0
#define PADCTL_EDP_EC_SWRESET_0_DUAL                    0x0
#define PADCTL_EDP_EC_SWRESET_0_SCR                     EC_SCR_0
#define PADCTL_EDP_EC_SWRESET_0_WORD_COUNT                      0x1
#define PADCTL_EDP_EC_SWRESET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_SWRESET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_SWRESET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_SWRESET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_SWRESET_0_READ_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_SWRESET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_SWRESET_0_SWRST_SHIFT                     _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_SWRESET_0_SWRST_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_SWRESET_0_SWRST_SHIFT)
#define PADCTL_EDP_EC_SWRESET_0_SWRST_RANGE                     0:0
#define PADCTL_EDP_EC_SWRESET_0_SWRST_WOFFSET                   0x0
#define PADCTL_EDP_EC_SWRESET_0_SWRST_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_SWRESET_0_SWRST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_SWRESET_0_SWRST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_SWRESET_0_SWRST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_SWRESET_0_SWRST_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_SWRESET_0_SWRST_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_EC_MISSIONERR_TYPE_0
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0                 _MK_ADDR_CONST(0x408)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_SECURE                  0x0
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_DUAL                    0x0
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_SCR                     EC_SCR_0
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_WORD_COUNT                      0x1
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_RESET_VAL                       _MK_MASK_CONST(0x5)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_READ_MASK                       _MK_MASK_CONST(0x3f)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_CODE_SHIFT                      _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_CODE_FIELD                      _MK_FIELD_CONST(0x3f, PADCTL_EDP_EC_MISSIONERR_TYPE_0_CODE_SHIFT)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_CODE_RANGE                      5:0
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_CODE_WOFFSET                    0x0
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_CODE_DEFAULT                    _MK_MASK_CONST(0x5)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0                   _MK_ADDR_CONST(0x40c)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_SECURE                    0x0
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_DUAL                      0x0
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_SCR                       EC_SCR_0
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_WORD_COUNT                        0x1
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_RESET_MASK                        _MK_MASK_CONST(0x1ff)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_READ_MASK                         _MK_MASK_CONST(0x1ff)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                       _MK_FIELD_CONST(0x1ff, PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                       8:0
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                     0x0
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0x1ff)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x410

// Register PADCTL_EDP_EC_MISSIONERR_INDEX_0
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0                        _MK_ADDR_CONST(0x414)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_SECURE                         0x0
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_DUAL                   0x0
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_SCR                    EC_SCR_0
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_WORD_COUNT                     0x1
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_IDX_SHIFT                      _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_IDX_FIELD                      _MK_FIELD_CONST(0x3, PADCTL_EDP_EC_MISSIONERR_INDEX_0_IDX_SHIFT)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_IDX_RANGE                      1:0
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_IDX_WOFFSET                    0x0
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_IDX_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0                   _MK_ADDR_CONST(0x418)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_SECURE                    0x0
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_DUAL                      0x0
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_SCR                       EC_SCR_0
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_WORD_COUNT                        0x1
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_RESET_VAL                         _MK_MASK_CONST(0xff)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                       _MK_FIELD_CONST(0xff, PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                       7:0
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                     0x0
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                     _MK_MASK_CONST(0xff)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0                        _MK_ADDR_CONST(0x41c)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_SECURE                         0x0
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_DUAL                   0x0
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_SCR                    EC_SCR_0
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                     0x1
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                     _MK_MASK_CONST(0xff)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                      _MK_MASK_CONST(0xff)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                    _MK_FIELD_CONST(0xff, PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                    7:0
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                  0x0
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                     _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                   _MK_ENUM_CONST(225)


// Reserved address 0x420

// Reserved address 0x424

// Reserved address 0x428

// Reserved address 0x42c

// Register PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0                     _MK_ADDR_CONST(0x430)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                      0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                         EC_SCR_0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                  0x1
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                   _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                  _MK_SHIFT_CONST(2)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                  2:2
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                  _MK_SHIFT_CONST(1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                  1:1
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                  _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                  0:0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0                      _MK_ADDR_CONST(0x434)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                       0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                         0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_SCR                  EC_SCR_0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                   0x1
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                   _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                   _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                   _MK_SHIFT_CONST(2)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                   2:2
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                 0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                   _MK_SHIFT_CONST(1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                   1:1
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                 0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                   _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                   _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                   0:0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                 0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                   _MK_ENUM_CONST(1)


// Register PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0                     _MK_ADDR_CONST(0x438)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                      0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_SCR                         EC_SCR_0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                  0x1
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                  _MK_SHIFT_CONST(2)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                  2:2
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                  _MK_SHIFT_CONST(1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                  1:1
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                  _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                  0:0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0                     _MK_ADDR_CONST(0x43c)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                      0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_SCR                         EC_SCR_0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                  0x1
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                  _MK_SHIFT_CONST(2)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                  2:2
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT                  _MK_SHIFT_CONST(1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_RANGE                  1:1
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_WOFFSET                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                  _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                  0:0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0                      _MK_ADDR_CONST(0x440)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                       0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                         0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_SCR                  EC_SCR_0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                   0x1
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                    _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                   _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                    _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                   _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                   _MK_SHIFT_CONST(2)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                   2:2
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                 0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                   _MK_SHIFT_CONST(1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                   1:1
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                 0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                   _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                   0:0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                 0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                  _MK_ENUM_CONST(1)


// Register PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0                       _MK_ADDR_CONST(0x444)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_SECURE                        0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_DUAL                  0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_SCR                   EC_SCR_0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                    0x1
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                    _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                    _MK_SHIFT_CONST(2)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                    2:2
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                  0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                    _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                    _MK_SHIFT_CONST(1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                    1:1
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                  0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                    _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                    _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                    0:0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                  0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                    _MK_ENUM_CONST(1)


// Register PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0                      _MK_ADDR_CONST(0x448)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_SECURE                       0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_DUAL                         0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_SCR                  EC_SCR_0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                   0x1
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                    _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                   _MK_SHIFT_CONST(2)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                   2:2
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                 0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                   _MK_SHIFT_CONST(1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                   1:1
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                 0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                   _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                   0:0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                 0x0
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Reserved address 0x44c

// Register PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0                        _MK_ADDR_CONST(0x450)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_SECURE                         0x0
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_DUAL                   0x0
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_SCR                    EC_SCR_0
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                     0x1
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                     2:2
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                   0x0
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                    _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                     _MK_SHIFT_CONST(1)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                     1:1
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                   0x0
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                    _MK_ENUM_CONST(1)

#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                     _MK_SHIFT_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                     0:0
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                   0x0
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                  _MK_ENUM_CONST(0)
#define PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                    _MK_ENUM_CONST(1)


// Reserved address 0x454

// Reserved address 0x458

// Reserved address 0x45c

//
// REGISTER LIST
//
#define LIST_ARPADCTL_EDP_REGS(_op_) \
_op_(PADCTL_EDP_SOC_GPIO50_0) \
_op_(PADCTL_EDP_CFG2TMC_SOC_GPIO50_0) \
_op_(PADCTL_EDP_SOC_GPIO51_0) \
_op_(PADCTL_EDP_CFG2TMC_SOC_GPIO51_0) \
_op_(PADCTL_EDP_SOC_GPIO52_0) \
_op_(PADCTL_EDP_CFG2TMC_SOC_GPIO52_0) \
_op_(PADCTL_EDP_SOC_GPIO53_0) \
_op_(PADCTL_EDP_CFG2TMC_SOC_GPIO53_0) \
_op_(PADCTL_EDP_SOC_GPIO54_0) \
_op_(PADCTL_EDP_CFG2TMC_SOC_GPIO54_0) \
_op_(PADCTL_EDP_SOC_GPIO55_0) \
_op_(PADCTL_EDP_CFG2TMC_SOC_GPIO55_0) \
_op_(PADCTL_EDP_DP_AUX_CH0_HPD_0) \
_op_(PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0) \
_op_(PADCTL_EDP_DP_AUX_CH1_HPD_0) \
_op_(PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0) \
_op_(PADCTL_EDP_DP_AUX_CH2_HPD_0) \
_op_(PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0) \
_op_(PADCTL_EDP_DP_AUX_CH3_HPD_0) \
_op_(PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0) \
_op_(PADCTL_EDP_HDMI_CEC_0) \
_op_(PADCTL_EDP_CFG2TMC_HDMI_CEC_0) \
_op_(PADCTL_EDP_EC_FEATURE_0) \
_op_(PADCTL_EDP_EC_SWRESET_0) \
_op_(PADCTL_EDP_EC_MISSIONERR_TYPE_0) \
_op_(PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0) \
_op_(PADCTL_EDP_EC_MISSIONERR_INDEX_0) \
_op_(PADCTL_EDP_EC_CORRECTABLE_THRESHOLD_0) \
_op_(PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0) \
_op_(PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0) \
_op_(PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_FORCE_0) \
_op_(PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_STATUS_0) \
_op_(PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_INJECT_0) \
_op_(PADCTL_EDP_EC_ERRSLICE0_LATENTERR_ENABLE_0) \
_op_(PADCTL_EDP_EC_ERRSLICE0_LATENTERR_FORCE_0) \
_op_(PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0) \
_op_(PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_PADCTL_EDP 0x00000000
#define BASE_ADDRESS_PADCTL_EDP_EC      0x00000400

//
// ARPADCTL_EDP REGISTER BANKS
//

#define PADCTL_EDP0_FIRST_REG 0x0000 // PADCTL_EDP_SOC_GPIO50_0
#define PADCTL_EDP0_LAST_REG 0x0054 // PADCTL_EDP_CFG2TMC_HDMI_CEC_0
#define PADCTL_EDP_EC0_FIRST_REG 0x0400 // PADCTL_EDP_EC_FEATURE_0
#define PADCTL_EDP_EC0_LAST_REG 0x040c // PADCTL_EDP_EC_CURRENT_COUNTER_VALUE_0
#define PADCTL_EDP_EC1_FIRST_REG 0x0414 // PADCTL_EDP_EC_MISSIONERR_INDEX_0
#define PADCTL_EDP_EC1_LAST_REG 0x041c // PADCTL_EDP_EC_MISSIONERR_INJECT_UNLOCK_0
#define PADCTL_EDP_EC2_FIRST_REG 0x0430 // PADCTL_EDP_EC_ERRSLICE0_MISSIONERR_ENABLE_0
#define PADCTL_EDP_EC2_LAST_REG 0x0448 // PADCTL_EDP_EC_ERRSLICE0_LATENTERR_STATUS_0
#define PADCTL_EDP_EC3_FIRST_REG 0x0450 // PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0
#define PADCTL_EDP_EC3_LAST_REG 0x0450 // PADCTL_EDP_EC_ERRSLICE0_COUNTER_RELOAD_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARPADCTL_EDP_H_INC_
