//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARAOPM_H_INC_
#define ___ARAOPM_H_INC_
#define NV_MOBILE_ARAOPM_H_UNIT_OF_OFFSET 1B


// Register AOPM_SOFT_RESET_0
#define AOPM_SOFT_RESET_0                       _MK_ADDR_CONST(0x0)
#define AOPM_SOFT_RESET_0_SECURE                        0x0
#define AOPM_SOFT_RESET_0_DUAL                  0x0
#define AOPM_SOFT_RESET_0_SCR                   SCR_PRIVATE_0
#define AOPM_SOFT_RESET_0_WORD_COUNT                    0x1
#define AOPM_SOFT_RESET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_SOFT_RESET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_SOFT_RESET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define AOPM_SOFT_RESET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_SOFT_RESET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_SOFT_RESET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_SOFT_RESET_0_SOFT_RESET_SHIFT                      _MK_SHIFT_CONST(0)
#define AOPM_SOFT_RESET_0_SOFT_RESET_FIELD                      _MK_FIELD_CONST(0x1, AOPM_SOFT_RESET_0_SOFT_RESET_SHIFT)
#define AOPM_SOFT_RESET_0_SOFT_RESET_RANGE                      0:0
#define AOPM_SOFT_RESET_0_SOFT_RESET_WOFFSET                    0x0
#define AOPM_SOFT_RESET_0_SOFT_RESET_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_SOFT_RESET_0_SOFT_RESET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_SOFT_RESET_0_SOFT_RESET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_SOFT_RESET_0_SOFT_RESET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_SOFT_RESET_0_SOFT_RESET_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_SOFT_RESET_0_SOFT_RESET_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_SOFT_RESET_0_SOFT_RESET_INIT_ENUM                  FALSE
#define AOPM_SOFT_RESET_0_SOFT_RESET_FALSE                      _MK_ENUM_CONST(0)
#define AOPM_SOFT_RESET_0_SOFT_RESET_TRUE                       _MK_ENUM_CONST(1)


// Register AOPM_SLCG_CTRL_0
#define AOPM_SLCG_CTRL_0                        _MK_ADDR_CONST(0x4)
#define AOPM_SLCG_CTRL_0_SECURE                         0x0
#define AOPM_SLCG_CTRL_0_DUAL                   0x0
#define AOPM_SLCG_CTRL_0_SCR                    SCR_PRIVATE_0
#define AOPM_SLCG_CTRL_0_WORD_COUNT                     0x1
#define AOPM_SLCG_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define AOPM_SLCG_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define AOPM_SLCG_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_SLCG_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_SLCG_CTRL_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define AOPM_SLCG_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_FIELD                      _MK_FIELD_CONST(0x1, AOPM_SLCG_CTRL_0_APB_SLCG_EN_SHIFT)
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_RANGE                      0:0
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_WOFFSET                    0x0
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_INIT_ENUM                  DISABLE
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_DISABLE                    _MK_ENUM_CONST(0)
#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_ENABLE                     _MK_ENUM_CONST(1)

#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_SHIFT                       _MK_SHIFT_CONST(1)
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_FIELD                       _MK_FIELD_CONST(0x1, AOPM_SLCG_CTRL_0_PM_SLCG_EN_SHIFT)
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_RANGE                       1:1
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_WOFFSET                     0x0
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_INIT_ENUM                   DISABLE
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_DISABLE                     _MK_ENUM_CONST(0)
#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_ENABLE                      _MK_ENUM_CONST(1)


// Register AOPM_TGT_PWR_STATE_0
#define AOPM_TGT_PWR_STATE_0                    _MK_ADDR_CONST(0x8)
#define AOPM_TGT_PWR_STATE_0_SECURE                     0x0
#define AOPM_TGT_PWR_STATE_0_DUAL                       0x0
#define AOPM_TGT_PWR_STATE_0_SCR                        SCR_SHARED_0
#define AOPM_TGT_PWR_STATE_0_WORD_COUNT                         0x1
#define AOPM_TGT_PWR_STATE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define AOPM_TGT_PWR_STATE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define AOPM_TGT_PWR_STATE_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
#define AOPM_TGT_PWR_STATE_0_STATE_SHIFT                        _MK_SHIFT_CONST(0)
#define AOPM_TGT_PWR_STATE_0_STATE_FIELD                        _MK_FIELD_CONST(0xf, AOPM_TGT_PWR_STATE_0_STATE_SHIFT)
#define AOPM_TGT_PWR_STATE_0_STATE_RANGE                        3:0
#define AOPM_TGT_PWR_STATE_0_STATE_WOFFSET                      0x0
#define AOPM_TGT_PWR_STATE_0_STATE_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_STATE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define AOPM_TGT_PWR_STATE_0_STATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_STATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_STATE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_STATE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_STATE_0_STATE_INIT_ENUM                    ACTIVE
#define AOPM_TGT_PWR_STATE_0_STATE_ACTIVE                       _MK_ENUM_CONST(0)
#define AOPM_TGT_PWR_STATE_0_STATE_IDLE                 _MK_ENUM_CONST(1)
#define AOPM_TGT_PWR_STATE_0_STATE_STANDBY                      _MK_ENUM_CONST(2)
#define AOPM_TGT_PWR_STATE_0_STATE_DORMANT                      _MK_ENUM_CONST(3)

#define AOPM_TGT_PWR_STATE_0_RAM_PPG_SHIFT                      _MK_SHIFT_CONST(4)
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_FIELD                      _MK_FIELD_CONST(0x1, AOPM_TGT_PWR_STATE_0_RAM_PPG_SHIFT)
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_RANGE                      4:4
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_WOFFSET                    0x0
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_INIT_ENUM                  DISABLE
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_DISABLE                    _MK_ENUM_CONST(0)
#define AOPM_TGT_PWR_STATE_0_RAM_PPG_ENABLE                     _MK_ENUM_CONST(1)

#define AOPM_TGT_PWR_STATE_0_RAM_RET_SHIFT                      _MK_SHIFT_CONST(5)
#define AOPM_TGT_PWR_STATE_0_RAM_RET_FIELD                      _MK_FIELD_CONST(0x1, AOPM_TGT_PWR_STATE_0_RAM_RET_SHIFT)
#define AOPM_TGT_PWR_STATE_0_RAM_RET_RANGE                      5:5
#define AOPM_TGT_PWR_STATE_0_RAM_RET_WOFFSET                    0x0
#define AOPM_TGT_PWR_STATE_0_RAM_RET_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAM_RET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_STATE_0_RAM_RET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAM_RET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAM_RET_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAM_RET_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_STATE_0_RAM_RET_INIT_ENUM                  DISABLE
#define AOPM_TGT_PWR_STATE_0_RAM_RET_DISABLE                    _MK_ENUM_CONST(0)
#define AOPM_TGT_PWR_STATE_0_RAM_RET_ENABLE                     _MK_ENUM_CONST(1)

#define AOPM_TGT_PWR_STATE_0_RAIL_RET_SHIFT                     _MK_SHIFT_CONST(6)
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_FIELD                     _MK_FIELD_CONST(0x1, AOPM_TGT_PWR_STATE_0_RAIL_RET_SHIFT)
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_RANGE                     6:6
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_WOFFSET                   0x0
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_INIT_ENUM                 DISABLE
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_DISABLE                   _MK_ENUM_CONST(0)
#define AOPM_TGT_PWR_STATE_0_RAIL_RET_ENABLE                    _MK_ENUM_CONST(1)

#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_SHIFT                       _MK_SHIFT_CONST(7)
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_FIELD                       _MK_FIELD_CONST(0x1, AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_SHIFT)
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_RANGE                       7:7
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_WOFFSET                     0x0
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_INIT_ENUM                   DISABLE
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_DISABLE                     _MK_ENUM_CONST(0)
#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_ENABLE                      _MK_ENUM_CONST(1)


// Register AOPM_TCM_RET_TIMER_0
#define AOPM_TCM_RET_TIMER_0                    _MK_ADDR_CONST(0xc)
#define AOPM_TCM_RET_TIMER_0_SECURE                     0x0
#define AOPM_TCM_RET_TIMER_0_DUAL                       0x0
#define AOPM_TCM_RET_TIMER_0_SCR                        SCR_SHARED_0
#define AOPM_TCM_RET_TIMER_0_WORD_COUNT                         0x1
#define AOPM_TCM_RET_TIMER_0_RESET_VAL                  _MK_MASK_CONST(0x10)
#define AOPM_TCM_RET_TIMER_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define AOPM_TCM_RET_TIMER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_TCM_RET_TIMER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_TCM_RET_TIMER_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define AOPM_TCM_RET_TIMER_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define AOPM_TCM_RET_TIMER_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define AOPM_TCM_RET_TIMER_0_VAL_FIELD                  _MK_FIELD_CONST(0xffffffff, AOPM_TCM_RET_TIMER_0_VAL_SHIFT)
#define AOPM_TCM_RET_TIMER_0_VAL_RANGE                  31:0
#define AOPM_TCM_RET_TIMER_0_VAL_WOFFSET                        0x0
#define AOPM_TCM_RET_TIMER_0_VAL_DEFAULT                        _MK_MASK_CONST(0x10)
#define AOPM_TCM_RET_TIMER_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define AOPM_TCM_RET_TIMER_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_TCM_RET_TIMER_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_TCM_RET_TIMER_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_TCM_RET_TIMER_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register AOPM_DBG_TIMER_0
#define AOPM_DBG_TIMER_0                        _MK_ADDR_CONST(0x10)
#define AOPM_DBG_TIMER_0_SECURE                         0x0
#define AOPM_DBG_TIMER_0_DUAL                   0x0
#define AOPM_DBG_TIMER_0_SCR                    SCR_SHARED_0
#define AOPM_DBG_TIMER_0_WORD_COUNT                     0x1
#define AOPM_DBG_TIMER_0_RESET_VAL                      _MK_MASK_CONST(0x10)
#define AOPM_DBG_TIMER_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define AOPM_DBG_TIMER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_DBG_TIMER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_DBG_TIMER_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define AOPM_DBG_TIMER_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define AOPM_DBG_TIMER_0_VAL_SHIFT                      _MK_SHIFT_CONST(0)
#define AOPM_DBG_TIMER_0_VAL_FIELD                      _MK_FIELD_CONST(0xffffffff, AOPM_DBG_TIMER_0_VAL_SHIFT)
#define AOPM_DBG_TIMER_0_VAL_RANGE                      31:0
#define AOPM_DBG_TIMER_0_VAL_WOFFSET                    0x0
#define AOPM_DBG_TIMER_0_VAL_DEFAULT                    _MK_MASK_CONST(0x10)
#define AOPM_DBG_TIMER_0_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define AOPM_DBG_TIMER_0_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_DBG_TIMER_0_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_TIMER_0_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_DBG_TIMER_0_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register AOPM_LP_EXIT_0
#define AOPM_LP_EXIT_0                  _MK_ADDR_CONST(0x14)
#define AOPM_LP_EXIT_0_SECURE                   0x0
#define AOPM_LP_EXIT_0_DUAL                     0x0
#define AOPM_LP_EXIT_0_SCR                      SCR_SHARED_0
#define AOPM_LP_EXIT_0_WORD_COUNT                       0x1
#define AOPM_LP_EXIT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define AOPM_LP_EXIT_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_LP_EXIT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define AOPM_LP_EXIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_LP_EXIT_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_LP_EXIT_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_LP_EXIT_0_EXIT_SHIFT                       _MK_SHIFT_CONST(0)
#define AOPM_LP_EXIT_0_EXIT_FIELD                       _MK_FIELD_CONST(0x1, AOPM_LP_EXIT_0_EXIT_SHIFT)
#define AOPM_LP_EXIT_0_EXIT_RANGE                       0:0
#define AOPM_LP_EXIT_0_EXIT_WOFFSET                     0x0
#define AOPM_LP_EXIT_0_EXIT_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_LP_EXIT_0_EXIT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_LP_EXIT_0_EXIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_LP_EXIT_0_EXIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_LP_EXIT_0_EXIT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_LP_EXIT_0_EXIT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_LP_EXIT_0_EXIT_DONE                        _MK_ENUM_CONST(0)
#define AOPM_LP_EXIT_0_EXIT_PENDING                     _MK_ENUM_CONST(1)


// Register AOPM_POWER_CFG_MASK_0
#define AOPM_POWER_CFG_MASK_0                   _MK_ADDR_CONST(0x18)
#define AOPM_POWER_CFG_MASK_0_SECURE                    0x0
#define AOPM_POWER_CFG_MASK_0_DUAL                      0x0
#define AOPM_POWER_CFG_MASK_0_SCR                       SCR_PRIVATE_0
#define AOPM_POWER_CFG_MASK_0_WORD_COUNT                        0x1
#define AOPM_POWER_CFG_MASK_0_RESET_VAL                         _MK_MASK_CONST(0x400070)
#define AOPM_POWER_CFG_MASK_0_RESET_MASK                        _MK_MASK_CONST(0x7f0777)
#define AOPM_POWER_CFG_MASK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_READ_MASK                         _MK_MASK_CONST(0x7f0777)
#define AOPM_POWER_CFG_MASK_0_WRITE_MASK                        _MK_MASK_CONST(0x7f0777)
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_SHIFT                    _MK_SHIFT_CONST(0)
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_FIELD                    _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFI_IDLE_SHIFT)
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_RANGE                    0:0
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_WOFFSET                  0x0
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_INIT_ENUM                        UNMASK
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_UNMASK                   _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_MASK                     _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_SHIFT                 _MK_SHIFT_CONST(1)
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_FIELD                 _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFI_STANDBY_SHIFT)
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_RANGE                 1:1
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_WOFFSET                       0x0
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_INIT_ENUM                     UNMASK
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_UNMASK                        _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_MASK                  _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_SHIFT                 _MK_SHIFT_CONST(2)
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_FIELD                 _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFI_DORMANT_SHIFT)
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_RANGE                 2:2
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_WOFFSET                       0x0
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_INIT_ENUM                     UNMASK
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_UNMASK                        _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_MASK                  _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_SHIFT                    _MK_SHIFT_CONST(4)
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_FIELD                    _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFE_IDLE_SHIFT)
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_RANGE                    4:4
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_WOFFSET                  0x0
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_DEFAULT                  _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_INIT_ENUM                        MASK
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_UNMASK                   _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_MASK                     _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_SHIFT                 _MK_SHIFT_CONST(5)
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_FIELD                 _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFE_STANDBY_SHIFT)
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_RANGE                 5:5
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_WOFFSET                       0x0
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_DEFAULT                       _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_INIT_ENUM                     MASK
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_UNMASK                        _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_MASK                  _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_SHIFT                 _MK_SHIFT_CONST(6)
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_FIELD                 _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFE_DORMANT_SHIFT)
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_RANGE                 6:6
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_WOFFSET                       0x0
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_DEFAULT                       _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_INIT_ENUM                     MASK
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_UNMASK                        _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_MASK                  _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_SHIFT                    _MK_SHIFT_CONST(8)
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_FIELD                    _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_TGT_IDLE_SHIFT)
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_RANGE                    8:8
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_WOFFSET                  0x0
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_INIT_ENUM                        UNMASK
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_UNMASK                   _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_MASK                     _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_SHIFT                 _MK_SHIFT_CONST(9)
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_FIELD                 _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_TGT_STANDBY_SHIFT)
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_RANGE                 9:9
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_WOFFSET                       0x0
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_INIT_ENUM                     UNMASK
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_UNMASK                        _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_MASK                  _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_SHIFT                 _MK_SHIFT_CONST(10)
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_FIELD                 _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_TGT_DORMANT_SHIFT)
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_RANGE                 10:10
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_WOFFSET                       0x0
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_INIT_ENUM                     UNMASK
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_UNMASK                        _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_MASK                  _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_RAM_PPG_SHIFT                     _MK_SHIFT_CONST(16)
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_FIELD                     _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_RAM_PPG_SHIFT)
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_RANGE                     16:16
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_WOFFSET                   0x0
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_INIT_ENUM                 UNMASK
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_UNMASK                    _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_RAM_PPG_MASK                      _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_RAM_RET_SHIFT                     _MK_SHIFT_CONST(17)
#define AOPM_POWER_CFG_MASK_0_RAM_RET_FIELD                     _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_RAM_RET_SHIFT)
#define AOPM_POWER_CFG_MASK_0_RAM_RET_RANGE                     17:17
#define AOPM_POWER_CFG_MASK_0_RAM_RET_WOFFSET                   0x0
#define AOPM_POWER_CFG_MASK_0_RAM_RET_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAM_RET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_RAM_RET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAM_RET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAM_RET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAM_RET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_RAM_RET_INIT_ENUM                 UNMASK
#define AOPM_POWER_CFG_MASK_0_RAM_RET_UNMASK                    _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_RAM_RET_MASK                      _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_SHIFT                 _MK_SHIFT_CONST(18)
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_FIELD                 _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_SHIFT)
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_RANGE                 18:18
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_WOFFSET                       0x0
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_INIT_ENUM                     ENABLE
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_DISABLE                       _MK_ENUM_CONST(1)
#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_ENABLE                        _MK_ENUM_CONST(0)

#define AOPM_POWER_CFG_MASK_0_RAIL_RET_SHIFT                    _MK_SHIFT_CONST(19)
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_FIELD                    _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_RAIL_RET_SHIFT)
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_RANGE                    19:19
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_WOFFSET                  0x0
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_INIT_ENUM                        UNMASK
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_UNMASK                   _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_RAIL_RET_MASK                     _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_SHIFT                        _MK_SHIFT_CONST(20)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_FIELD                        _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_SHIFT)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_RANGE                        20:20
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_WOFFSET                      0x0
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_INIT_ENUM                    OFF
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_OFF                  _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_ON                   _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_SHIFT                        _MK_SHIFT_CONST(21)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_FIELD                        _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_SHIFT)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_RANGE                        21:21
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_WOFFSET                      0x0
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_INIT_ENUM                    OFF
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_OFF                  _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_ON                   _MK_ENUM_CONST(1)

#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_SHIFT                        _MK_SHIFT_CONST(22)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_FIELD                        _MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_SHIFT)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_RANGE                        22:22
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_WOFFSET                      0x0
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_DEFAULT                      _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_INIT_ENUM                    ON
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_OFF                  _MK_ENUM_CONST(0)
#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_ON                   _MK_ENUM_CONST(1)


// Register AOPM_TGT_PWR_CFG_ORIDE_0
#define AOPM_TGT_PWR_CFG_ORIDE_0                        _MK_ADDR_CONST(0x1c)
#define AOPM_TGT_PWR_CFG_ORIDE_0_SECURE                         0x0
#define AOPM_TGT_PWR_CFG_ORIDE_0_DUAL                   0x0
#define AOPM_TGT_PWR_CFG_ORIDE_0_SCR                    SCR_PRIVATE_0
#define AOPM_TGT_PWR_CFG_ORIDE_0_WORD_COUNT                     0x1
#define AOPM_TGT_PWR_CFG_ORIDE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RESET_MASK                     _MK_MASK_CONST(0x800000ff)
#define AOPM_TGT_PWR_CFG_ORIDE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_READ_MASK                      _MK_MASK_CONST(0x800000ff)
#define AOPM_TGT_PWR_CFG_ORIDE_0_WRITE_MASK                     _MK_MASK_CONST(0x800000ff)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_SHIFT                    _MK_SHIFT_CONST(0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_FIELD                    _MK_FIELD_CONST(0xf, AOPM_TGT_PWR_CFG_ORIDE_0_STATE_SHIFT)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_RANGE                    3:0
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_WOFFSET                  0x0
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_INIT_ENUM                        ACTIVE
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_ACTIVE                   _MK_ENUM_CONST(0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_IDLE                     _MK_ENUM_CONST(1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_STANDBY                  _MK_ENUM_CONST(2)
#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_DORMANT                  _MK_ENUM_CONST(3)

#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_SHIFT                  _MK_SHIFT_CONST(4)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_FIELD                  _MK_FIELD_CONST(0x1, AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_SHIFT)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_RANGE                  4:4
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_WOFFSET                        0x0
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_INIT_ENUM                      DISABLE
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_DISABLE                        _MK_ENUM_CONST(0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_ENABLE                 _MK_ENUM_CONST(1)

#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_SHIFT                  _MK_SHIFT_CONST(5)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_FIELD                  _MK_FIELD_CONST(0x1, AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_SHIFT)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_RANGE                  5:5
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_WOFFSET                        0x0
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_INIT_ENUM                      DISABLE
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_DISABLE                        _MK_ENUM_CONST(0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_ENABLE                 _MK_ENUM_CONST(1)

#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_SHIFT                 _MK_SHIFT_CONST(6)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_FIELD                 _MK_FIELD_CONST(0x1, AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_SHIFT)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_RANGE                 6:6
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_WOFFSET                       0x0
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_INIT_ENUM                     DISABLE
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_DISABLE                       _MK_ENUM_CONST(0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_ENABLE                        _MK_ENUM_CONST(1)

#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_SHIFT                   _MK_SHIFT_CONST(7)
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_FIELD                   _MK_FIELD_CONST(0x1, AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_SHIFT)
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_RANGE                   7:7
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_WOFFSET                 0x0
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_INIT_ENUM                       DISABLE
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_DISABLE                 _MK_ENUM_CONST(0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_ENABLE                  _MK_ENUM_CONST(1)

#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_SHIFT                 _MK_SHIFT_CONST(31)
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_FIELD                 _MK_FIELD_CONST(0x1, AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_SHIFT)
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_RANGE                 31:31
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_WOFFSET                       0x0
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_INIT_ENUM                     DISABLE
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_DISABLE                       _MK_ENUM_CONST(0)
#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_ENABLE                        _MK_ENUM_CONST(1)


// Register AOPM_PWR_STATUS_0
#define AOPM_PWR_STATUS_0                       _MK_ADDR_CONST(0x20)
#define AOPM_PWR_STATUS_0_SECURE                        0x0
#define AOPM_PWR_STATUS_0_DUAL                  0x0
#define AOPM_PWR_STATUS_0_SCR                   0
#define AOPM_PWR_STATUS_0_WORD_COUNT                    0x1
#define AOPM_PWR_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x7ffffc0)
#define AOPM_PWR_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7ffffc0)
#define AOPM_PWR_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_TCM_RET_SHIFT                 _MK_SHIFT_CONST(6)
#define AOPM_PWR_STATUS_0_TCM_RET_FIELD                 _MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_TCM_RET_SHIFT)
#define AOPM_PWR_STATUS_0_TCM_RET_RANGE                 6:6
#define AOPM_PWR_STATUS_0_TCM_RET_WOFFSET                       0x0
#define AOPM_PWR_STATUS_0_TCM_RET_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_TCM_RET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_TCM_RET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_TCM_RET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_TCM_RET_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_TCM_RET_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_TCM_RET_INIT_ENUM                     ACTIVE
#define AOPM_PWR_STATUS_0_TCM_RET_ACTIVE                        _MK_ENUM_CONST(0)
#define AOPM_PWR_STATUS_0_TCM_RET_RET                   _MK_ENUM_CONST(1)

#define AOPM_PWR_STATUS_0_RAIL_SHIFT                    _MK_SHIFT_CONST(7)
#define AOPM_PWR_STATUS_0_RAIL_FIELD                    _MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_RAIL_SHIFT)
#define AOPM_PWR_STATUS_0_RAIL_RANGE                    7:7
#define AOPM_PWR_STATUS_0_RAIL_WOFFSET                  0x0
#define AOPM_PWR_STATUS_0_RAIL_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_RAIL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_RAIL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_RAIL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_RAIL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_RAIL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_RAIL_INIT_ENUM                        ACTIVE
#define AOPM_PWR_STATUS_0_RAIL_ACTIVE                   _MK_ENUM_CONST(0)
#define AOPM_PWR_STATUS_0_RAIL_RET                      _MK_ENUM_CONST(1)

#define AOPM_PWR_STATUS_0_STATE_SHIFT                   _MK_SHIFT_CONST(8)
#define AOPM_PWR_STATUS_0_STATE_FIELD                   _MK_FIELD_CONST(0xf, AOPM_PWR_STATUS_0_STATE_SHIFT)
#define AOPM_PWR_STATUS_0_STATE_RANGE                   11:8
#define AOPM_PWR_STATUS_0_STATE_WOFFSET                 0x0
#define AOPM_PWR_STATUS_0_STATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_STATE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define AOPM_PWR_STATUS_0_STATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_STATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_STATE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_STATE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_STATE_INIT_ENUM                       ACTIVE
#define AOPM_PWR_STATUS_0_STATE_ACTIVE                  _MK_ENUM_CONST(0)
#define AOPM_PWR_STATUS_0_STATE_IDLE_SHALLOW                    _MK_ENUM_CONST(1)
#define AOPM_PWR_STATUS_0_STATE_IDLE_DEEP                       _MK_ENUM_CONST(2)
#define AOPM_PWR_STATUS_0_STATE_STANDBY_SHALLOW                 _MK_ENUM_CONST(3)
#define AOPM_PWR_STATUS_0_STATE_STANDBY_DEEP                    _MK_ENUM_CONST(4)
#define AOPM_PWR_STATUS_0_STATE_DORMANT_SHALLOW                 _MK_ENUM_CONST(5)
#define AOPM_PWR_STATUS_0_STATE_DORMANT_DEEP                    _MK_ENUM_CONST(6)

#define AOPM_PWR_STATUS_0_EXIT_CAUSE_SHIFT                      _MK_SHIFT_CONST(12)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_FIELD                      _MK_FIELD_CONST(0xf, AOPM_PWR_STATUS_0_EXIT_CAUSE_SHIFT)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_RANGE                      15:12
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_WOFFSET                    0x0
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_INIT_ENUM                  NONE
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_NONE                       _MK_ENUM_CONST(0)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_SWTRIG                     _MK_ENUM_CONST(1)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_DMA_ACTIVE                 _MK_ENUM_CONST(2)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_IRQ                        _MK_ENUM_CONST(3)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_FIQ                        _MK_ENUM_CONST(4)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_WAKE                       _MK_ENUM_CONST(5)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_RTC_ALARM                  _MK_ENUM_CONST(6)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_DBG_TIMEOUT                        _MK_ENUM_CONST(7)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_WFI                        _MK_ENUM_CONST(8)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_WFE                        _MK_ENUM_CONST(9)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_CLKSTOPPED                 _MK_ENUM_CONST(10)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_SC7                        _MK_ENUM_CONST(11)
#define AOPM_PWR_STATUS_0_EXIT_CAUSE_AXIP                       _MK_ENUM_CONST(12)

#define AOPM_PWR_STATUS_0_LAST_LP_STATE_SHIFT                   _MK_SHIFT_CONST(16)
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_FIELD                   _MK_FIELD_CONST(0x3, AOPM_PWR_STATUS_0_LAST_LP_STATE_SHIFT)
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_RANGE                   17:16
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_WOFFSET                 0x0
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_INIT_ENUM                       NONE
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_NONE                    _MK_ENUM_CONST(0)
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_IDLE                    _MK_ENUM_CONST(1)
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_STANDBY                 _MK_ENUM_CONST(2)
#define AOPM_PWR_STATUS_0_LAST_LP_STATE_DORMANT                 _MK_ENUM_CONST(3)

#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_SHIFT                     _MK_SHIFT_CONST(18)
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_FIELD                     _MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_SHIFT)
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_RANGE                     18:18
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_WOFFSET                   0x0
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_INIT_ENUM                 FALSE
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_FALSE                     _MK_ENUM_CONST(0)
#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_TRUE                      _MK_ENUM_CONST(1)

#define AOPM_PWR_STATUS_0_EXIT_STATUS_SHIFT                     _MK_SHIFT_CONST(19)
#define AOPM_PWR_STATUS_0_EXIT_STATUS_FIELD                     _MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_EXIT_STATUS_SHIFT)
#define AOPM_PWR_STATUS_0_EXIT_STATUS_RANGE                     19:19
#define AOPM_PWR_STATUS_0_EXIT_STATUS_WOFFSET                   0x0
#define AOPM_PWR_STATUS_0_EXIT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_EXIT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_EXIT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_EXIT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_EXIT_STATUS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_EXIT_STATUS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_EXIT_STATUS_INIT_ENUM                 DONE
#define AOPM_PWR_STATUS_0_EXIT_STATUS_DONE                      _MK_ENUM_CONST(0)
#define AOPM_PWR_STATUS_0_EXIT_STATUS_EXITING                   _MK_ENUM_CONST(1)

#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_SHIFT                     _MK_SHIFT_CONST(20)
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_FIELD                     _MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_ACTIVE_TYPE_SHIFT)
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_RANGE                     20:20
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_WOFFSET                   0x0
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_INIT_ENUM                 ACTIVE
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_ACTIVE                    _MK_ENUM_CONST(0)
#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_ACTIVE_IRQFIQ                     _MK_ENUM_CONST(1)

#define AOPM_PWR_STATUS_0_nWFI_SHIFT                    _MK_SHIFT_CONST(21)
#define AOPM_PWR_STATUS_0_nWFI_FIELD                    _MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_nWFI_SHIFT)
#define AOPM_PWR_STATUS_0_nWFI_RANGE                    21:21
#define AOPM_PWR_STATUS_0_nWFI_WOFFSET                  0x0
#define AOPM_PWR_STATUS_0_nWFI_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nWFI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_nWFI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nWFI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nWFI_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nWFI_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define AOPM_PWR_STATUS_0_nWFE_SHIFT                    _MK_SHIFT_CONST(22)
#define AOPM_PWR_STATUS_0_nWFE_FIELD                    _MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_nWFE_SHIFT)
#define AOPM_PWR_STATUS_0_nWFE_RANGE                    22:22
#define AOPM_PWR_STATUS_0_nWFE_WOFFSET                  0x0
#define AOPM_PWR_STATUS_0_nWFE_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nWFE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_nWFE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nWFE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nWFE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nWFE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_SHIFT                        _MK_SHIFT_CONST(23)
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_FIELD                        _MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_SKIPPING_RAILRET_SHIFT)
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_RANGE                        23:23
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_WOFFSET                      0x0
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_INIT_ENUM                    FALSE
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_FALSE                        _MK_ENUM_CONST(0)
#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_TRUE                 _MK_ENUM_CONST(1)

#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_SHIFT                  _MK_SHIFT_CONST(24)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_FIELD                  _MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_LAST_LP_DID_PG_SHIFT)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_RANGE                  24:24
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_WOFFSET                        0x0
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_INIT_ENUM                      FALSE
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_FALSE                  _MK_ENUM_CONST(0)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_TRUE                   _MK_ENUM_CONST(1)

#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_SHIFT                 _MK_SHIFT_CONST(25)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_FIELD                 _MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_LAST_LP_DID_RST_SHIFT)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_RANGE                 25:25
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_WOFFSET                       0x0
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_INIT_ENUM                     FALSE
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_FALSE                 _MK_ENUM_CONST(0)
#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_TRUE                  _MK_ENUM_CONST(1)

#define AOPM_PWR_STATUS_0_nCLKSTOPPED_SHIFT                     _MK_SHIFT_CONST(26)
#define AOPM_PWR_STATUS_0_nCLKSTOPPED_FIELD                     _MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_nCLKSTOPPED_SHIFT)
#define AOPM_PWR_STATUS_0_nCLKSTOPPED_RANGE                     26:26
#define AOPM_PWR_STATUS_0_nCLKSTOPPED_WOFFSET                   0x0
#define AOPM_PWR_STATUS_0_nCLKSTOPPED_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nCLKSTOPPED_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_PWR_STATUS_0_nCLKSTOPPED_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nCLKSTOPPED_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nCLKSTOPPED_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_PWR_STATUS_0_nCLKSTOPPED_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register AOPM_DBG_STATUS_0
#define AOPM_DBG_STATUS_0                       _MK_ADDR_CONST(0x24)
#define AOPM_DBG_STATUS_0_SECURE                        0x0
#define AOPM_DBG_STATUS_0_DUAL                  0x0
#define AOPM_DBG_STATUS_0_SCR                   0
#define AOPM_DBG_STATUS_0_WORD_COUNT                    0x1
#define AOPM_DBG_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x1ffff3)
#define AOPM_DBG_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x1ffff3)
#define AOPM_DBG_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_SHIFT                 _MK_SHIFT_CONST(0)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_FIELD                 _MK_FIELD_CONST(0x3, AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_SHIFT)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_RANGE                 1:0
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_WOFFSET                       0x0
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_INIT_ENUM                     NONE
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_NONE                  _MK_ENUM_CONST(0)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_IDLE                  _MK_ENUM_CONST(1)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_STANDBY                       _MK_ENUM_CONST(2)
#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_DORMANT                       _MK_ENUM_CONST(3)

#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_SHIFT                 _MK_SHIFT_CONST(4)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_FIELD                 _MK_FIELD_CONST(0xf, AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_SHIFT)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_RANGE                 7:4
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_WOFFSET                       0x0
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_INIT_ENUM                     PMI_ACTIVE
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PMI_ACTIVE                    _MK_ENUM_CONST(0)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PMI_CARREQ_H                  _MK_ENUM_CONST(1)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PMI_CARREQ_L                  _MK_ENUM_CONST(2)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PMI_IDLE_SHALLOW                      _MK_ENUM_CONST(3)
#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PMI_IDLE_DEEP                 _MK_ENUM_CONST(4)

#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_SHIFT                      _MK_SHIFT_CONST(8)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_FIELD                      _MK_FIELD_CONST(0xf, AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_SHIFT)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_RANGE                      11:8
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_WOFFSET                    0x0
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_INIT_ENUM                  PMS_ACTIVE
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_ACTIVE                 _MK_ENUM_CONST(0)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_CARREQ_H                       _MK_ENUM_CONST(1)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_CARREQ_L                       _MK_ENUM_CONST(2)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_RET_WAIT                       _MK_ENUM_CONST(3)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_RAMRET_IN                      _MK_ENUM_CONST(4)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_RAMRET_OUT                     _MK_ENUM_CONST(5)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_RAILRET                        _MK_ENUM_CONST(6)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_STANDBY_SHALLOW                        _MK_ENUM_CONST(7)
#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_STANDBY_DEEP                   _MK_ENUM_CONST(8)

#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_SHIFT                      _MK_SHIFT_CONST(12)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_FIELD                      _MK_FIELD_CONST(0x1f, AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_SHIFT)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_RANGE                      16:12
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_WOFFSET                    0x0
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_INIT_ENUM                  PMD_ACTIVE
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_ACTIVE                 _MK_ENUM_CONST(0)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_CARREQ_H                       _MK_ENUM_CONST(1)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_CARREQ_L                       _MK_ENUM_CONST(2)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_RAMRET_IN                      _MK_ENUM_CONST(4)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_RAILRET                        _MK_ENUM_CONST(5)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_RST_ASRT                       _MK_ENUM_CONST(6)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_PG                     _MK_ENUM_CONST(7)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_OSCOFF                 _MK_ENUM_CONST(8)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_OSCON                  _MK_ENUM_CONST(9)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_UPG                    _MK_ENUM_CONST(10)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_RST_DEASRT                     _MK_ENUM_CONST(11)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_RAMRET_OUT                     _MK_ENUM_CONST(12)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_DORMANT_S                      _MK_ENUM_CONST(13)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_DORMANT_D                      _MK_ENUM_CONST(14)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_NOC_IDLE_ACK_H                 _MK_ENUM_CONST(15)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_NOC_IDLE_H                     _MK_ENUM_CONST(16)
#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_NOC_IDLE_ACK_L                 _MK_ENUM_CONST(17)

#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_SHIFT                       _MK_SHIFT_CONST(17)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_FIELD                       _MK_FIELD_CONST(0xf, AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_SHIFT)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_RANGE                       20:17
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_WOFFSET                     0x0
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_INIT_ENUM                   PMA_ACTIVE
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PMA_ACTIVE                  _MK_ENUM_CONST(0)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PMA_CARREQ_H                        _MK_ENUM_CONST(1)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PMA_CARREQ_L                        _MK_ENUM_CONST(2)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PMA_WAIT_LP                 _MK_ENUM_CONST(3)
#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PMA_ACT_IRQFIQ                      _MK_ENUM_CONST(4)


// Register AOPM_DBG_FEATURES_0
#define AOPM_DBG_FEATURES_0                     _MK_ADDR_CONST(0x28)
#define AOPM_DBG_FEATURES_0_SECURE                      0x0
#define AOPM_DBG_FEATURES_0_DUAL                        0x0
#define AOPM_DBG_FEATURES_0_SCR                         SCR_PRIVATE_0
#define AOPM_DBG_FEATURES_0_WORD_COUNT                  0x1
#define AOPM_DBG_FEATURES_0_RESET_VAL                   _MK_MASK_CONST(0x1c4)
#define AOPM_DBG_FEATURES_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
#define AOPM_DBG_FEATURES_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
#define AOPM_DBG_FEATURES_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_SHIFT                     _MK_SHIFT_CONST(0)
#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_FIELD                     _MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_SHIFT)
#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_RANGE                     0:0
#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_WOFFSET                   0x0
#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define AOPM_DBG_FEATURES_0_FORCE_START_SHIFT                   _MK_SHIFT_CONST(1)
#define AOPM_DBG_FEATURES_0_FORCE_START_FIELD                   _MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_FORCE_START_SHIFT)
#define AOPM_DBG_FEATURES_0_FORCE_START_RANGE                   1:1
#define AOPM_DBG_FEATURES_0_FORCE_START_WOFFSET                 0x0
#define AOPM_DBG_FEATURES_0_FORCE_START_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FORCE_START_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_FORCE_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FORCE_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FORCE_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FORCE_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_SHIFT                    _MK_SHIFT_CONST(2)
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_FIELD                    _MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_SHIFT)
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_RANGE                    2:2
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_WOFFSET                  0x0
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_DEFAULT                  _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_INIT_ENUM                        ENABLE
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_DISABLE                  _MK_ENUM_CONST(0)
#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_ENABLE                   _MK_ENUM_CONST(1)

#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_SHIFT                        _MK_SHIFT_CONST(3)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_FIELD                        _MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_SHIFT)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_RANGE                        3:3
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_WOFFSET                      0x0
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_INIT_ENUM                    DISABLE
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_DISABLE                      _MK_ENUM_CONST(0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_ENABLE                       _MK_ENUM_CONST(1)

#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_SHIFT                        _MK_SHIFT_CONST(4)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_FIELD                        _MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_SHIFT)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_RANGE                        4:4
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_WOFFSET                      0x0
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_INIT_ENUM                    DISABLE
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_DISABLE                      _MK_ENUM_CONST(0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_ENABLE                       _MK_ENUM_CONST(1)

#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_SHIFT                    _MK_SHIFT_CONST(5)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_FIELD                    _MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_SHIFT)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_RANGE                    5:5
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_WOFFSET                  0x0
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_INIT_ENUM                        DISABLE
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_DISABLE                  _MK_ENUM_CONST(0)
#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_ENABLE                   _MK_ENUM_CONST(1)

#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_SHIFT                     _MK_SHIFT_CONST(6)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_FIELD                     _MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_SHIFT)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_RANGE                     6:6
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_WOFFSET                   0x0
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_DEFAULT                   _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_INIT_ENUM                 INCLUDE
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_EXCLUDE                   _MK_ENUM_CONST(0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_INCLUDE                   _MK_ENUM_CONST(1)

#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_SHIFT                     _MK_SHIFT_CONST(7)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_FIELD                     _MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_SHIFT)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_RANGE                     7:7
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_WOFFSET                   0x0
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_DEFAULT                   _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_INIT_ENUM                 INCLUDE
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_EXCLUDE                   _MK_ENUM_CONST(0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_INCLUDE                   _MK_ENUM_CONST(1)

#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_SHIFT                 _MK_SHIFT_CONST(8)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_FIELD                 _MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_SHIFT)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_RANGE                 8:8
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_WOFFSET                       0x0
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_DEFAULT                       _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_INIT_ENUM                     INCLUDE
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_EXCLUDE                       _MK_ENUM_CONST(0)
#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_INCLUDE                       _MK_ENUM_CONST(1)

#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_SHIFT                        _MK_SHIFT_CONST(9)
#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_FIELD                        _MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_SHIFT)
#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_RANGE                        9:9
#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_WOFFSET                      0x0
#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register AOPM_EXIT_MASK_0
#define AOPM_EXIT_MASK_0                        _MK_ADDR_CONST(0x2c)
#define AOPM_EXIT_MASK_0_SECURE                         0x0
#define AOPM_EXIT_MASK_0_DUAL                   0x0
#define AOPM_EXIT_MASK_0_SCR                    SCR_SHARED_0
#define AOPM_EXIT_MASK_0_WORD_COUNT                     0x1
#define AOPM_EXIT_MASK_0_RESET_VAL                      _MK_MASK_CONST(0xa0)
#define AOPM_EXIT_MASK_0_RESET_MASK                     _MK_MASK_CONST(0x3ff)
#define AOPM_EXIT_MASK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_READ_MASK                      _MK_MASK_CONST(0x3ff)
#define AOPM_EXIT_MASK_0_WRITE_MASK                     _MK_MASK_CONST(0x3ff)
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_SHIFT                       _MK_SHIFT_CONST(0)
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_FIELD                       _MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_DMA_ACTIVE_SHIFT)
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_RANGE                       0:0
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_WOFFSET                     0x0
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_INIT_ENUM                   UNMASK
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_UNMASK                      _MK_ENUM_CONST(0)
#define AOPM_EXIT_MASK_0_DMA_ACTIVE_MASK                        _MK_ENUM_CONST(1)

#define AOPM_EXIT_MASK_0_IRQ_SHIFT                      _MK_SHIFT_CONST(1)
#define AOPM_EXIT_MASK_0_IRQ_FIELD                      _MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_IRQ_SHIFT)
#define AOPM_EXIT_MASK_0_IRQ_RANGE                      1:1
#define AOPM_EXIT_MASK_0_IRQ_WOFFSET                    0x0
#define AOPM_EXIT_MASK_0_IRQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_IRQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_IRQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_IRQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_IRQ_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_IRQ_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_IRQ_INIT_ENUM                  UNMASK
#define AOPM_EXIT_MASK_0_IRQ_UNMASK                     _MK_ENUM_CONST(0)
#define AOPM_EXIT_MASK_0_IRQ_MASK                       _MK_ENUM_CONST(1)

#define AOPM_EXIT_MASK_0_FIQ_SHIFT                      _MK_SHIFT_CONST(2)
#define AOPM_EXIT_MASK_0_FIQ_FIELD                      _MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_FIQ_SHIFT)
#define AOPM_EXIT_MASK_0_FIQ_RANGE                      2:2
#define AOPM_EXIT_MASK_0_FIQ_WOFFSET                    0x0
#define AOPM_EXIT_MASK_0_FIQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_FIQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_FIQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_FIQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_FIQ_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_FIQ_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_FIQ_INIT_ENUM                  UNMASK
#define AOPM_EXIT_MASK_0_FIQ_UNMASK                     _MK_ENUM_CONST(0)
#define AOPM_EXIT_MASK_0_FIQ_MASK                       _MK_ENUM_CONST(1)

#define AOPM_EXIT_MASK_0_T0_WAKE_SHIFT                  _MK_SHIFT_CONST(3)
#define AOPM_EXIT_MASK_0_T0_WAKE_FIELD                  _MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_T0_WAKE_SHIFT)
#define AOPM_EXIT_MASK_0_T0_WAKE_RANGE                  3:3
#define AOPM_EXIT_MASK_0_T0_WAKE_WOFFSET                        0x0
#define AOPM_EXIT_MASK_0_T0_WAKE_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_T0_WAKE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_T0_WAKE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_T0_WAKE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_T0_WAKE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_T0_WAKE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_T0_WAKE_INIT_ENUM                      UNMASK
#define AOPM_EXIT_MASK_0_T0_WAKE_UNMASK                 _MK_ENUM_CONST(0)
#define AOPM_EXIT_MASK_0_T0_WAKE_MASK                   _MK_ENUM_CONST(1)

#define AOPM_EXIT_MASK_0_RTC_ALARM_SHIFT                        _MK_SHIFT_CONST(4)
#define AOPM_EXIT_MASK_0_RTC_ALARM_FIELD                        _MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_RTC_ALARM_SHIFT)
#define AOPM_EXIT_MASK_0_RTC_ALARM_RANGE                        4:4
#define AOPM_EXIT_MASK_0_RTC_ALARM_WOFFSET                      0x0
#define AOPM_EXIT_MASK_0_RTC_ALARM_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_RTC_ALARM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_RTC_ALARM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_RTC_ALARM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_RTC_ALARM_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_RTC_ALARM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_RTC_ALARM_INIT_ENUM                    UNMASK
#define AOPM_EXIT_MASK_0_RTC_ALARM_UNMASK                       _MK_ENUM_CONST(0)
#define AOPM_EXIT_MASK_0_RTC_ALARM_MASK                 _MK_ENUM_CONST(1)

#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_SHIFT                      _MK_SHIFT_CONST(5)
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_FIELD                      _MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_DBG_TIMEOUT_SHIFT)
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_RANGE                      5:5
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_WOFFSET                    0x0
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_DEFAULT                    _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_INIT_ENUM                  MASK
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_UNMASK                     _MK_ENUM_CONST(0)
#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_MASK                       _MK_ENUM_CONST(1)

#define AOPM_EXIT_MASK_0_WFI_SHIFT                      _MK_SHIFT_CONST(6)
#define AOPM_EXIT_MASK_0_WFI_FIELD                      _MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_WFI_SHIFT)
#define AOPM_EXIT_MASK_0_WFI_RANGE                      6:6
#define AOPM_EXIT_MASK_0_WFI_WOFFSET                    0x0
#define AOPM_EXIT_MASK_0_WFI_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_WFI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_WFI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_WFI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_WFI_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_WFI_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_WFI_INIT_ENUM                  UNMASK
#define AOPM_EXIT_MASK_0_WFI_UNMASK                     _MK_ENUM_CONST(0)
#define AOPM_EXIT_MASK_0_WFI_MASK                       _MK_ENUM_CONST(1)

#define AOPM_EXIT_MASK_0_WFE_SHIFT                      _MK_SHIFT_CONST(7)
#define AOPM_EXIT_MASK_0_WFE_FIELD                      _MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_WFE_SHIFT)
#define AOPM_EXIT_MASK_0_WFE_RANGE                      7:7
#define AOPM_EXIT_MASK_0_WFE_WOFFSET                    0x0
#define AOPM_EXIT_MASK_0_WFE_DEFAULT                    _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_WFE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_WFE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_WFE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_WFE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_WFE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_WFE_INIT_ENUM                  MASK
#define AOPM_EXIT_MASK_0_WFE_UNMASK                     _MK_ENUM_CONST(0)
#define AOPM_EXIT_MASK_0_WFE_MASK                       _MK_ENUM_CONST(1)

#define AOPM_EXIT_MASK_0_CLKSTOPPED_SHIFT                       _MK_SHIFT_CONST(8)
#define AOPM_EXIT_MASK_0_CLKSTOPPED_FIELD                       _MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_CLKSTOPPED_SHIFT)
#define AOPM_EXIT_MASK_0_CLKSTOPPED_RANGE                       8:8
#define AOPM_EXIT_MASK_0_CLKSTOPPED_WOFFSET                     0x0
#define AOPM_EXIT_MASK_0_CLKSTOPPED_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_CLKSTOPPED_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_CLKSTOPPED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_CLKSTOPPED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_CLKSTOPPED_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_CLKSTOPPED_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_CLKSTOPPED_INIT_ENUM                   UNMASK
#define AOPM_EXIT_MASK_0_CLKSTOPPED_UNMASK                      _MK_ENUM_CONST(0)
#define AOPM_EXIT_MASK_0_CLKSTOPPED_MASK                        _MK_ENUM_CONST(1)

#define AOPM_EXIT_MASK_0_AXIP_SHIFT                     _MK_SHIFT_CONST(9)
#define AOPM_EXIT_MASK_0_AXIP_FIELD                     _MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_AXIP_SHIFT)
#define AOPM_EXIT_MASK_0_AXIP_RANGE                     9:9
#define AOPM_EXIT_MASK_0_AXIP_WOFFSET                   0x0
#define AOPM_EXIT_MASK_0_AXIP_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_AXIP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_AXIP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_AXIP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_AXIP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_EXIT_MASK_0_AXIP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_EXIT_MASK_0_AXIP_INIT_ENUM                 UNMASK
#define AOPM_EXIT_MASK_0_AXIP_UNMASK                    _MK_ENUM_CONST(0)
#define AOPM_EXIT_MASK_0_AXIP_MASK                      _MK_ENUM_CONST(1)


// Register AOPM_BURST_CLK_0
#define AOPM_BURST_CLK_0                        _MK_ADDR_CONST(0x30)
#define AOPM_BURST_CLK_0_SECURE                         0x0
#define AOPM_BURST_CLK_0_DUAL                   0x0
#define AOPM_BURST_CLK_0_SCR                    SCR_SHARED_0
#define AOPM_BURST_CLK_0_WORD_COUNT                     0x1
#define AOPM_BURST_CLK_0_RESET_VAL                      _MK_MASK_CONST(0x2)
#define AOPM_BURST_CLK_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define AOPM_BURST_CLK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_BURST_CLK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_BURST_CLK_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define AOPM_BURST_CLK_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define AOPM_BURST_CLK_0_BURST_CLK_EN_SHIFT                     _MK_SHIFT_CONST(0)
#define AOPM_BURST_CLK_0_BURST_CLK_EN_FIELD                     _MK_FIELD_CONST(0x1, AOPM_BURST_CLK_0_BURST_CLK_EN_SHIFT)
#define AOPM_BURST_CLK_0_BURST_CLK_EN_RANGE                     0:0
#define AOPM_BURST_CLK_0_BURST_CLK_EN_WOFFSET                   0x0
#define AOPM_BURST_CLK_0_BURST_CLK_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_BURST_CLK_0_BURST_CLK_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_BURST_CLK_0_BURST_CLK_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_BURST_CLK_0_BURST_CLK_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_BURST_CLK_0_BURST_CLK_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_BURST_CLK_0_BURST_CLK_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_BURST_CLK_0_BURST_CLK_EN_INIT_ENUM                 DISABLE
#define AOPM_BURST_CLK_0_BURST_CLK_EN_DISABLE                   _MK_ENUM_CONST(0)
#define AOPM_BURST_CLK_0_BURST_CLK_EN_ENABLE                    _MK_ENUM_CONST(1)

#define AOPM_BURST_CLK_0_BURST_LP_EN_SHIFT                      _MK_SHIFT_CONST(1)
#define AOPM_BURST_CLK_0_BURST_LP_EN_FIELD                      _MK_FIELD_CONST(0x1, AOPM_BURST_CLK_0_BURST_LP_EN_SHIFT)
#define AOPM_BURST_CLK_0_BURST_LP_EN_RANGE                      1:1
#define AOPM_BURST_CLK_0_BURST_LP_EN_WOFFSET                    0x0
#define AOPM_BURST_CLK_0_BURST_LP_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define AOPM_BURST_CLK_0_BURST_LP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_BURST_CLK_0_BURST_LP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_BURST_CLK_0_BURST_LP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_BURST_CLK_0_BURST_LP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_BURST_CLK_0_BURST_LP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_BURST_CLK_0_BURST_LP_EN_INIT_ENUM                  ENABLE
#define AOPM_BURST_CLK_0_BURST_LP_EN_DISABLE                    _MK_ENUM_CONST(0)
#define AOPM_BURST_CLK_0_BURST_LP_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register AOPM_ACTIRQFIQ_TO_ACT_0
#define AOPM_ACTIRQFIQ_TO_ACT_0                 _MK_ADDR_CONST(0x34)
#define AOPM_ACTIRQFIQ_TO_ACT_0_SECURE                  0x0
#define AOPM_ACTIRQFIQ_TO_ACT_0_DUAL                    0x0
#define AOPM_ACTIRQFIQ_TO_ACT_0_SCR                     SCR_SHARED_0
#define AOPM_ACTIRQFIQ_TO_ACT_0_WORD_COUNT                      0x1
#define AOPM_ACTIRQFIQ_TO_ACT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define AOPM_ACTIRQFIQ_TO_ACT_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_ACTIRQFIQ_TO_ACT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_ACTIRQFIQ_TO_ACT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define AOPM_ACTIRQFIQ_TO_ACT_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_ACTIRQFIQ_TO_ACT_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_SHIFT                        _MK_SHIFT_CONST(0)
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_FIELD                        _MK_FIELD_CONST(0x1, AOPM_ACTIRQFIQ_TO_ACT_0_EN_SHIFT)
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_RANGE                        0:0
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_WOFFSET                      0x0
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_DONE                 _MK_ENUM_CONST(0)
#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_PENDING                      _MK_ENUM_CONST(1)


// Register AOPM_CSITE_CFG_0
#define AOPM_CSITE_CFG_0                        _MK_ADDR_CONST(0x38)
#define AOPM_CSITE_CFG_0_SECURE                         0x0
#define AOPM_CSITE_CFG_0_DUAL                   0x0
#define AOPM_CSITE_CFG_0_SCR                    SCR_PRIVATE_0
#define AOPM_CSITE_CFG_0_WORD_COUNT                     0x1
#define AOPM_CSITE_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define AOPM_CSITE_CFG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_CSITE_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_CSITE_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_CSITE_CFG_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_CSITE_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_SHIFT                   _MK_SHIFT_CONST(0)
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_FIELD                   _MK_FIELD_CONST(0x1, AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_SHIFT)
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_RANGE                   0:0
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_WOFFSET                 0x0
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_INIT_ENUM                       FALSE
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_FALSE                   _MK_ENUM_CONST(0)
#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_TRUE                    _MK_ENUM_CONST(1)


// Register AOPM_R5_CFG_0
#define AOPM_R5_CFG_0                   _MK_ADDR_CONST(0x3c)
#define AOPM_R5_CFG_0_SECURE                    0x0
#define AOPM_R5_CFG_0_DUAL                      0x0
#define AOPM_R5_CFG_0_SCR                       SCR_PRIVATE_0
#define AOPM_R5_CFG_0_WORD_COUNT                        0x1
#define AOPM_R5_CFG_0_RESET_VAL                         _MK_MASK_CONST(0xa88)
#define AOPM_R5_CFG_0_RESET_MASK                        _MK_MASK_CONST(0xffffff8a)
#define AOPM_R5_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_READ_MASK                         _MK_MASK_CONST(0xffffff8a)
#define AOPM_R5_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0xffffff8a)
#define AOPM_R5_CFG_0_TEINIT_SHIFT                      _MK_SHIFT_CONST(1)
#define AOPM_R5_CFG_0_TEINIT_FIELD                      _MK_FIELD_CONST(0x1, AOPM_R5_CFG_0_TEINIT_SHIFT)
#define AOPM_R5_CFG_0_TEINIT_RANGE                      1:1
#define AOPM_R5_CFG_0_TEINIT_WOFFSET                    0x0
#define AOPM_R5_CFG_0_TEINIT_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_TEINIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_R5_CFG_0_TEINIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_TEINIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_TEINIT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_TEINIT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_R5_CFG_0_TEINIT_INIT_ENUM                  ARM
#define AOPM_R5_CFG_0_TEINIT_ARM                        _MK_ENUM_CONST(0)
#define AOPM_R5_CFG_0_TEINIT_THUMB                      _MK_ENUM_CONST(1)

#define AOPM_R5_CFG_0_INITPPX_SHIFT                     _MK_SHIFT_CONST(3)
#define AOPM_R5_CFG_0_INITPPX_FIELD                     _MK_FIELD_CONST(0x1, AOPM_R5_CFG_0_INITPPX_SHIFT)
#define AOPM_R5_CFG_0_INITPPX_RANGE                     3:3
#define AOPM_R5_CFG_0_INITPPX_WOFFSET                   0x0
#define AOPM_R5_CFG_0_INITPPX_DEFAULT                   _MK_MASK_CONST(0x1)
#define AOPM_R5_CFG_0_INITPPX_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_R5_CFG_0_INITPPX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_INITPPX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_INITPPX_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_INITPPX_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_R5_CFG_0_INITPPX_INIT_ENUM                 ENABLE
#define AOPM_R5_CFG_0_INITPPX_DISABLE                   _MK_ENUM_CONST(0)
#define AOPM_R5_CFG_0_INITPPX_ENABLE                    _MK_ENUM_CONST(1)

#define AOPM_R5_CFG_0_PPXSIZE_SHIFT                     _MK_SHIFT_CONST(7)
#define AOPM_R5_CFG_0_PPXSIZE_FIELD                     _MK_FIELD_CONST(0x1f, AOPM_R5_CFG_0_PPXSIZE_SHIFT)
#define AOPM_R5_CFG_0_PPXSIZE_RANGE                     11:7
#define AOPM_R5_CFG_0_PPXSIZE_WOFFSET                   0x0
#define AOPM_R5_CFG_0_PPXSIZE_DEFAULT                   _MK_MASK_CONST(0x15)
#define AOPM_R5_CFG_0_PPXSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define AOPM_R5_CFG_0_PPXSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_PPXSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_PPXSIZE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_PPXSIZE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define AOPM_R5_CFG_0_PPXBASE_SHIFT                     _MK_SHIFT_CONST(12)
#define AOPM_R5_CFG_0_PPXBASE_FIELD                     _MK_FIELD_CONST(0xfffff, AOPM_R5_CFG_0_PPXBASE_SHIFT)
#define AOPM_R5_CFG_0_PPXBASE_RANGE                     31:12
#define AOPM_R5_CFG_0_PPXBASE_WOFFSET                   0x0
#define AOPM_R5_CFG_0_PPXBASE_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_PPXBASE_DEFAULT_MASK                      _MK_MASK_CONST(0xfffff)
#define AOPM_R5_CFG_0_PPXBASE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_PPXBASE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_PPXBASE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_R5_CFG_0_PPXBASE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register AOPM_R5_CTRL_0
#define AOPM_R5_CTRL_0                  _MK_ADDR_CONST(0x40)
#define AOPM_R5_CTRL_0_SECURE                   0x0
#define AOPM_R5_CTRL_0_DUAL                     0x0
#define AOPM_R5_CTRL_0_SCR                      SCR_PRIVATE_0
#define AOPM_R5_CTRL_0_WORD_COUNT                       0x1
#define AOPM_R5_CTRL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define AOPM_R5_CTRL_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define AOPM_R5_CTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define AOPM_R5_CTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_R5_CTRL_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define AOPM_R5_CTRL_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define AOPM_R5_CTRL_0_FWLOADDONE_SHIFT                 _MK_SHIFT_CONST(1)
#define AOPM_R5_CTRL_0_FWLOADDONE_FIELD                 _MK_FIELD_CONST(0x1, AOPM_R5_CTRL_0_FWLOADDONE_SHIFT)
#define AOPM_R5_CTRL_0_FWLOADDONE_RANGE                 1:1
#define AOPM_R5_CTRL_0_FWLOADDONE_WOFFSET                       0x0
#define AOPM_R5_CTRL_0_FWLOADDONE_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_R5_CTRL_0_FWLOADDONE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_R5_CTRL_0_FWLOADDONE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_R5_CTRL_0_FWLOADDONE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_R5_CTRL_0_FWLOADDONE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_R5_CTRL_0_FWLOADDONE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_R5_CTRL_0_FWLOADDONE_INIT_ENUM                     HALTED
#define AOPM_R5_CTRL_0_FWLOADDONE_HALTED                        _MK_ENUM_CONST(0)
#define AOPM_R5_CTRL_0_FWLOADDONE_DONE                  _MK_ENUM_CONST(1)

#define AOPM_R5_CTRL_0_LOCK_SHIFT                       _MK_SHIFT_CONST(0)
#define AOPM_R5_CTRL_0_LOCK_FIELD                       _MK_FIELD_CONST(0x1, AOPM_R5_CTRL_0_LOCK_SHIFT)
#define AOPM_R5_CTRL_0_LOCK_RANGE                       0:0
#define AOPM_R5_CTRL_0_LOCK_WOFFSET                     0x0
#define AOPM_R5_CTRL_0_LOCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_R5_CTRL_0_LOCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_R5_CTRL_0_LOCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_R5_CTRL_0_LOCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_R5_CTRL_0_LOCK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_R5_CTRL_0_LOCK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_R5_CTRL_0_LOCK_INIT_ENUM                   UNLOCKED
#define AOPM_R5_CTRL_0_LOCK_UNLOCKED                    _MK_ENUM_CONST(0)
#define AOPM_R5_CTRL_0_LOCK_LOCKED                      _MK_ENUM_CONST(1)


// Register AOPM_TCM_SEL_0
#define AOPM_TCM_SEL_0                  _MK_ADDR_CONST(0x44)
#define AOPM_TCM_SEL_0_SECURE                   0x0
#define AOPM_TCM_SEL_0_DUAL                     0x0
#define AOPM_TCM_SEL_0_SCR                      SCR_SHARED_0
#define AOPM_TCM_SEL_0_WORD_COUNT                       0x1
#define AOPM_TCM_SEL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define AOPM_TCM_SEL_0_RESET_MASK                       _MK_MASK_CONST(0x3c)
#define AOPM_TCM_SEL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define AOPM_TCM_SEL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_TCM_SEL_0_READ_MASK                        _MK_MASK_CONST(0x3c)
#define AOPM_TCM_SEL_0_WRITE_MASK                       _MK_MASK_CONST(0x3c)
#define AOPM_TCM_SEL_0_AXI_ADDR_SHIFT                   _MK_SHIFT_CONST(2)
#define AOPM_TCM_SEL_0_AXI_ADDR_FIELD                   _MK_FIELD_CONST(0xf, AOPM_TCM_SEL_0_AXI_ADDR_SHIFT)
#define AOPM_TCM_SEL_0_AXI_ADDR_RANGE                   5:2
#define AOPM_TCM_SEL_0_AXI_ADDR_WOFFSET                 0x0
#define AOPM_TCM_SEL_0_AXI_ADDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_TCM_SEL_0_AXI_ADDR_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define AOPM_TCM_SEL_0_AXI_ADDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_TCM_SEL_0_AXI_ADDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_TCM_SEL_0_AXI_ADDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_TCM_SEL_0_AXI_ADDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register AOPM_TCM_SLCG_0
#define AOPM_TCM_SLCG_0                 _MK_ADDR_CONST(0x48)
#define AOPM_TCM_SLCG_0_SECURE                  0x0
#define AOPM_TCM_SLCG_0_DUAL                    0x0
#define AOPM_TCM_SLCG_0_SCR                     SCR_SHARED_0
#define AOPM_TCM_SLCG_0_WORD_COUNT                      0x1
#define AOPM_TCM_SLCG_0_RESET_VAL                       _MK_MASK_CONST(0x3)
#define AOPM_TCM_SLCG_0_RESET_MASK                      _MK_MASK_CONST(0x3)
#define AOPM_TCM_SLCG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_TCM_SLCG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define AOPM_TCM_SLCG_0_READ_MASK                       _MK_MASK_CONST(0x3)
#define AOPM_TCM_SLCG_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_FIELD                      _MK_FIELD_CONST(0x1, AOPM_TCM_SLCG_0_ATCM_SLCG_EN_SHIFT)
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_RANGE                      0:0
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_WOFFSET                    0x0
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_INIT_ENUM                  ENABLE
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_DISABLE                    _MK_ENUM_CONST(0)
#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_ENABLE                     _MK_ENUM_CONST(1)

#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_SHIFT                      _MK_SHIFT_CONST(1)
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_FIELD                      _MK_FIELD_CONST(0x1, AOPM_TCM_SLCG_0_BTCM_SLCG_EN_SHIFT)
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_RANGE                      1:1
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_WOFFSET                    0x0
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_INIT_ENUM                  ENABLE
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_DISABLE                    _MK_ENUM_CONST(0)
#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register AOPM_ACTMON_0
#define AOPM_ACTMON_0                   _MK_ADDR_CONST(0x4c)
#define AOPM_ACTMON_0_SECURE                    0x0
#define AOPM_ACTMON_0_DUAL                      0x0
#define AOPM_ACTMON_0_SCR                       SCR_SHARED_0
#define AOPM_ACTMON_0_WORD_COUNT                        0x1
#define AOPM_ACTMON_0_RESET_VAL                         _MK_MASK_CONST(0xff0000)
#define AOPM_ACTMON_0_RESET_MASK                        _MK_MASK_CONST(0x80ff00f7)
#define AOPM_ACTMON_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_READ_MASK                         _MK_MASK_CONST(0x80ff00f7)
#define AOPM_ACTMON_0_WRITE_MASK                        _MK_MASK_CONST(0x80ff00f7)
#define AOPM_ACTMON_0_MASK_NCLK_SHIFT                   _MK_SHIFT_CONST(0)
#define AOPM_ACTMON_0_MASK_NCLK_FIELD                   _MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_NCLK_SHIFT)
#define AOPM_ACTMON_0_MASK_NCLK_RANGE                   0:0
#define AOPM_ACTMON_0_MASK_NCLK_WOFFSET                 0x0
#define AOPM_ACTMON_0_MASK_NCLK_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NCLK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_NCLK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NCLK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NCLK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NCLK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_NCLK_INIT_ENUM                       UNMASK
#define AOPM_ACTMON_0_MASK_NCLK_UNMASK                  _MK_ENUM_CONST(0)
#define AOPM_ACTMON_0_MASK_NCLK_MASK                    _MK_ENUM_CONST(1)

#define AOPM_ACTMON_0_MASK_NWFI_SHIFT                   _MK_SHIFT_CONST(1)
#define AOPM_ACTMON_0_MASK_NWFI_FIELD                   _MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_NWFI_SHIFT)
#define AOPM_ACTMON_0_MASK_NWFI_RANGE                   1:1
#define AOPM_ACTMON_0_MASK_NWFI_WOFFSET                 0x0
#define AOPM_ACTMON_0_MASK_NWFI_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NWFI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_NWFI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NWFI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NWFI_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NWFI_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_NWFI_INIT_ENUM                       UNMASK
#define AOPM_ACTMON_0_MASK_NWFI_UNMASK                  _MK_ENUM_CONST(0)
#define AOPM_ACTMON_0_MASK_NWFI_MASK                    _MK_ENUM_CONST(1)

#define AOPM_ACTMON_0_MASK_NWFE_SHIFT                   _MK_SHIFT_CONST(2)
#define AOPM_ACTMON_0_MASK_NWFE_FIELD                   _MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_NWFE_SHIFT)
#define AOPM_ACTMON_0_MASK_NWFE_RANGE                   2:2
#define AOPM_ACTMON_0_MASK_NWFE_WOFFSET                 0x0
#define AOPM_ACTMON_0_MASK_NWFE_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NWFE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_NWFE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NWFE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NWFE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_NWFE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_NWFE_INIT_ENUM                       UNMASK
#define AOPM_ACTMON_0_MASK_NWFE_UNMASK                  _MK_ENUM_CONST(0)
#define AOPM_ACTMON_0_MASK_NWFE_MASK                    _MK_ENUM_CONST(1)

#define AOPM_ACTMON_0_MASK_EB5_SHIFT                    _MK_SHIFT_CONST(4)
#define AOPM_ACTMON_0_MASK_EB5_FIELD                    _MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_EB5_SHIFT)
#define AOPM_ACTMON_0_MASK_EB5_RANGE                    4:4
#define AOPM_ACTMON_0_MASK_EB5_WOFFSET                  0x0
#define AOPM_ACTMON_0_MASK_EB5_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_EB5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB5_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB5_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_EB5_INIT_ENUM                        UNMASK
#define AOPM_ACTMON_0_MASK_EB5_UNMASK                   _MK_ENUM_CONST(0)
#define AOPM_ACTMON_0_MASK_EB5_MASK                     _MK_ENUM_CONST(1)

#define AOPM_ACTMON_0_MASK_EB16_SHIFT                   _MK_SHIFT_CONST(5)
#define AOPM_ACTMON_0_MASK_EB16_FIELD                   _MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_EB16_SHIFT)
#define AOPM_ACTMON_0_MASK_EB16_RANGE                   5:5
#define AOPM_ACTMON_0_MASK_EB16_WOFFSET                 0x0
#define AOPM_ACTMON_0_MASK_EB16_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB16_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_EB16_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB16_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB16_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB16_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_EB16_INIT_ENUM                       UNMASK
#define AOPM_ACTMON_0_MASK_EB16_UNMASK                  _MK_ENUM_CONST(0)
#define AOPM_ACTMON_0_MASK_EB16_MASK                    _MK_ENUM_CONST(1)

#define AOPM_ACTMON_0_MASK_EB19_SHIFT                   _MK_SHIFT_CONST(6)
#define AOPM_ACTMON_0_MASK_EB19_FIELD                   _MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_EB19_SHIFT)
#define AOPM_ACTMON_0_MASK_EB19_RANGE                   6:6
#define AOPM_ACTMON_0_MASK_EB19_WOFFSET                 0x0
#define AOPM_ACTMON_0_MASK_EB19_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB19_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_EB19_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB19_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB19_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB19_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_EB19_INIT_ENUM                       UNMASK
#define AOPM_ACTMON_0_MASK_EB19_UNMASK                  _MK_ENUM_CONST(0)
#define AOPM_ACTMON_0_MASK_EB19_MASK                    _MK_ENUM_CONST(1)

#define AOPM_ACTMON_0_MASK_EB20_SHIFT                   _MK_SHIFT_CONST(7)
#define AOPM_ACTMON_0_MASK_EB20_FIELD                   _MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_EB20_SHIFT)
#define AOPM_ACTMON_0_MASK_EB20_RANGE                   7:7
#define AOPM_ACTMON_0_MASK_EB20_WOFFSET                 0x0
#define AOPM_ACTMON_0_MASK_EB20_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB20_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_EB20_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB20_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB20_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_MASK_EB20_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_MASK_EB20_INIT_ENUM                       UNMASK
#define AOPM_ACTMON_0_MASK_EB20_UNMASK                  _MK_ENUM_CONST(0)
#define AOPM_ACTMON_0_MASK_EB20_MASK                    _MK_ENUM_CONST(1)

#define AOPM_ACTMON_0_COUNT_TGT_SHIFT                   _MK_SHIFT_CONST(16)
#define AOPM_ACTMON_0_COUNT_TGT_FIELD                   _MK_FIELD_CONST(0xff, AOPM_ACTMON_0_COUNT_TGT_SHIFT)
#define AOPM_ACTMON_0_COUNT_TGT_RANGE                   23:16
#define AOPM_ACTMON_0_COUNT_TGT_WOFFSET                 0x0
#define AOPM_ACTMON_0_COUNT_TGT_DEFAULT                 _MK_MASK_CONST(0xff)
#define AOPM_ACTMON_0_COUNT_TGT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define AOPM_ACTMON_0_COUNT_TGT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_COUNT_TGT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_COUNT_TGT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_COUNT_TGT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define AOPM_ACTMON_0_ENB_CNTR_SHIFT                    _MK_SHIFT_CONST(31)
#define AOPM_ACTMON_0_ENB_CNTR_FIELD                    _MK_FIELD_CONST(0x1, AOPM_ACTMON_0_ENB_CNTR_SHIFT)
#define AOPM_ACTMON_0_ENB_CNTR_RANGE                    31:31
#define AOPM_ACTMON_0_ENB_CNTR_WOFFSET                  0x0
#define AOPM_ACTMON_0_ENB_CNTR_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_ENB_CNTR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_ENB_CNTR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_ENB_CNTR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_ENB_CNTR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_ACTMON_0_ENB_CNTR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_ACTMON_0_ENB_CNTR_INIT_ENUM                        DISABLE
#define AOPM_ACTMON_0_ENB_CNTR_DISABLE                  _MK_ENUM_CONST(0)
#define AOPM_ACTMON_0_ENB_CNTR_ENABLE                   _MK_ENUM_CONST(1)


// Register AOPM_R5_INTR_STATUS_0
#define AOPM_R5_INTR_STATUS_0                   _MK_ADDR_CONST(0x50)
#define AOPM_R5_INTR_STATUS_0_SECURE                    0x0
#define AOPM_R5_INTR_STATUS_0_DUAL                      0x0
#define AOPM_R5_INTR_STATUS_0_SCR                       SCR_SHARED_0
#define AOPM_R5_INTR_STATUS_0_WORD_COUNT                        0x1
#define AOPM_R5_INTR_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_SHIFT                   _MK_SHIFT_CONST(0)
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_FIELD                   _MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_RTC_ALARM_SHIFT)
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_RANGE                   0:0
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_WOFFSET                 0x0
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_INIT_ENUM                       CLEAR
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_CLEAR                   _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_SET                     _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_SHIFT                  _MK_SHIFT_CONST(1)
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_FIELD                  _MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_SHIFT)
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_RANGE                  1:1
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_WOFFSET                        0x0
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_INIT_ENUM                      CLEAR
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_CLEAR                  _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_SET                    _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_SHIFT                  _MK_SHIFT_CONST(2)
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_FIELD                  _MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_SHIFT)
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_RANGE                  2:2
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_WOFFSET                        0x0
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_INIT_ENUM                      CLEAR
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_CLEAR                  _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_SET                    _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_SHIFT                  _MK_SHIFT_CONST(3)
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_FIELD                  _MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_SHIFT)
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_RANGE                  3:3
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_WOFFSET                        0x0
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_INIT_ENUM                      CLEAR
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_CLEAR                  _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_SET                    _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_STATUS_0_LP_EXIT_SHIFT                     _MK_SHIFT_CONST(4)
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_FIELD                     _MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_LP_EXIT_SHIFT)
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_RANGE                     4:4
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_WOFFSET                   0x0
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_INIT_ENUM                 CLEAR
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_CLEAR                     _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_STATUS_0_LP_EXIT_SET                       _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_STATUS_0_DBG_TO_SHIFT                      _MK_SHIFT_CONST(5)
#define AOPM_R5_INTR_STATUS_0_DBG_TO_FIELD                      _MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_DBG_TO_SHIFT)
#define AOPM_R5_INTR_STATUS_0_DBG_TO_RANGE                      5:5
#define AOPM_R5_INTR_STATUS_0_DBG_TO_WOFFSET                    0x0
#define AOPM_R5_INTR_STATUS_0_DBG_TO_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_DBG_TO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_DBG_TO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_DBG_TO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_DBG_TO_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_DBG_TO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_DBG_TO_INIT_ENUM                  CLEAR
#define AOPM_R5_INTR_STATUS_0_DBG_TO_CLEAR                      _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_STATUS_0_DBG_TO_SET                        _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_SHIFT                  _MK_SHIFT_CONST(6)
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_FIELD                  _MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_RET_ACK_SHIFT)
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_RANGE                  6:6
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_WOFFSET                        0x0
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_INIT_ENUM                      CLEAR
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_CLEAR                  _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_SET                    _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_SHIFT                     _MK_SHIFT_CONST(7)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_FIELD                     _MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_SHIFT)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_RANGE                     7:7
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_WOFFSET                   0x0
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_INIT_ENUM                 CLEAR
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_CLEAR                     _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_SET                       _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_SHIFT                 _MK_SHIFT_CONST(8)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_FIELD                 _MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_SHIFT)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_RANGE                 8:8
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_WOFFSET                       0x0
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_INIT_ENUM                     CLEAR
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_CLEAR                 _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_SET                   _MK_ENUM_CONST(1)


// Register AOPM_R5_INTR_MASK_0
#define AOPM_R5_INTR_MASK_0                     _MK_ADDR_CONST(0x54)
#define AOPM_R5_INTR_MASK_0_SECURE                      0x0
#define AOPM_R5_INTR_MASK_0_DUAL                        0x0
#define AOPM_R5_INTR_MASK_0_SCR                         SCR_SHARED_0
#define AOPM_R5_INTR_MASK_0_WORD_COUNT                  0x1
#define AOPM_R5_INTR_MASK_0_RESET_VAL                   _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_MASK_0_RESET_MASK                  _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_MASK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_READ_MASK                   _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_MASK_0_WRITE_MASK                  _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_SHIFT                     _MK_SHIFT_CONST(0)
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_FIELD                     _MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_RTC_ALARM_SHIFT)
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_RANGE                     0:0
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_WOFFSET                   0x0
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_DEFAULT                   _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_INIT_ENUM                 MASK
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_UNMASK                    _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_MASK_0_RTC_ALARM_MASK                      _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_SHIFT                    _MK_SHIFT_CONST(1)
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_FIELD                    _MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_CAR_ACK_SHIFT)
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_RANGE                    1:1
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_WOFFSET                  0x0
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_DEFAULT                  _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_INIT_ENUM                        MASK
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_UNMASK                   _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_MASK                     _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_SHIFT                    _MK_SHIFT_CONST(2)
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_FIELD                    _MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_DVS_ACK_SHIFT)
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_RANGE                    2:2
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_WOFFSET                  0x0
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_DEFAULT                  _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_INIT_ENUM                        MASK
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_UNMASK                   _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_MASK                     _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_SHIFT                    _MK_SHIFT_CONST(3)
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_FIELD                    _MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_OSC_ACK_SHIFT)
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_RANGE                    3:3
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_WOFFSET                  0x0
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_DEFAULT                  _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_INIT_ENUM                        MASK
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_UNMASK                   _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_MASK                     _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_MASK_0_LP_EXIT_SHIFT                       _MK_SHIFT_CONST(4)
#define AOPM_R5_INTR_MASK_0_LP_EXIT_FIELD                       _MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_LP_EXIT_SHIFT)
#define AOPM_R5_INTR_MASK_0_LP_EXIT_RANGE                       4:4
#define AOPM_R5_INTR_MASK_0_LP_EXIT_WOFFSET                     0x0
#define AOPM_R5_INTR_MASK_0_LP_EXIT_DEFAULT                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_LP_EXIT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_LP_EXIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_LP_EXIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_LP_EXIT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_LP_EXIT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_LP_EXIT_INIT_ENUM                   MASK
#define AOPM_R5_INTR_MASK_0_LP_EXIT_UNMASK                      _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_MASK_0_LP_EXIT_MASK                        _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_MASK_0_DBG_TO_SHIFT                        _MK_SHIFT_CONST(5)
#define AOPM_R5_INTR_MASK_0_DBG_TO_FIELD                        _MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_DBG_TO_SHIFT)
#define AOPM_R5_INTR_MASK_0_DBG_TO_RANGE                        5:5
#define AOPM_R5_INTR_MASK_0_DBG_TO_WOFFSET                      0x0
#define AOPM_R5_INTR_MASK_0_DBG_TO_DEFAULT                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_DBG_TO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_DBG_TO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_DBG_TO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_DBG_TO_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_DBG_TO_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_DBG_TO_INIT_ENUM                    MASK
#define AOPM_R5_INTR_MASK_0_DBG_TO_UNMASK                       _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_MASK_0_DBG_TO_MASK                 _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_SHIFT                    _MK_SHIFT_CONST(6)
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_FIELD                    _MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_RET_ACK_SHIFT)
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_RANGE                    6:6
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_WOFFSET                  0x0
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_DEFAULT                  _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_INIT_ENUM                        MASK
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_UNMASK                   _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_MASK                     _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_SHIFT                       _MK_SHIFT_CONST(7)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_FIELD                       _MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_SHIFT)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_RANGE                       7:7
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_WOFFSET                     0x0
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_DEFAULT                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_INIT_ENUM                   MASK
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_UNMASK                      _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_MASK                        _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_SHIFT                   _MK_SHIFT_CONST(8)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_FIELD                   _MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_SHIFT)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_RANGE                   8:8
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_WOFFSET                 0x0
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_DEFAULT                 _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_INIT_ENUM                       MASK
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_UNMASK                  _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_MASK                    _MK_ENUM_CONST(1)


// Register AOPM_R5_INTR_SET_0
#define AOPM_R5_INTR_SET_0                      _MK_ADDR_CONST(0x58)
#define AOPM_R5_INTR_SET_0_SECURE                       0x0
#define AOPM_R5_INTR_SET_0_DUAL                         0x0
#define AOPM_R5_INTR_SET_0_SCR                  SCR_SHARED_0
#define AOPM_R5_INTR_SET_0_WORD_COUNT                   0x1
#define AOPM_R5_INTR_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_SET_0_RTC_ALARM_SHIFT                      _MK_SHIFT_CONST(0)
#define AOPM_R5_INTR_SET_0_RTC_ALARM_FIELD                      _MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_RTC_ALARM_SHIFT)
#define AOPM_R5_INTR_SET_0_RTC_ALARM_RANGE                      0:0
#define AOPM_R5_INTR_SET_0_RTC_ALARM_WOFFSET                    0x0
#define AOPM_R5_INTR_SET_0_RTC_ALARM_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_RTC_ALARM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_RTC_ALARM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_RTC_ALARM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_RTC_ALARM_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_RTC_ALARM_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_RTC_ALARM_INIT_ENUM                  CLEAR
#define AOPM_R5_INTR_SET_0_RTC_ALARM_CLEAR                      _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_SET_0_RTC_ALARM_SET                        _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_SHIFT                     _MK_SHIFT_CONST(1)
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_FIELD                     _MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_CAR_ACK_SHIFT)
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_RANGE                     1:1
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_WOFFSET                   0x0
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_INIT_ENUM                 CLEAR
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_CLEAR                     _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_SET                       _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_SHIFT                     _MK_SHIFT_CONST(2)
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_FIELD                     _MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_DVS_ACK_SHIFT)
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_RANGE                     2:2
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_WOFFSET                   0x0
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_INIT_ENUM                 CLEAR
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_CLEAR                     _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_SET                       _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_SHIFT                     _MK_SHIFT_CONST(3)
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_FIELD                     _MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_OSC_ACK_SHIFT)
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_RANGE                     3:3
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_WOFFSET                   0x0
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_INIT_ENUM                 CLEAR
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_CLEAR                     _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_SET                       _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_SET_0_LP_EXIT_SHIFT                        _MK_SHIFT_CONST(4)
#define AOPM_R5_INTR_SET_0_LP_EXIT_FIELD                        _MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_LP_EXIT_SHIFT)
#define AOPM_R5_INTR_SET_0_LP_EXIT_RANGE                        4:4
#define AOPM_R5_INTR_SET_0_LP_EXIT_WOFFSET                      0x0
#define AOPM_R5_INTR_SET_0_LP_EXIT_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_LP_EXIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_LP_EXIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_LP_EXIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_LP_EXIT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_LP_EXIT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_LP_EXIT_INIT_ENUM                    CLEAR
#define AOPM_R5_INTR_SET_0_LP_EXIT_CLEAR                        _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_SET_0_LP_EXIT_SET                  _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_SET_0_DBG_TO_SHIFT                 _MK_SHIFT_CONST(5)
#define AOPM_R5_INTR_SET_0_DBG_TO_FIELD                 _MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_DBG_TO_SHIFT)
#define AOPM_R5_INTR_SET_0_DBG_TO_RANGE                 5:5
#define AOPM_R5_INTR_SET_0_DBG_TO_WOFFSET                       0x0
#define AOPM_R5_INTR_SET_0_DBG_TO_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_DBG_TO_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_DBG_TO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_DBG_TO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_DBG_TO_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_DBG_TO_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_DBG_TO_INIT_ENUM                     CLEAR
#define AOPM_R5_INTR_SET_0_DBG_TO_CLEAR                 _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_SET_0_DBG_TO_SET                   _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_SET_0_NO_RET_ACK_SHIFT                     _MK_SHIFT_CONST(6)
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_FIELD                     _MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_RET_ACK_SHIFT)
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_RANGE                     6:6
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_WOFFSET                   0x0
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_INIT_ENUM                 CLEAR
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_CLEAR                     _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_SET_0_NO_RET_ACK_SET                       _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_SHIFT                        _MK_SHIFT_CONST(7)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_FIELD                        _MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_SHIFT)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_RANGE                        7:7
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_WOFFSET                      0x0
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_INIT_ENUM                    CLEAR
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_CLEAR                        _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_SET                  _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_SHIFT                    _MK_SHIFT_CONST(8)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_FIELD                    _MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_NOC_IDLE_SHIFT)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_RANGE                    8:8
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_WOFFSET                  0x0
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_INIT_ENUM                        CLEAR
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_CLEAR                    _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_SET                      _MK_ENUM_CONST(1)


// Register AOPM_R5_INTR_CLEAR_0
#define AOPM_R5_INTR_CLEAR_0                    _MK_ADDR_CONST(0x5c)
#define AOPM_R5_INTR_CLEAR_0_SECURE                     0x0
#define AOPM_R5_INTR_CLEAR_0_DUAL                       0x0
#define AOPM_R5_INTR_CLEAR_0_SCR                        SCR_SHARED_0
#define AOPM_R5_INTR_CLEAR_0_WORD_COUNT                         0x1
#define AOPM_R5_INTR_CLEAR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_RESET_MASK                         _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_CLEAR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_CLEAR_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_SHIFT                    _MK_SHIFT_CONST(0)
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_FIELD                    _MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_RTC_ALARM_SHIFT)
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_RANGE                    0:0
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_WOFFSET                  0x0
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_INIT_ENUM                        DISABLE
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_DISABLE                  _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_ENABLE                   _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_SHIFT                   _MK_SHIFT_CONST(1)
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_FIELD                   _MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_SHIFT)
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_RANGE                   1:1
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_WOFFSET                 0x0
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_INIT_ENUM                       DISABLE
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_DISABLE                 _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_ENABLE                  _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_SHIFT                   _MK_SHIFT_CONST(2)
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_FIELD                   _MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_SHIFT)
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_RANGE                   2:2
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_WOFFSET                 0x0
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_INIT_ENUM                       DISABLE
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_DISABLE                 _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_ENABLE                  _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_SHIFT                   _MK_SHIFT_CONST(3)
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_FIELD                   _MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_SHIFT)
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_RANGE                   3:3
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_WOFFSET                 0x0
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_INIT_ENUM                       DISABLE
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_DISABLE                 _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_ENABLE                  _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_SHIFT                      _MK_SHIFT_CONST(4)
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_FIELD                      _MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_LP_EXIT_SHIFT)
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_RANGE                      4:4
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_WOFFSET                    0x0
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_INIT_ENUM                  DISABLE
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_DISABLE                    _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_ENABLE                     _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_CLEAR_0_DBG_TO_SHIFT                       _MK_SHIFT_CONST(5)
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_FIELD                       _MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_DBG_TO_SHIFT)
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_RANGE                       5:5
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_WOFFSET                     0x0
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_INIT_ENUM                   DISABLE
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_DISABLE                     _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_CLEAR_0_DBG_TO_ENABLE                      _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_SHIFT                   _MK_SHIFT_CONST(6)
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_FIELD                   _MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_SHIFT)
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_RANGE                   6:6
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_WOFFSET                 0x0
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_INIT_ENUM                       DISABLE
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_DISABLE                 _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_ENABLE                  _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SHIFT                      _MK_SHIFT_CONST(7)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_FIELD                      _MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SHIFT)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_RANGE                      7:7
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_WOFFSET                    0x0
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_INIT_ENUM                  DISABLE
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DISABLE                    _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_ENABLE                     _MK_ENUM_CONST(1)

#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_SHIFT                  _MK_SHIFT_CONST(8)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_FIELD                  _MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_SHIFT)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_RANGE                  8:8
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_WOFFSET                        0x0
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_INIT_ENUM                      DISABLE
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_DISABLE                        _MK_ENUM_CONST(0)
#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ENABLE                 _MK_ENUM_CONST(1)


// Register AOPM_EXT_INTR_STATUS_0
#define AOPM_EXT_INTR_STATUS_0                  _MK_ADDR_CONST(0x60)
#define AOPM_EXT_INTR_STATUS_0_SECURE                   0x0
#define AOPM_EXT_INTR_STATUS_0_DUAL                     0x0
#define AOPM_EXT_INTR_STATUS_0_SCR                      SCR_SHARED_0
#define AOPM_EXT_INTR_STATUS_0_WORD_COUNT                       0x1
#define AOPM_EXT_INTR_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_SHIFT                  _MK_SHIFT_CONST(0)
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_FIELD                  _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_RTC_ALARM_SHIFT)
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_RANGE                  0:0
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_WOFFSET                        0x0
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_INIT_ENUM                      CLEAR
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_CLEAR                  _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_SET                    _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_SHIFT                 _MK_SHIFT_CONST(1)
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_FIELD                 _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_SHIFT)
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_RANGE                 1:1
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_WOFFSET                       0x0
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_INIT_ENUM                     CLEAR
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_CLEAR                 _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_SET                   _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_SHIFT                 _MK_SHIFT_CONST(2)
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_FIELD                 _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_SHIFT)
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_RANGE                 2:2
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_WOFFSET                       0x0
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_INIT_ENUM                     CLEAR
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_CLEAR                 _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_SET                   _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_SHIFT                 _MK_SHIFT_CONST(3)
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_FIELD                 _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_SHIFT)
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_RANGE                 3:3
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_WOFFSET                       0x0
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_INIT_ENUM                     CLEAR
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_CLEAR                 _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_SET                   _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_SHIFT                    _MK_SHIFT_CONST(4)
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_FIELD                    _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_LP_EXIT_SHIFT)
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_RANGE                    4:4
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_WOFFSET                  0x0
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_INIT_ENUM                        CLEAR
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_CLEAR                    _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_SET                      _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_STATUS_0_DBG_TO_SHIFT                     _MK_SHIFT_CONST(5)
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_FIELD                     _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_DBG_TO_SHIFT)
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_RANGE                     5:5
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_WOFFSET                   0x0
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_INIT_ENUM                 CLEAR
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_CLEAR                     _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_STATUS_0_DBG_TO_SET                       _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_SHIFT                 _MK_SHIFT_CONST(6)
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_FIELD                 _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_SHIFT)
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_RANGE                 6:6
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_WOFFSET                       0x0
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_INIT_ENUM                     CLEAR
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_CLEAR                 _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_SET                   _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_SHIFT                    _MK_SHIFT_CONST(7)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_FIELD                    _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_SHIFT)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_RANGE                    7:7
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_WOFFSET                  0x0
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_INIT_ENUM                        CLEAR
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_CLEAR                    _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_SET                      _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_SHIFT                        _MK_SHIFT_CONST(8)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_FIELD                        _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_SHIFT)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_RANGE                        8:8
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_WOFFSET                      0x0
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_INIT_ENUM                    CLEAR
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_CLEAR                        _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_SET                  _MK_ENUM_CONST(1)


// Register AOPM_EXT_INTR_MASK_0
#define AOPM_EXT_INTR_MASK_0                    _MK_ADDR_CONST(0x64)
#define AOPM_EXT_INTR_MASK_0_SECURE                     0x0
#define AOPM_EXT_INTR_MASK_0_DUAL                       0x0
#define AOPM_EXT_INTR_MASK_0_SCR                        SCR_PRIVATE_0
#define AOPM_EXT_INTR_MASK_0_WORD_COUNT                         0x1
#define AOPM_EXT_INTR_MASK_0_RESET_VAL                  _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_MASK_0_RESET_MASK                         _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_MASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_MASK_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_SHIFT                    _MK_SHIFT_CONST(0)
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_FIELD                    _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_RTC_ALARM_SHIFT)
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_RANGE                    0:0
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_WOFFSET                  0x0
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_DEFAULT                  _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_INIT_ENUM                        MASK
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_UNMASK                   _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_MASK                     _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_SHIFT                   _MK_SHIFT_CONST(1)
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_FIELD                   _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_SHIFT)
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_RANGE                   1:1
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_WOFFSET                 0x0
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_DEFAULT                 _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_INIT_ENUM                       MASK
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_UNMASK                  _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_MASK                    _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_SHIFT                   _MK_SHIFT_CONST(2)
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_FIELD                   _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_SHIFT)
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_RANGE                   2:2
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_WOFFSET                 0x0
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_DEFAULT                 _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_INIT_ENUM                       MASK
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_UNMASK                  _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_MASK                    _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_SHIFT                   _MK_SHIFT_CONST(3)
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_FIELD                   _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_SHIFT)
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_RANGE                   3:3
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_WOFFSET                 0x0
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_DEFAULT                 _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_INIT_ENUM                       MASK
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_UNMASK                  _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_MASK                    _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_MASK_0_LP_EXIT_SHIFT                      _MK_SHIFT_CONST(4)
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_FIELD                      _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_LP_EXIT_SHIFT)
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_RANGE                      4:4
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_WOFFSET                    0x0
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_DEFAULT                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_INIT_ENUM                  MASK
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_UNMASK                     _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_MASK_0_LP_EXIT_MASK                       _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_MASK_0_DBG_TO_SHIFT                       _MK_SHIFT_CONST(5)
#define AOPM_EXT_INTR_MASK_0_DBG_TO_FIELD                       _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_DBG_TO_SHIFT)
#define AOPM_EXT_INTR_MASK_0_DBG_TO_RANGE                       5:5
#define AOPM_EXT_INTR_MASK_0_DBG_TO_WOFFSET                     0x0
#define AOPM_EXT_INTR_MASK_0_DBG_TO_DEFAULT                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_DBG_TO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_DBG_TO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_DBG_TO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_DBG_TO_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_DBG_TO_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_DBG_TO_INIT_ENUM                   MASK
#define AOPM_EXT_INTR_MASK_0_DBG_TO_UNMASK                      _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_MASK_0_DBG_TO_MASK                        _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_SHIFT                   _MK_SHIFT_CONST(6)
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_FIELD                   _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_RET_ACK_SHIFT)
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_RANGE                   6:6
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_WOFFSET                 0x0
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_DEFAULT                 _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_INIT_ENUM                       MASK
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_UNMASK                  _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_MASK                    _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_SHIFT                      _MK_SHIFT_CONST(7)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_FIELD                      _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_SHIFT)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_RANGE                      7:7
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_WOFFSET                    0x0
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_DEFAULT                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_INIT_ENUM                  MASK
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_UNMASK                     _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_MASK                       _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_SHIFT                  _MK_SHIFT_CONST(8)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_FIELD                  _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_SHIFT)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_RANGE                  8:8
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_WOFFSET                        0x0
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_DEFAULT                        _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_INIT_ENUM                      MASK
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_UNMASK                 _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_MASK                   _MK_ENUM_CONST(1)


// Register AOPM_EXT_INTR_SET_0
#define AOPM_EXT_INTR_SET_0                     _MK_ADDR_CONST(0x68)
#define AOPM_EXT_INTR_SET_0_SECURE                      0x0
#define AOPM_EXT_INTR_SET_0_DUAL                        0x0
#define AOPM_EXT_INTR_SET_0_SCR                         SCR_PRIVATE_0
#define AOPM_EXT_INTR_SET_0_WORD_COUNT                  0x1
#define AOPM_EXT_INTR_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_READ_MASK                   _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_SHIFT                     _MK_SHIFT_CONST(0)
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_FIELD                     _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_RTC_ALARM_SHIFT)
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_RANGE                     0:0
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_WOFFSET                   0x0
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_INIT_ENUM                 CLEAR
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_CLEAR                     _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_SET_0_RTC_ALARM_SET                       _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_SHIFT                    _MK_SHIFT_CONST(1)
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_FIELD                    _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_CAR_ACK_SHIFT)
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_RANGE                    1:1
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_WOFFSET                  0x0
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_INIT_ENUM                        CLEAR
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_CLEAR                    _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_SET                      _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_SHIFT                    _MK_SHIFT_CONST(2)
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_FIELD                    _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_DVS_ACK_SHIFT)
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_RANGE                    2:2
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_WOFFSET                  0x0
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_INIT_ENUM                        CLEAR
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_CLEAR                    _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_SET                      _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_SHIFT                    _MK_SHIFT_CONST(3)
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_FIELD                    _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_OSC_ACK_SHIFT)
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_RANGE                    3:3
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_WOFFSET                  0x0
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_INIT_ENUM                        CLEAR
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_CLEAR                    _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_SET                      _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_SET_0_LP_EXIT_SHIFT                       _MK_SHIFT_CONST(4)
#define AOPM_EXT_INTR_SET_0_LP_EXIT_FIELD                       _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_LP_EXIT_SHIFT)
#define AOPM_EXT_INTR_SET_0_LP_EXIT_RANGE                       4:4
#define AOPM_EXT_INTR_SET_0_LP_EXIT_WOFFSET                     0x0
#define AOPM_EXT_INTR_SET_0_LP_EXIT_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_LP_EXIT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_LP_EXIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_LP_EXIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_LP_EXIT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_LP_EXIT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_LP_EXIT_INIT_ENUM                   CLEAR
#define AOPM_EXT_INTR_SET_0_LP_EXIT_CLEAR                       _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_SET_0_LP_EXIT_SET                 _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_SET_0_DBG_TO_SHIFT                        _MK_SHIFT_CONST(5)
#define AOPM_EXT_INTR_SET_0_DBG_TO_FIELD                        _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_DBG_TO_SHIFT)
#define AOPM_EXT_INTR_SET_0_DBG_TO_RANGE                        5:5
#define AOPM_EXT_INTR_SET_0_DBG_TO_WOFFSET                      0x0
#define AOPM_EXT_INTR_SET_0_DBG_TO_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_DBG_TO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_DBG_TO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_DBG_TO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_DBG_TO_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_DBG_TO_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_DBG_TO_INIT_ENUM                    CLEAR
#define AOPM_EXT_INTR_SET_0_DBG_TO_CLEAR                        _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_SET_0_DBG_TO_SET                  _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_SHIFT                    _MK_SHIFT_CONST(6)
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_FIELD                    _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_RET_ACK_SHIFT)
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_RANGE                    6:6
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_WOFFSET                  0x0
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_INIT_ENUM                        CLEAR
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_CLEAR                    _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_SET                      _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_SHIFT                       _MK_SHIFT_CONST(7)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_FIELD                       _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_SHIFT)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_RANGE                       7:7
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_WOFFSET                     0x0
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_INIT_ENUM                   CLEAR
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_CLEAR                       _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_SET                 _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_SHIFT                   _MK_SHIFT_CONST(8)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_FIELD                   _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_SHIFT)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_RANGE                   8:8
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_WOFFSET                 0x0
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_INIT_ENUM                       CLEAR
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_CLEAR                   _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_SET                     _MK_ENUM_CONST(1)


// Register AOPM_EXT_INTR_CLEAR_0
#define AOPM_EXT_INTR_CLEAR_0                   _MK_ADDR_CONST(0x6c)
#define AOPM_EXT_INTR_CLEAR_0_SECURE                    0x0
#define AOPM_EXT_INTR_CLEAR_0_DUAL                      0x0
#define AOPM_EXT_INTR_CLEAR_0_SCR                       SCR_PRIVATE_0
#define AOPM_EXT_INTR_CLEAR_0_WORD_COUNT                        0x1
#define AOPM_EXT_INTR_CLEAR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_RESET_MASK                        _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_CLEAR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_READ_MASK                         _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_CLEAR_0_WRITE_MASK                        _MK_MASK_CONST(0x1ff)
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_SHIFT                   _MK_SHIFT_CONST(0)
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_FIELD                   _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_SHIFT)
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_RANGE                   0:0
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_WOFFSET                 0x0
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_INIT_ENUM                       DISABLE
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_DISABLE                 _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_ENABLE                  _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_SHIFT                  _MK_SHIFT_CONST(1)
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_FIELD                  _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_SHIFT)
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_RANGE                  1:1
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_WOFFSET                        0x0
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_INIT_ENUM                      DISABLE
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_DISABLE                        _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_ENABLE                 _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_SHIFT                  _MK_SHIFT_CONST(2)
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_FIELD                  _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_SHIFT)
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_RANGE                  2:2
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_WOFFSET                        0x0
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_INIT_ENUM                      DISABLE
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_DISABLE                        _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_ENABLE                 _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_SHIFT                  _MK_SHIFT_CONST(3)
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_FIELD                  _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_SHIFT)
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_RANGE                  3:3
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_WOFFSET                        0x0
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_INIT_ENUM                      DISABLE
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_DISABLE                        _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_ENABLE                 _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_SHIFT                     _MK_SHIFT_CONST(4)
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_FIELD                     _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_LP_EXIT_SHIFT)
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_RANGE                     4:4
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_WOFFSET                   0x0
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_INIT_ENUM                 DISABLE
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_DISABLE                   _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_ENABLE                    _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_SHIFT                      _MK_SHIFT_CONST(5)
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_FIELD                      _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_DBG_TO_SHIFT)
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_RANGE                      5:5
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_WOFFSET                    0x0
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_INIT_ENUM                  DISABLE
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_DISABLE                    _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_ENABLE                     _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_SHIFT                  _MK_SHIFT_CONST(6)
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_FIELD                  _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_SHIFT)
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_RANGE                  6:6
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_WOFFSET                        0x0
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_INIT_ENUM                      DISABLE
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_DISABLE                        _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_ENABLE                 _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SHIFT                     _MK_SHIFT_CONST(7)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_FIELD                     _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SHIFT)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_RANGE                     7:7
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_WOFFSET                   0x0
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_INIT_ENUM                 DISABLE
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DISABLE                   _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_ENABLE                    _MK_ENUM_CONST(1)

#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_SHIFT                 _MK_SHIFT_CONST(8)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_FIELD                 _MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_SHIFT)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_RANGE                 8:8
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_WOFFSET                       0x0
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_INIT_ENUM                     DISABLE
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_DISABLE                       _MK_ENUM_CONST(0)
#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ENABLE                        _MK_ENUM_CONST(1)


// Register AOPM_PM_STATUS_NUM_IDLE_0
#define AOPM_PM_STATUS_NUM_IDLE_0                       _MK_ADDR_CONST(0x70)
#define AOPM_PM_STATUS_NUM_IDLE_0_SECURE                        0x0
#define AOPM_PM_STATUS_NUM_IDLE_0_DUAL                  0x0
#define AOPM_PM_STATUS_NUM_IDLE_0_SCR                   SCR_SHARED_0
#define AOPM_PM_STATUS_NUM_IDLE_0_WORD_COUNT                    0x1
#define AOPM_PM_STATUS_NUM_IDLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_IDLE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define AOPM_PM_STATUS_NUM_IDLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_IDLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_IDLE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define AOPM_PM_STATUS_NUM_IDLE_0_WRITE_MASK                    _MK_MASK_CONST(0x80000000)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_SHIFT                      _MK_SHIFT_CONST(0)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_FIELD                      _MK_FIELD_CONST(0x7fffffff, AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_SHIFT)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_RANGE                      30:0
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_WOFFSET                    0x0
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_DEFAULT_MASK                       _MK_MASK_CONST(0x7fffffff)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_SHIFT                  _MK_SHIFT_CONST(31)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_FIELD                  _MK_FIELD_CONST(0x1, AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_SHIFT)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_RANGE                  31:31
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_WOFFSET                        0x0
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register AOPM_PM_STATUS_NUM_STANDBY_0
#define AOPM_PM_STATUS_NUM_STANDBY_0                    _MK_ADDR_CONST(0x74)
#define AOPM_PM_STATUS_NUM_STANDBY_0_SECURE                     0x0
#define AOPM_PM_STATUS_NUM_STANDBY_0_DUAL                       0x0
#define AOPM_PM_STATUS_NUM_STANDBY_0_SCR                        SCR_SHARED_0
#define AOPM_PM_STATUS_NUM_STANDBY_0_WORD_COUNT                         0x1
#define AOPM_PM_STATUS_NUM_STANDBY_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define AOPM_PM_STATUS_NUM_STANDBY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define AOPM_PM_STATUS_NUM_STANDBY_0_WRITE_MASK                         _MK_MASK_CONST(0x80000000)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_SHIFT                        _MK_SHIFT_CONST(0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_FIELD                        _MK_FIELD_CONST(0x7fffffff, AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_SHIFT)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_RANGE                        30:0
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_WOFFSET                      0x0
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_DEFAULT_MASK                 _MK_MASK_CONST(0x7fffffff)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_SHIFT                    _MK_SHIFT_CONST(31)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_FIELD                    _MK_FIELD_CONST(0x1, AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_SHIFT)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_RANGE                    31:31
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_WOFFSET                  0x0
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register AOPM_PM_STATUS_NUM_DORMANT_0
#define AOPM_PM_STATUS_NUM_DORMANT_0                    _MK_ADDR_CONST(0x78)
#define AOPM_PM_STATUS_NUM_DORMANT_0_SECURE                     0x0
#define AOPM_PM_STATUS_NUM_DORMANT_0_DUAL                       0x0
#define AOPM_PM_STATUS_NUM_DORMANT_0_SCR                        SCR_SHARED_0
#define AOPM_PM_STATUS_NUM_DORMANT_0_WORD_COUNT                         0x1
#define AOPM_PM_STATUS_NUM_DORMANT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define AOPM_PM_STATUS_NUM_DORMANT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define AOPM_PM_STATUS_NUM_DORMANT_0_WRITE_MASK                         _MK_MASK_CONST(0x80000000)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_SHIFT                        _MK_SHIFT_CONST(0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_FIELD                        _MK_FIELD_CONST(0x7fffffff, AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_SHIFT)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_RANGE                        30:0
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_WOFFSET                      0x0
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_DEFAULT_MASK                 _MK_MASK_CONST(0x7fffffff)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_SHIFT                    _MK_SHIFT_CONST(31)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_FIELD                    _MK_FIELD_CONST(0x1, AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_SHIFT)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_RANGE                    31:31
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_WOFFSET                  0x0
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Reserved address 0x7c

// Reserved address 0x80

// Reserved address 0x84

// Reserved address 0x88

// Reserved address 0x8c

// Register AOPM_CYA_0
#define AOPM_CYA_0                      _MK_ADDR_CONST(0x90)
#define AOPM_CYA_0_SECURE                       0x0
#define AOPM_CYA_0_DUAL                         0x0
#define AOPM_CYA_0_SCR                  0
#define AOPM_CYA_0_WORD_COUNT                   0x1
#define AOPM_CYA_0_RESET_VAL                    _MK_MASK_CONST(0xfab)
#define AOPM_CYA_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define AOPM_CYA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_CYA_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_0_CYA_SHIFT                    _MK_SHIFT_CONST(0)
#define AOPM_CYA_0_CYA_FIELD                    _MK_FIELD_CONST(0xffffffff, AOPM_CYA_0_CYA_SHIFT)
#define AOPM_CYA_0_CYA_RANGE                    31:0
#define AOPM_CYA_0_CYA_WOFFSET                  0x0
#define AOPM_CYA_0_CYA_DEFAULT                  _MK_MASK_CONST(0xfab)
#define AOPM_CYA_0_CYA_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_0_CYA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_CYA_0_CYA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_CYA_0_CYA_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_CYA_0_CYA_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register AOPM_CYA
#define AOPM_CYA                        _MK_ADDR_CONST(0x90)
#define AOPM_CYA_SECURE                         0x0
#define AOPM_CYA_DUAL                   0x0
#define AOPM_CYA_SCR                    0
#define AOPM_CYA_WORD_COUNT                     0x1
#define AOPM_CYA_RESET_VAL                      _MK_MASK_CONST(0xfab)
#define AOPM_CYA_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_CYA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_CYA_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_CYA_SHIFT                      _MK_SHIFT_CONST(0)
#define AOPM_CYA_CYA_FIELD                      _MK_FIELD_CONST(0xffffffff, AOPM_CYA_CYA_SHIFT)
#define AOPM_CYA_CYA_RANGE                      31:0
#define AOPM_CYA_CYA_WOFFSET                    0x0
#define AOPM_CYA_CYA_DEFAULT                    _MK_MASK_CONST(0xfab)
#define AOPM_CYA_CYA_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_CYA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_CYA_CYA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_CYA_CYA_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_CYA_CYA_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register AOPM_CYA_1
#define AOPM_CYA_1                      _MK_ADDR_CONST(0x94)
#define AOPM_CYA_1_SECURE                       0x0
#define AOPM_CYA_1_DUAL                         0x0
#define AOPM_CYA_1_SCR                  0
#define AOPM_CYA_1_WORD_COUNT                   0x1
#define AOPM_CYA_1_RESET_VAL                    _MK_MASK_CONST(0xfab)
#define AOPM_CYA_1_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define AOPM_CYA_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_CYA_1_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_1_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_1_CYA_SHIFT                    _MK_SHIFT_CONST(0)
#define AOPM_CYA_1_CYA_FIELD                    _MK_FIELD_CONST(0xffffffff, AOPM_CYA_1_CYA_SHIFT)
#define AOPM_CYA_1_CYA_RANGE                    31:0
#define AOPM_CYA_1_CYA_WOFFSET                  0x0
#define AOPM_CYA_1_CYA_DEFAULT                  _MK_MASK_CONST(0xfab)
#define AOPM_CYA_1_CYA_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define AOPM_CYA_1_CYA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_CYA_1_CYA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_CYA_1_CYA_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define AOPM_CYA_1_CYA_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register AOPM_RAIL_RET_TIMER_0
#define AOPM_RAIL_RET_TIMER_0                   _MK_ADDR_CONST(0x98)
#define AOPM_RAIL_RET_TIMER_0_SECURE                    0x0
#define AOPM_RAIL_RET_TIMER_0_DUAL                      0x0
#define AOPM_RAIL_RET_TIMER_0_SCR                       SCR_PRIVATE_0
#define AOPM_RAIL_RET_TIMER_0_WORD_COUNT                        0x1
#define AOPM_RAIL_RET_TIMER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_RAIL_RET_TIMER_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define AOPM_RAIL_RET_TIMER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define AOPM_RAIL_RET_TIMER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_RAIL_RET_TIMER_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define AOPM_RAIL_RET_TIMER_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
#define AOPM_RAIL_RET_TIMER_0_VAL_SHIFT                 _MK_SHIFT_CONST(0)
#define AOPM_RAIL_RET_TIMER_0_VAL_FIELD                 _MK_FIELD_CONST(0xffff, AOPM_RAIL_RET_TIMER_0_VAL_SHIFT)
#define AOPM_RAIL_RET_TIMER_0_VAL_RANGE                 15:0
#define AOPM_RAIL_RET_TIMER_0_VAL_WOFFSET                       0x0
#define AOPM_RAIL_RET_TIMER_0_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define AOPM_RAIL_RET_TIMER_0_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define AOPM_RAIL_RET_TIMER_0_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_RAIL_RET_TIMER_0_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_RAIL_RET_TIMER_0_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_RAIL_RET_TIMER_0_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register AOPM_EXT_SLCG_0
#define AOPM_EXT_SLCG_0                 _MK_ADDR_CONST(0x9c)
#define AOPM_EXT_SLCG_0_SECURE                  0x0
#define AOPM_EXT_SLCG_0_DUAL                    0x0
#define AOPM_EXT_SLCG_0_SCR                     SCR_PRIVATE_0
#define AOPM_EXT_SLCG_0_WORD_COUNT                      0x1
#define AOPM_EXT_SLCG_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_SLCG_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_SLCG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_EXT_SLCG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define AOPM_EXT_SLCG_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_EXT_SLCG_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_SHIFT                   _MK_SHIFT_CONST(0)
#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_FIELD                   _MK_FIELD_CONST(0x1, AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_SHIFT)
#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_RANGE                   0:0
#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_WOFFSET                 0x0
#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x1)
#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register AOPM_SPARE_0
#define AOPM_SPARE_0                    _MK_ADDR_CONST(0xa0)
#define AOPM_SPARE_0_SECURE                     0x0
#define AOPM_SPARE_0_DUAL                       0x0
#define AOPM_SPARE_0_SCR                        0
#define AOPM_SPARE_0_WORD_COUNT                         0x1
#define AOPM_SPARE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_SPARE_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_SPARE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_SPARE_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_0_SPARE_SHIFT                        _MK_SHIFT_CONST(0)
#define AOPM_SPARE_0_SPARE_FIELD                        _MK_FIELD_CONST(0xffffffff, AOPM_SPARE_0_SPARE_SHIFT)
#define AOPM_SPARE_0_SPARE_RANGE                        31:0
#define AOPM_SPARE_0_SPARE_WOFFSET                      0x0
#define AOPM_SPARE_0_SPARE_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_SPARE_0_SPARE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_0_SPARE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_SPARE_0_SPARE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_SPARE_0_SPARE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_SPARE_0_SPARE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register AOPM_SPARE
#define AOPM_SPARE                      _MK_ADDR_CONST(0xa0)
#define AOPM_SPARE_SECURE                       0x0
#define AOPM_SPARE_DUAL                         0x0
#define AOPM_SPARE_SCR                  0
#define AOPM_SPARE_WORD_COUNT                   0x1
#define AOPM_SPARE_RESET_VAL                    _MK_MASK_CONST(0x0)
#define AOPM_SPARE_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define AOPM_SPARE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_SPARE_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_SPARE_SHIFT                  _MK_SHIFT_CONST(0)
#define AOPM_SPARE_SPARE_FIELD                  _MK_FIELD_CONST(0xffffffff, AOPM_SPARE_SPARE_SHIFT)
#define AOPM_SPARE_SPARE_RANGE                  31:0
#define AOPM_SPARE_SPARE_WOFFSET                        0x0
#define AOPM_SPARE_SPARE_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_SPARE_SPARE_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_SPARE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_SPARE_SPARE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_SPARE_SPARE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_SPARE_SPARE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register AOPM_SPARE_1
#define AOPM_SPARE_1                    _MK_ADDR_CONST(0xa4)
#define AOPM_SPARE_1_SECURE                     0x0
#define AOPM_SPARE_1_DUAL                       0x0
#define AOPM_SPARE_1_SCR                        0
#define AOPM_SPARE_1_WORD_COUNT                         0x1
#define AOPM_SPARE_1_RESET_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_SPARE_1_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_1_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_SPARE_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_SPARE_1_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_1_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_1_SPARE_SHIFT                        _MK_SHIFT_CONST(0)
#define AOPM_SPARE_1_SPARE_FIELD                        _MK_FIELD_CONST(0xffffffff, AOPM_SPARE_1_SPARE_SHIFT)
#define AOPM_SPARE_1_SPARE_RANGE                        31:0
#define AOPM_SPARE_1_SPARE_WOFFSET                      0x0
#define AOPM_SPARE_1_SPARE_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_SPARE_1_SPARE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_1_SPARE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_SPARE_1_SPARE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_SPARE_1_SPARE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_SPARE_1_SPARE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register AOPM_SPARE_2
#define AOPM_SPARE_2                    _MK_ADDR_CONST(0xa8)
#define AOPM_SPARE_2_SECURE                     0x0
#define AOPM_SPARE_2_DUAL                       0x0
#define AOPM_SPARE_2_SCR                        0
#define AOPM_SPARE_2_WORD_COUNT                         0x1
#define AOPM_SPARE_2_RESET_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_SPARE_2_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_2_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_SPARE_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_SPARE_2_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_2_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_2_SPARE_SHIFT                        _MK_SHIFT_CONST(0)
#define AOPM_SPARE_2_SPARE_FIELD                        _MK_FIELD_CONST(0xffffffff, AOPM_SPARE_2_SPARE_SHIFT)
#define AOPM_SPARE_2_SPARE_RANGE                        31:0
#define AOPM_SPARE_2_SPARE_WOFFSET                      0x0
#define AOPM_SPARE_2_SPARE_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_SPARE_2_SPARE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define AOPM_SPARE_2_SPARE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_SPARE_2_SPARE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_SPARE_2_SPARE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_SPARE_2_SPARE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0xac

// Reserved address 0xb0

// Register AOPM_SEC_LATCH_0
#define AOPM_SEC_LATCH_0                        _MK_ADDR_CONST(0xb4)
#define AOPM_SEC_LATCH_0_SECURE                         0x0
#define AOPM_SEC_LATCH_0_DUAL                   0x0
#define AOPM_SEC_LATCH_0_SCR                    SCR_PRIVATE_0
#define AOPM_SEC_LATCH_0_WORD_COUNT                     0x1
#define AOPM_SEC_LATCH_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_SEC_LATCH_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_SEC_LATCH_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define AOPM_SEC_LATCH_0_UPD_SHIFT                      _MK_SHIFT_CONST(0)
#define AOPM_SEC_LATCH_0_UPD_FIELD                      _MK_FIELD_CONST(0x1, AOPM_SEC_LATCH_0_UPD_SHIFT)
#define AOPM_SEC_LATCH_0_UPD_RANGE                      0:0
#define AOPM_SEC_LATCH_0_UPD_WOFFSET                    0x0
#define AOPM_SEC_LATCH_0_UPD_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_0_UPD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_SEC_LATCH_0_UPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_0_UPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_0_UPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_0_UPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define AOPM_SEC_LATCH_0_UPD_INIT_ENUM                  DISABLE
#define AOPM_SEC_LATCH_0_UPD_DISABLE                    _MK_ENUM_CONST(0)
#define AOPM_SEC_LATCH_0_UPD_ENABLE                     _MK_ENUM_CONST(1)


// Register AOPM_AON_BLOCK_0
#define AOPM_AON_BLOCK_0                        _MK_ADDR_CONST(0xb8)
#define AOPM_AON_BLOCK_0_SECURE                         0x0
#define AOPM_AON_BLOCK_0_DUAL                   0x0
#define AOPM_AON_BLOCK_0_SCR                    SCR_PRIVATE_0
#define AOPM_AON_BLOCK_0_WORD_COUNT                     0x1
#define AOPM_AON_BLOCK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define AOPM_AON_BLOCK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define AOPM_AON_BLOCK_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_SHIFT                     _MK_SHIFT_CONST(0)
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_FIELD                     _MK_FIELD_CONST(0x1, AOPM_AON_BLOCK_0_AON2SNIC_REQ_SHIFT)
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_RANGE                     0:0
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_WOFFSET                   0x0
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_INIT_ENUM                 DISABLE
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_DISABLE                   _MK_ENUM_CONST(0)
#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_ENABLE                    _MK_ENUM_CONST(1)

#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_SHIFT                  _MK_SHIFT_CONST(1)
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_FIELD                  _MK_FIELD_CONST(0x1, AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_SHIFT)
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_RANGE                  1:1
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_WOFFSET                        0x0
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_INIT_ENUM                      DISABLE
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_DISABLE                        _MK_ENUM_CONST(0)
#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_ENABLE                 _MK_ENUM_CONST(1)

#define AOPM_AON_BLOCK_0_AON2MC_REQ_SHIFT                       _MK_SHIFT_CONST(2)
#define AOPM_AON_BLOCK_0_AON2MC_REQ_FIELD                       _MK_FIELD_CONST(0x1, AOPM_AON_BLOCK_0_AON2MC_REQ_SHIFT)
#define AOPM_AON_BLOCK_0_AON2MC_REQ_RANGE                       2:2
#define AOPM_AON_BLOCK_0_AON2MC_REQ_WOFFSET                     0x0
#define AOPM_AON_BLOCK_0_AON2MC_REQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_AON2MC_REQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define AOPM_AON_BLOCK_0_AON2MC_REQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_AON2MC_REQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_AON2MC_REQ_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define AOPM_AON_BLOCK_0_AON2MC_REQ_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define AOPM_AON_BLOCK_0_AON2MC_REQ_INIT_ENUM                   DISABLE
#define AOPM_AON_BLOCK_0_AON2MC_REQ_DISABLE                     _MK_ENUM_CONST(0)
#define AOPM_AON_BLOCK_0_AON2MC_REQ_ENABLE                      _MK_ENUM_CONST(1)


// Register AOPM_DVS_VOLT_INDEX_0
#define AOPM_DVS_VOLT_INDEX_0                   _MK_ADDR_CONST(0xbc)
#define AOPM_DVS_VOLT_INDEX_0_SECURE                    0x0
#define AOPM_DVS_VOLT_INDEX_0_DUAL                      0x0
#define AOPM_DVS_VOLT_INDEX_0_SCR                       SCR_PRIVATE_0
#define AOPM_DVS_VOLT_INDEX_0_WORD_COUNT                        0x1
#define AOPM_DVS_VOLT_INDEX_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define AOPM_DVS_VOLT_INDEX_0_RESET_MASK                        _MK_MASK_CONST(0x3f3f)
#define AOPM_DVS_VOLT_INDEX_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define AOPM_DVS_VOLT_INDEX_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_DVS_VOLT_INDEX_0_READ_MASK                         _MK_MASK_CONST(0x3f3f)
#define AOPM_DVS_VOLT_INDEX_0_WRITE_MASK                        _MK_MASK_CONST(0x3f3f)
#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_SHIFT                      _MK_SHIFT_CONST(0)
#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_FIELD                      _MK_FIELD_CONST(0x3f, AOPM_DVS_VOLT_INDEX_0_IDX_IN_SHIFT)
#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_RANGE                      5:0
#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_WOFFSET                    0x0
#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_SHIFT                     _MK_SHIFT_CONST(8)
#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_FIELD                     _MK_FIELD_CONST(0x3f, AOPM_DVS_VOLT_INDEX_0_IDX_OUT_SHIFT)
#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_RANGE                     13:8
#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_WOFFSET                   0x0
#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register AOPM_RTC_ALARM_TIMER_0
#define AOPM_RTC_ALARM_TIMER_0                  _MK_ADDR_CONST(0xc0)
#define AOPM_RTC_ALARM_TIMER_0_SECURE                   0x0
#define AOPM_RTC_ALARM_TIMER_0_DUAL                     0x0
#define AOPM_RTC_ALARM_TIMER_0_SCR                      SCR_SHARED_0
#define AOPM_RTC_ALARM_TIMER_0_WORD_COUNT                       0x1
#define AOPM_RTC_ALARM_TIMER_0_RESET_VAL                        _MK_MASK_CONST(0x10)
#define AOPM_RTC_ALARM_TIMER_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define AOPM_RTC_ALARM_TIMER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_TIMER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_TIMER_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define AOPM_RTC_ALARM_TIMER_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define AOPM_RTC_ALARM_TIMER_0_VAL_SHIFT                        _MK_SHIFT_CONST(0)
#define AOPM_RTC_ALARM_TIMER_0_VAL_FIELD                        _MK_FIELD_CONST(0xffffffff, AOPM_RTC_ALARM_TIMER_0_VAL_SHIFT)
#define AOPM_RTC_ALARM_TIMER_0_VAL_RANGE                        31:0
#define AOPM_RTC_ALARM_TIMER_0_VAL_WOFFSET                      0x0
#define AOPM_RTC_ALARM_TIMER_0_VAL_DEFAULT                      _MK_MASK_CONST(0x10)
#define AOPM_RTC_ALARM_TIMER_0_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define AOPM_RTC_ALARM_TIMER_0_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_TIMER_0_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_TIMER_0_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_TIMER_0_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register AOPM_RTC_ALARM_MSEC_TIMER_0
#define AOPM_RTC_ALARM_MSEC_TIMER_0                     _MK_ADDR_CONST(0xc4)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_SECURE                      0x0
#define AOPM_RTC_ALARM_MSEC_TIMER_0_DUAL                        0x0
#define AOPM_RTC_ALARM_MSEC_TIMER_0_SCR                         SCR_SHARED_0
#define AOPM_RTC_ALARM_MSEC_TIMER_0_WORD_COUNT                  0x1
#define AOPM_RTC_ALARM_MSEC_TIMER_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_FIELD                   _MK_FIELD_CONST(0x3ff, AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_SHIFT)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_RANGE                   9:0
#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_WOFFSET                 0x0
#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3ff)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register AOPM_DEBUG_AXIBLOCK_STATUS_0
#define AOPM_DEBUG_AXIBLOCK_STATUS_0                    _MK_ADDR_CONST(0xc8)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_SECURE                     0x0
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_DUAL                       0x0
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_SCR                        SCR_SHARED_0
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_WORD_COUNT                         0x1
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_DEBUG_AXIBLOCK_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_DEBUG_AXIBLOCK_STATUS_FIELD                        _MK_FIELD_CONST(0xffffffff, AOPM_DEBUG_AXIBLOCK_STATUS_0_DEBUG_AXIBLOCK_STATUS_SHIFT)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_DEBUG_AXIBLOCK_STATUS_RANGE                        31:0
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_DEBUG_AXIBLOCK_STATUS_WOFFSET                      0x0
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_DEBUG_AXIBLOCK_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_DEBUG_AXIBLOCK_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_DEBUG_AXIBLOCK_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_DEBUG_AXIBLOCK_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_DEBUG_AXIBLOCK_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define AOPM_DEBUG_AXIBLOCK_STATUS_0_DEBUG_AXIBLOCK_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register AOPM_SEC_LATCH_STATUS_0
#define AOPM_SEC_LATCH_STATUS_0                 _MK_ADDR_CONST(0xcc)
#define AOPM_SEC_LATCH_STATUS_0_SECURE                  0x0
#define AOPM_SEC_LATCH_STATUS_0_DUAL                    0x0
#define AOPM_SEC_LATCH_STATUS_0_SCR                     SCR_PRIVATE_0
#define AOPM_SEC_LATCH_STATUS_0_WORD_COUNT                      0x1
#define AOPM_SEC_LATCH_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x1fffe)
#define AOPM_SEC_LATCH_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x1ffff)
#define AOPM_SEC_LATCH_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x1ffff)
#define AOPM_SEC_LATCH_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_LOCK_SHIFT                      _MK_SHIFT_CONST(0)
#define AOPM_SEC_LATCH_STATUS_0_LOCK_FIELD                      _MK_FIELD_CONST(0x1, AOPM_SEC_LATCH_STATUS_0_LOCK_SHIFT)
#define AOPM_SEC_LATCH_STATUS_0_LOCK_RANGE                      0:0
#define AOPM_SEC_LATCH_STATUS_0_LOCK_WOFFSET                    0x0
#define AOPM_SEC_LATCH_STATUS_0_LOCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_LOCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define AOPM_SEC_LATCH_STATUS_0_LOCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_LOCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_LOCK_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_LOCK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_SHIFT                   _MK_SHIFT_CONST(1)
#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_FIELD                   _MK_FIELD_CONST(0x1, AOPM_SEC_LATCH_STATUS_0_AWPROT1_SHIFT)
#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_RANGE                   1:1
#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_WOFFSET                 0x0
#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_DEFAULT                 _MK_MASK_CONST(0x1)
#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_SHIFT                   _MK_SHIFT_CONST(2)
#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_FIELD                   _MK_FIELD_CONST(0x1, AOPM_SEC_LATCH_STATUS_0_ARPROT1_SHIFT)
#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_RANGE                   2:2
#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_WOFFSET                 0x0
#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_DEFAULT                 _MK_MASK_CONST(0x1)
#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_SHIFT                 _MK_SHIFT_CONST(3)
#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_FIELD                 _MK_FIELD_CONST(0x7f, AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_SHIFT)
#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_RANGE                 9:3
#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_WOFFSET                       0x0
#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_DEFAULT                       _MK_MASK_CONST(0x7f)
#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_SHIFT                 _MK_SHIFT_CONST(10)
#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_FIELD                 _MK_FIELD_CONST(0x7f, AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_SHIFT)
#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_RANGE                 16:10
#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_WOFFSET                       0x0
#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_DEFAULT                       _MK_MASK_CONST(0x7f)
#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARAOPM_REGS(_op_) \
_op_(AOPM_SOFT_RESET_0) \
_op_(AOPM_SLCG_CTRL_0) \
_op_(AOPM_TGT_PWR_STATE_0) \
_op_(AOPM_TCM_RET_TIMER_0) \
_op_(AOPM_DBG_TIMER_0) \
_op_(AOPM_LP_EXIT_0) \
_op_(AOPM_POWER_CFG_MASK_0) \
_op_(AOPM_TGT_PWR_CFG_ORIDE_0) \
_op_(AOPM_PWR_STATUS_0) \
_op_(AOPM_DBG_STATUS_0) \
_op_(AOPM_DBG_FEATURES_0) \
_op_(AOPM_EXIT_MASK_0) \
_op_(AOPM_BURST_CLK_0) \
_op_(AOPM_ACTIRQFIQ_TO_ACT_0) \
_op_(AOPM_CSITE_CFG_0) \
_op_(AOPM_R5_CFG_0) \
_op_(AOPM_R5_CTRL_0) \
_op_(AOPM_TCM_SEL_0) \
_op_(AOPM_TCM_SLCG_0) \
_op_(AOPM_ACTMON_0) \
_op_(AOPM_R5_INTR_STATUS_0) \
_op_(AOPM_R5_INTR_MASK_0) \
_op_(AOPM_R5_INTR_SET_0) \
_op_(AOPM_R5_INTR_CLEAR_0) \
_op_(AOPM_EXT_INTR_STATUS_0) \
_op_(AOPM_EXT_INTR_MASK_0) \
_op_(AOPM_EXT_INTR_SET_0) \
_op_(AOPM_EXT_INTR_CLEAR_0) \
_op_(AOPM_PM_STATUS_NUM_IDLE_0) \
_op_(AOPM_PM_STATUS_NUM_STANDBY_0) \
_op_(AOPM_PM_STATUS_NUM_DORMANT_0) \
_op_(AOPM_CYA_0) \
_op_(AOPM_CYA) \
_op_(AOPM_CYA_1) \
_op_(AOPM_RAIL_RET_TIMER_0) \
_op_(AOPM_EXT_SLCG_0) \
_op_(AOPM_SPARE_0) \
_op_(AOPM_SPARE) \
_op_(AOPM_SPARE_1) \
_op_(AOPM_SPARE_2) \
_op_(AOPM_SEC_LATCH_0) \
_op_(AOPM_AON_BLOCK_0) \
_op_(AOPM_DVS_VOLT_INDEX_0) \
_op_(AOPM_RTC_ALARM_TIMER_0) \
_op_(AOPM_RTC_ALARM_MSEC_TIMER_0) \
_op_(AOPM_DEBUG_AXIBLOCK_STATUS_0) \
_op_(AOPM_SEC_LATCH_STATUS_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_AOPM       0x00000000

//
// ARAOPM REGISTER BANKS
//

#define AOPM0_FIRST_REG 0x0000 // AOPM_SOFT_RESET_0
#define AOPM0_LAST_REG 0x0078 // AOPM_PM_STATUS_NUM_DORMANT_0
#define AOPM1_FIRST_REG 0x0090 // AOPM_CYA_0
#define AOPM1_LAST_REG 0x00a8 // AOPM_SPARE_2
#define AOPM2_FIRST_REG 0x00b4 // AOPM_SEC_LATCH_0
#define AOPM2_LAST_REG 0x00cc // AOPM_SEC_LATCH_STATUS_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARAOPM_H_INC_
