//
// Copyright (c) 2015 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//  * Redistributions of source code must retain the above copyright
//    notice, this list of conditions and the following disclaimer.
//  * Redistributions in binary form must reproduce the above copyright
//    notice, this list of conditions and the following disclaimer in the
//    documentation and/or other materials provided with the distribution.
//  * Neither the name of NVIDIA CORPORATION nor the names of its
//    contributors may be used to endorse or promote products derived
//    from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARAPS_FRSC_H_INC_
#define ___ARAPS_FRSC_H_INC_

// Register APS_FRSC_SC_CTL_0
#define APS_FRSC_SC_CTL_0                       _MK_ADDR_CONST(0x0)
#define APS_FRSC_SC_CTL_0_SECURE                        0x0
#define APS_FRSC_SC_CTL_0_SCR                   0
#define APS_FRSC_SC_CTL_0_WORD_COUNT                    0x1
#define APS_FRSC_SC_CTL_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define APS_FRSC_SC_CTL_0_RESET_MASK                    _MK_MASK_CONST(0xf)
#define APS_FRSC_SC_CTL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_CTL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_CTL_0_READ_MASK                     _MK_MASK_CONST(0xf)
#define APS_FRSC_SC_CTL_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
#define APS_FRSC_SC_CTL_0_REG_SLCG_OVR_ON_SHIFT                 _MK_SHIFT_CONST(3)
#define APS_FRSC_SC_CTL_0_REG_SLCG_OVR_ON_FIELD                 _MK_FIELD_CONST(0x1, APS_FRSC_SC_CTL_0_REG_SLCG_OVR_ON_SHIFT)
#define APS_FRSC_SC_CTL_0_REG_SLCG_OVR_ON_RANGE                 3:3
#define APS_FRSC_SC_CTL_0_REG_SLCG_OVR_ON_WOFFSET                       0x0
#define APS_FRSC_SC_CTL_0_REG_SLCG_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_CTL_0_REG_SLCG_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APS_FRSC_SC_CTL_0_REG_SLCG_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_CTL_0_REG_SLCG_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APS_FRSC_SC_CTL_0_R5R_DISABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define APS_FRSC_SC_CTL_0_R5R_DISABLE_FIELD                     _MK_FIELD_CONST(0x1, APS_FRSC_SC_CTL_0_R5R_DISABLE_SHIFT)
#define APS_FRSC_SC_CTL_0_R5R_DISABLE_RANGE                     2:2
#define APS_FRSC_SC_CTL_0_R5R_DISABLE_WOFFSET                   0x0
#define APS_FRSC_SC_CTL_0_R5R_DISABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_CTL_0_R5R_DISABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APS_FRSC_SC_CTL_0_R5R_DISABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_CTL_0_R5R_DISABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APS_FRSC_SC_CTL_0_FN_DISABLE_C_SHIFT                    _MK_SHIFT_CONST(0)
#define APS_FRSC_SC_CTL_0_FN_DISABLE_C_FIELD                    _MK_FIELD_CONST(0x3, APS_FRSC_SC_CTL_0_FN_DISABLE_C_SHIFT)
#define APS_FRSC_SC_CTL_0_FN_DISABLE_C_RANGE                    1:0
#define APS_FRSC_SC_CTL_0_FN_DISABLE_C_WOFFSET                  0x0
#define APS_FRSC_SC_CTL_0_FN_DISABLE_C_DEFAULT                  _MK_MASK_CONST(0x1)
#define APS_FRSC_SC_CTL_0_FN_DISABLE_C_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define APS_FRSC_SC_CTL_0_FN_DISABLE_C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_CTL_0_FN_DISABLE_C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_CTL_0_FN_DISABLE_C_INIT_ENUM                        DISABLE
#define APS_FRSC_SC_CTL_0_FN_DISABLE_C_DISABLE                  _MK_ENUM_CONST(1)
#define APS_FRSC_SC_CTL_0_FN_DISABLE_C_ENABLE                   _MK_ENUM_CONST(2)


// Register APS_FRSC_SC_STS_0
#define APS_FRSC_SC_STS_0                       _MK_ADDR_CONST(0x4)
#define APS_FRSC_SC_STS_0_SECURE                        0x0
#define APS_FRSC_SC_STS_0_SCR                   0
#define APS_FRSC_SC_STS_0_WORD_COUNT                    0x1
#define APS_FRSC_SC_STS_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define APS_FRSC_SC_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffff07)
#define APS_FRSC_SC_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffff07)
#define APS_FRSC_SC_STS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_STS_0_FN_MODEOUT_SHIFT                      _MK_SHIFT_CONST(8)
#define APS_FRSC_SC_STS_0_FN_MODEOUT_FIELD                      _MK_FIELD_CONST(0xffffff, APS_FRSC_SC_STS_0_FN_MODEOUT_SHIFT)
#define APS_FRSC_SC_STS_0_FN_MODEOUT_RANGE                      31:8
#define APS_FRSC_SC_STS_0_FN_MODEOUT_WOFFSET                    0x0
#define APS_FRSC_SC_STS_0_FN_MODEOUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_STS_0_FN_MODEOUT_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_SC_STS_0_FN_MODEOUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_STS_0_FN_MODEOUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APS_FRSC_SC_STS_0_FN_DPU_HALTED_SHIFT                   _MK_SHIFT_CONST(2)
#define APS_FRSC_SC_STS_0_FN_DPU_HALTED_FIELD                   _MK_FIELD_CONST(0x1, APS_FRSC_SC_STS_0_FN_DPU_HALTED_SHIFT)
#define APS_FRSC_SC_STS_0_FN_DPU_HALTED_RANGE                   2:2
#define APS_FRSC_SC_STS_0_FN_DPU_HALTED_WOFFSET                 0x0
#define APS_FRSC_SC_STS_0_FN_DPU_HALTED_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_STS_0_FN_DPU_HALTED_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APS_FRSC_SC_STS_0_FN_DPU_HALTED_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_STS_0_FN_DPU_HALTED_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APS_FRSC_SC_STS_0_FN_ENABLED_C_SHIFT                    _MK_SHIFT_CONST(0)
#define APS_FRSC_SC_STS_0_FN_ENABLED_C_FIELD                    _MK_FIELD_CONST(0x3, APS_FRSC_SC_STS_0_FN_ENABLED_C_SHIFT)
#define APS_FRSC_SC_STS_0_FN_ENABLED_C_RANGE                    1:0
#define APS_FRSC_SC_STS_0_FN_ENABLED_C_WOFFSET                  0x0
#define APS_FRSC_SC_STS_0_FN_ENABLED_C_DEFAULT                  _MK_MASK_CONST(0x1)
#define APS_FRSC_SC_STS_0_FN_ENABLED_C_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define APS_FRSC_SC_STS_0_FN_ENABLED_C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_STS_0_FN_ENABLED_C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_0_DATA_0
#define APS_FRSC_PGO_0_DATA_0                   _MK_ADDR_CONST(0x8)
#define APS_FRSC_PGO_0_DATA_0_SECURE                    0x0
#define APS_FRSC_PGO_0_DATA_0_SCR                       0
#define APS_FRSC_PGO_0_DATA_0_WORD_COUNT                        0x1
#define APS_FRSC_PGO_0_DATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_0_DATA_0_RESET_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_0_DATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_0_DATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_0_DATA_0_READ_MASK                         _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_0_DATA_0_WRITE_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_0_DATA_0_FN_PGO_0_DATA_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_0_DATA_0_FN_PGO_0_DATA_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_0_DATA_0_FN_PGO_0_DATA_SHIFT)
#define APS_FRSC_PGO_0_DATA_0_FN_PGO_0_DATA_RANGE                       23:0
#define APS_FRSC_PGO_0_DATA_0_FN_PGO_0_DATA_WOFFSET                     0x0
#define APS_FRSC_PGO_0_DATA_0_FN_PGO_0_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_0_DATA_0_FN_PGO_0_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_0_DATA_0_FN_PGO_0_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_0_DATA_0_FN_PGO_0_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_1_DATA_0
#define APS_FRSC_PGO_1_DATA_0                   _MK_ADDR_CONST(0xc)
#define APS_FRSC_PGO_1_DATA_0_SECURE                    0x0
#define APS_FRSC_PGO_1_DATA_0_SCR                       0
#define APS_FRSC_PGO_1_DATA_0_WORD_COUNT                        0x1
#define APS_FRSC_PGO_1_DATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_1_DATA_0_RESET_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_1_DATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_1_DATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_1_DATA_0_READ_MASK                         _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_1_DATA_0_WRITE_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_1_DATA_0_FN_PGO_1_DATA_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_1_DATA_0_FN_PGO_1_DATA_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_1_DATA_0_FN_PGO_1_DATA_SHIFT)
#define APS_FRSC_PGO_1_DATA_0_FN_PGO_1_DATA_RANGE                       23:0
#define APS_FRSC_PGO_1_DATA_0_FN_PGO_1_DATA_WOFFSET                     0x0
#define APS_FRSC_PGO_1_DATA_0_FN_PGO_1_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_1_DATA_0_FN_PGO_1_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_1_DATA_0_FN_PGO_1_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_1_DATA_0_FN_PGO_1_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_INDIRECT_ACCESS_0
#define APS_FRSC_GI_INDIRECT_ACCESS_0                   _MK_ADDR_CONST(0x10)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_SECURE                    0x0
#define APS_FRSC_GI_INDIRECT_ACCESS_0_SCR                       0
#define APS_FRSC_GI_INDIRECT_ACCESS_0_WORD_COUNT                        0x1
#define APS_FRSC_GI_INDIRECT_ACCESS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_RESET_MASK                        _MK_MASK_CONST(0x3ff)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_READ_MASK                         _MK_MASK_CONST(0x3ff)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_FN_GI_INDIRECT_ACCESS_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_FN_GI_INDIRECT_ACCESS_FIELD                       _MK_FIELD_CONST(0x3ff, APS_FRSC_GI_INDIRECT_ACCESS_0_FN_GI_INDIRECT_ACCESS_SHIFT)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_FN_GI_INDIRECT_ACCESS_RANGE                       9:0
#define APS_FRSC_GI_INDIRECT_ACCESS_0_FN_GI_INDIRECT_ACCESS_WOFFSET                     0x0
#define APS_FRSC_GI_INDIRECT_ACCESS_0_FN_GI_INDIRECT_ACCESS_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_FN_GI_INDIRECT_ACCESS_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_FN_GI_INDIRECT_ACCESS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_INDIRECT_ACCESS_0_FN_GI_INDIRECT_ACCESS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_SC_MODEIN_0
#define APS_FRSC_SC_MODEIN_0                    _MK_ADDR_CONST(0x14)
#define APS_FRSC_SC_MODEIN_0_SECURE                     0x0
#define APS_FRSC_SC_MODEIN_0_SCR                        0
#define APS_FRSC_SC_MODEIN_0_WORD_COUNT                         0x1
#define APS_FRSC_SC_MODEIN_0_RESET_VAL                  _MK_MASK_CONST(0x29516)
#define APS_FRSC_SC_MODEIN_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
#define APS_FRSC_SC_MODEIN_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_MODEIN_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_MODEIN_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_SC_MODEIN_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff)
#define APS_FRSC_SC_MODEIN_0_FN_MODEIN_SHIFT                    _MK_SHIFT_CONST(0)
#define APS_FRSC_SC_MODEIN_0_FN_MODEIN_FIELD                    _MK_FIELD_CONST(0xffffff, APS_FRSC_SC_MODEIN_0_FN_MODEIN_SHIFT)
#define APS_FRSC_SC_MODEIN_0_FN_MODEIN_RANGE                    23:0
#define APS_FRSC_SC_MODEIN_0_FN_MODEIN_WOFFSET                  0x0
#define APS_FRSC_SC_MODEIN_0_FN_MODEIN_DEFAULT                  _MK_MASK_CONST(0x29516)
#define APS_FRSC_SC_MODEIN_0_FN_MODEIN_DEFAULT_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_SC_MODEIN_0_FN_MODEIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_SC_MODEIN_0_FN_MODEIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_ALARM_INJ_0
#define APS_FRSC_PGO_ALARM_INJ_0                        _MK_ADDR_CONST(0x18)
#define APS_FRSC_PGO_ALARM_INJ_0_SECURE                         0x0
#define APS_FRSC_PGO_ALARM_INJ_0_SCR                    0
#define APS_FRSC_PGO_ALARM_INJ_0_WORD_COUNT                     0x1
#define APS_FRSC_PGO_ALARM_INJ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_0_FN_PGO_ALARM_INJ_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_ALARM_INJ_0_FN_PGO_ALARM_INJ_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_ALARM_INJ_0_FN_PGO_ALARM_INJ_SHIFT)
#define APS_FRSC_PGO_ALARM_INJ_0_FN_PGO_ALARM_INJ_RANGE                 23:0
#define APS_FRSC_PGO_ALARM_INJ_0_FN_PGO_ALARM_INJ_WOFFSET                       0x0
#define APS_FRSC_PGO_ALARM_INJ_0_FN_PGO_ALARM_INJ_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_0_FN_PGO_ALARM_INJ_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_0_FN_PGO_ALARM_INJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_0_FN_PGO_ALARM_INJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_ALARM_INJ
#define APS_FRSC_PGO_ALARM_INJ                  _MK_ADDR_CONST(0x18)
#define APS_FRSC_PGO_ALARM_INJ_SECURE                   0x0
#define APS_FRSC_PGO_ALARM_INJ_SCR                      0
#define APS_FRSC_PGO_ALARM_INJ_WORD_COUNT                       0x1
#define APS_FRSC_PGO_ALARM_INJ_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_FN_PGO_ALARM_INJ_SHIFT                   _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_ALARM_INJ_FN_PGO_ALARM_INJ_FIELD                   _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_ALARM_INJ_FN_PGO_ALARM_INJ_SHIFT)
#define APS_FRSC_PGO_ALARM_INJ_FN_PGO_ALARM_INJ_RANGE                   23:0
#define APS_FRSC_PGO_ALARM_INJ_FN_PGO_ALARM_INJ_WOFFSET                 0x0
#define APS_FRSC_PGO_ALARM_INJ_FN_PGO_ALARM_INJ_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_FN_PGO_ALARM_INJ_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_FN_PGO_ALARM_INJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_FN_PGO_ALARM_INJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_ALARM_INJ_1
#define APS_FRSC_PGO_ALARM_INJ_1                        _MK_ADDR_CONST(0x1c)
#define APS_FRSC_PGO_ALARM_INJ_1_SECURE                         0x0
#define APS_FRSC_PGO_ALARM_INJ_1_SCR                    0
#define APS_FRSC_PGO_ALARM_INJ_1_WORD_COUNT                     0x1
#define APS_FRSC_PGO_ALARM_INJ_1_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_1_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_1_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_1_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_1_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_1_FN_PGO_ALARM_INJ_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_ALARM_INJ_1_FN_PGO_ALARM_INJ_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_ALARM_INJ_1_FN_PGO_ALARM_INJ_SHIFT)
#define APS_FRSC_PGO_ALARM_INJ_1_FN_PGO_ALARM_INJ_RANGE                 23:0
#define APS_FRSC_PGO_ALARM_INJ_1_FN_PGO_ALARM_INJ_WOFFSET                       0x0
#define APS_FRSC_PGO_ALARM_INJ_1_FN_PGO_ALARM_INJ_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_1_FN_PGO_ALARM_INJ_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARM_INJ_1_FN_PGO_ALARM_INJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARM_INJ_1_FN_PGO_ALARM_INJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_ALARMS_0
#define APS_FRSC_GI_ALARMS_0                    _MK_ADDR_CONST(0x20)
#define APS_FRSC_GI_ALARMS_0_SECURE                     0x0
#define APS_FRSC_GI_ALARMS_0_SCR                        0
#define APS_FRSC_GI_ALARMS_0_WORD_COUNT                         0x1
#define APS_FRSC_GI_ALARMS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_ALARMS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_ALARMS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_0_FN_GI_ALARMS_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_ALARMS_0_FN_GI_ALARMS_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_ALARMS_0_FN_GI_ALARMS_SHIFT)
#define APS_FRSC_GI_ALARMS_0_FN_GI_ALARMS_RANGE                 23:0
#define APS_FRSC_GI_ALARMS_0_FN_GI_ALARMS_WOFFSET                       0x0
#define APS_FRSC_GI_ALARMS_0_FN_GI_ALARMS_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_0_FN_GI_ALARMS_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_ALARMS_0_FN_GI_ALARMS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_0_FN_GI_ALARMS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_ALARMS
#define APS_FRSC_GI_ALARMS                      _MK_ADDR_CONST(0x20)
#define APS_FRSC_GI_ALARMS_SECURE                       0x0
#define APS_FRSC_GI_ALARMS_SCR                  0
#define APS_FRSC_GI_ALARMS_WORD_COUNT                   0x1
#define APS_FRSC_GI_ALARMS_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_ALARMS_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_ALARMS_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_FN_GI_ALARMS_SHIFT                   _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_ALARMS_FN_GI_ALARMS_FIELD                   _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_ALARMS_FN_GI_ALARMS_SHIFT)
#define APS_FRSC_GI_ALARMS_FN_GI_ALARMS_RANGE                   23:0
#define APS_FRSC_GI_ALARMS_FN_GI_ALARMS_WOFFSET                 0x0
#define APS_FRSC_GI_ALARMS_FN_GI_ALARMS_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_FN_GI_ALARMS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_ALARMS_FN_GI_ALARMS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_FN_GI_ALARMS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_ALARMS_1
#define APS_FRSC_GI_ALARMS_1                    _MK_ADDR_CONST(0x24)
#define APS_FRSC_GI_ALARMS_1_SECURE                     0x0
#define APS_FRSC_GI_ALARMS_1_SCR                        0
#define APS_FRSC_GI_ALARMS_1_WORD_COUNT                         0x1
#define APS_FRSC_GI_ALARMS_1_RESET_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_1_RESET_MASK                         _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_ALARMS_1_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_1_READ_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_ALARMS_1_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_1_FN_GI_ALARMS_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_ALARMS_1_FN_GI_ALARMS_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_ALARMS_1_FN_GI_ALARMS_SHIFT)
#define APS_FRSC_GI_ALARMS_1_FN_GI_ALARMS_RANGE                 23:0
#define APS_FRSC_GI_ALARMS_1_FN_GI_ALARMS_WOFFSET                       0x0
#define APS_FRSC_GI_ALARMS_1_FN_GI_ALARMS_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_1_FN_GI_ALARMS_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_ALARMS_1_FN_GI_ALARMS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_ALARMS_1_FN_GI_ALARMS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_CTXT_FA_0
#define APS_FRSC_GI_CTXT_FA_0                   _MK_ADDR_CONST(0x28)
#define APS_FRSC_GI_CTXT_FA_0_SECURE                    0x0
#define APS_FRSC_GI_CTXT_FA_0_SCR                       0
#define APS_FRSC_GI_CTXT_FA_0_WORD_COUNT                        0x1
#define APS_FRSC_GI_CTXT_FA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_0_RESET_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_FA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_0_READ_MASK                         _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_FA_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_0_FN_GI_CTXT_FA_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_CTXT_FA_0_FN_GI_CTXT_FA_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_CTXT_FA_0_FN_GI_CTXT_FA_SHIFT)
#define APS_FRSC_GI_CTXT_FA_0_FN_GI_CTXT_FA_RANGE                       23:0
#define APS_FRSC_GI_CTXT_FA_0_FN_GI_CTXT_FA_WOFFSET                     0x0
#define APS_FRSC_GI_CTXT_FA_0_FN_GI_CTXT_FA_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_0_FN_GI_CTXT_FA_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_FA_0_FN_GI_CTXT_FA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_0_FN_GI_CTXT_FA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_CTXT_FA
#define APS_FRSC_GI_CTXT_FA                     _MK_ADDR_CONST(0x28)
#define APS_FRSC_GI_CTXT_FA_SECURE                      0x0
#define APS_FRSC_GI_CTXT_FA_SCR                         0
#define APS_FRSC_GI_CTXT_FA_WORD_COUNT                  0x1
#define APS_FRSC_GI_CTXT_FA_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_RESET_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_FA_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_READ_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_FA_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_FN_GI_CTXT_FA_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_CTXT_FA_FN_GI_CTXT_FA_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_CTXT_FA_FN_GI_CTXT_FA_SHIFT)
#define APS_FRSC_GI_CTXT_FA_FN_GI_CTXT_FA_RANGE                 23:0
#define APS_FRSC_GI_CTXT_FA_FN_GI_CTXT_FA_WOFFSET                       0x0
#define APS_FRSC_GI_CTXT_FA_FN_GI_CTXT_FA_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_FN_GI_CTXT_FA_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_FA_FN_GI_CTXT_FA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_FN_GI_CTXT_FA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_CTXT_FA_1
#define APS_FRSC_GI_CTXT_FA_1                   _MK_ADDR_CONST(0x2c)
#define APS_FRSC_GI_CTXT_FA_1_SECURE                    0x0
#define APS_FRSC_GI_CTXT_FA_1_SCR                       0
#define APS_FRSC_GI_CTXT_FA_1_WORD_COUNT                        0x1
#define APS_FRSC_GI_CTXT_FA_1_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_1_RESET_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_FA_1_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_1_READ_MASK                         _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_FA_1_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_1_FN_GI_CTXT_FA_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_CTXT_FA_1_FN_GI_CTXT_FA_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_CTXT_FA_1_FN_GI_CTXT_FA_SHIFT)
#define APS_FRSC_GI_CTXT_FA_1_FN_GI_CTXT_FA_RANGE                       23:0
#define APS_FRSC_GI_CTXT_FA_1_FN_GI_CTXT_FA_WOFFSET                     0x0
#define APS_FRSC_GI_CTXT_FA_1_FN_GI_CTXT_FA_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_1_FN_GI_CTXT_FA_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_FA_1_FN_GI_CTXT_FA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FA_1_FN_GI_CTXT_FA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_EVENT_MASK_0
#define APS_FRSC_PGO_EVENT_MASK_0                       _MK_ADDR_CONST(0x30)
#define APS_FRSC_PGO_EVENT_MASK_0_SECURE                        0x0
#define APS_FRSC_PGO_EVENT_MASK_0_SCR                   0
#define APS_FRSC_PGO_EVENT_MASK_0_WORD_COUNT                    0x1
#define APS_FRSC_PGO_EVENT_MASK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_0_FN_PGO_EVENT_MASK_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_EVENT_MASK_0_FN_PGO_EVENT_MASK_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_EVENT_MASK_0_FN_PGO_EVENT_MASK_SHIFT)
#define APS_FRSC_PGO_EVENT_MASK_0_FN_PGO_EVENT_MASK_RANGE                       23:0
#define APS_FRSC_PGO_EVENT_MASK_0_FN_PGO_EVENT_MASK_WOFFSET                     0x0
#define APS_FRSC_PGO_EVENT_MASK_0_FN_PGO_EVENT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_0_FN_PGO_EVENT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_0_FN_PGO_EVENT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_0_FN_PGO_EVENT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_EVENT_MASK
#define APS_FRSC_PGO_EVENT_MASK                 _MK_ADDR_CONST(0x30)
#define APS_FRSC_PGO_EVENT_MASK_SECURE                  0x0
#define APS_FRSC_PGO_EVENT_MASK_SCR                     0
#define APS_FRSC_PGO_EVENT_MASK_WORD_COUNT                      0x1
#define APS_FRSC_PGO_EVENT_MASK_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_WRITE_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_FN_PGO_EVENT_MASK_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_EVENT_MASK_FN_PGO_EVENT_MASK_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_EVENT_MASK_FN_PGO_EVENT_MASK_SHIFT)
#define APS_FRSC_PGO_EVENT_MASK_FN_PGO_EVENT_MASK_RANGE                 23:0
#define APS_FRSC_PGO_EVENT_MASK_FN_PGO_EVENT_MASK_WOFFSET                       0x0
#define APS_FRSC_PGO_EVENT_MASK_FN_PGO_EVENT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_FN_PGO_EVENT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_FN_PGO_EVENT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_FN_PGO_EVENT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_EVENT_MASK_1
#define APS_FRSC_PGO_EVENT_MASK_1                       _MK_ADDR_CONST(0x34)
#define APS_FRSC_PGO_EVENT_MASK_1_SECURE                        0x0
#define APS_FRSC_PGO_EVENT_MASK_1_SCR                   0
#define APS_FRSC_PGO_EVENT_MASK_1_WORD_COUNT                    0x1
#define APS_FRSC_PGO_EVENT_MASK_1_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_1_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_1_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_1_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_1_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_1_FN_PGO_EVENT_MASK_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_EVENT_MASK_1_FN_PGO_EVENT_MASK_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_EVENT_MASK_1_FN_PGO_EVENT_MASK_SHIFT)
#define APS_FRSC_PGO_EVENT_MASK_1_FN_PGO_EVENT_MASK_RANGE                       23:0
#define APS_FRSC_PGO_EVENT_MASK_1_FN_PGO_EVENT_MASK_WOFFSET                     0x0
#define APS_FRSC_PGO_EVENT_MASK_1_FN_PGO_EVENT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_1_FN_PGO_EVENT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_EVENT_MASK_1_FN_PGO_EVENT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_EVENT_MASK_1_FN_PGO_EVENT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_ALARMS_ROUTING_0A_0
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0                        _MK_ADDR_CONST(0x38)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_SECURE                         0x0
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_SCR                    0
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_WORD_COUNT                     0x1
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_RESET_VAL                      _MK_MASK_CONST(0xaae02a)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_FN_PGO_ALARMS_ROUTING_0A_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_FN_PGO_ALARMS_ROUTING_0A_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_ALARMS_ROUTING_0A_0_FN_PGO_ALARMS_ROUTING_0A_SHIFT)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_FN_PGO_ALARMS_ROUTING_0A_RANGE                 23:0
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_FN_PGO_ALARMS_ROUTING_0A_WOFFSET                       0x0
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_FN_PGO_ALARMS_ROUTING_0A_DEFAULT                       _MK_MASK_CONST(0xaae02a)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_FN_PGO_ALARMS_ROUTING_0A_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_FN_PGO_ALARMS_ROUTING_0A_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_0A_0_FN_PGO_ALARMS_ROUTING_0A_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_ALARMS_ROUTING_0B_0
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0                        _MK_ADDR_CONST(0x3c)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_SECURE                         0x0
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_SCR                    0
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_WORD_COUNT                     0x1
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_RESET_VAL                      _MK_MASK_CONST(0x80aaaa)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_FN_PGO_ALARMS_ROUTING_0B_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_FN_PGO_ALARMS_ROUTING_0B_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_ALARMS_ROUTING_0B_0_FN_PGO_ALARMS_ROUTING_0B_SHIFT)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_FN_PGO_ALARMS_ROUTING_0B_RANGE                 23:0
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_FN_PGO_ALARMS_ROUTING_0B_WOFFSET                       0x0
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_FN_PGO_ALARMS_ROUTING_0B_DEFAULT                       _MK_MASK_CONST(0x80aaaa)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_FN_PGO_ALARMS_ROUTING_0B_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_FN_PGO_ALARMS_ROUTING_0B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_0B_0_FN_PGO_ALARMS_ROUTING_0B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_ALARMS_ROUTING_1A_0
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0                        _MK_ADDR_CONST(0x40)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_SECURE                         0x0
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_SCR                    0
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_WORD_COUNT                     0x1
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_RESET_VAL                      _MK_MASK_CONST(0xe8e8e8)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_FN_PGO_ALARMS_ROUTING_1A_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_FN_PGO_ALARMS_ROUTING_1A_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_ALARMS_ROUTING_1A_0_FN_PGO_ALARMS_ROUTING_1A_SHIFT)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_FN_PGO_ALARMS_ROUTING_1A_RANGE                 23:0
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_FN_PGO_ALARMS_ROUTING_1A_WOFFSET                       0x0
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_FN_PGO_ALARMS_ROUTING_1A_DEFAULT                       _MK_MASK_CONST(0xe8e8e8)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_FN_PGO_ALARMS_ROUTING_1A_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_FN_PGO_ALARMS_ROUTING_1A_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_1A_0_FN_PGO_ALARMS_ROUTING_1A_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_ALARMS_ROUTING_1B_0
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0                        _MK_ADDR_CONST(0x44)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_SECURE                         0x0
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_SCR                    0
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_WORD_COUNT                     0x1
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_RESET_VAL                      _MK_MASK_CONST(0xa00e8)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_FN_PGO_ALARMS_ROUTING_1B_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_FN_PGO_ALARMS_ROUTING_1B_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_ALARMS_ROUTING_1B_0_FN_PGO_ALARMS_ROUTING_1B_SHIFT)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_FN_PGO_ALARMS_ROUTING_1B_RANGE                 23:0
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_FN_PGO_ALARMS_ROUTING_1B_WOFFSET                       0x0
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_FN_PGO_ALARMS_ROUTING_1B_DEFAULT                       _MK_MASK_CONST(0xa00e8)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_FN_PGO_ALARMS_ROUTING_1B_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_FN_PGO_ALARMS_ROUTING_1B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_ALARMS_ROUTING_1B_0_FN_PGO_ALARMS_ROUTING_1B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_LOGS_RST_0
#define APS_FRSC_PGO_LOGS_RST_0                 _MK_ADDR_CONST(0x48)
#define APS_FRSC_PGO_LOGS_RST_0_SECURE                  0x0
#define APS_FRSC_PGO_LOGS_RST_0_SCR                     0
#define APS_FRSC_PGO_LOGS_RST_0_WORD_COUNT                      0x1
#define APS_FRSC_PGO_LOGS_RST_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_LOGS_RST_0_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_LOGS_RST_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_LOGS_RST_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_LOGS_RST_0_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_LOGS_RST_0_WRITE_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_LOGS_RST_0_FN_PGO_LOGS_RST_SHIFT                   _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_LOGS_RST_0_FN_PGO_LOGS_RST_FIELD                   _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_LOGS_RST_0_FN_PGO_LOGS_RST_SHIFT)
#define APS_FRSC_PGO_LOGS_RST_0_FN_PGO_LOGS_RST_RANGE                   23:0
#define APS_FRSC_PGO_LOGS_RST_0_FN_PGO_LOGS_RST_WOFFSET                 0x0
#define APS_FRSC_PGO_LOGS_RST_0_FN_PGO_LOGS_RST_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_LOGS_RST_0_FN_PGO_LOGS_RST_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_LOGS_RST_0_FN_PGO_LOGS_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_LOGS_RST_0_FN_PGO_LOGS_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_DUMMYADR_0
#define APS_FRSC_PGO_DUMMYADR_0                 _MK_ADDR_CONST(0x4c)
#define APS_FRSC_PGO_DUMMYADR_0_SECURE                  0x0
#define APS_FRSC_PGO_DUMMYADR_0_SCR                     0
#define APS_FRSC_PGO_DUMMYADR_0_WORD_COUNT                      0x1
#define APS_FRSC_PGO_DUMMYADR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_DUMMYADR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define APS_FRSC_PGO_DUMMYADR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_DUMMYADR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_DUMMYADR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define APS_FRSC_PGO_DUMMYADR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_B_SHIFT                 _MK_SHIFT_CONST(24)
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_B_FIELD                 _MK_FIELD_CONST(0xff, APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_B_SHIFT)
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_B_RANGE                 31:24
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_B_WOFFSET                       0x0
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_B_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_B_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_A_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_A_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_A_SHIFT)
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_A_RANGE                 23:0
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_A_WOFFSET                       0x0
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_A_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_A_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_A_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_DUMMYADR_0_FN_PGO_DUMMYADR_A_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_0
#define APS_FRSC_PGO_MISC_0                     _MK_ADDR_CONST(0x50)
#define APS_FRSC_PGO_MISC_0_SECURE                      0x0
#define APS_FRSC_PGO_MISC_0_SCR                         0
#define APS_FRSC_PGO_MISC_0_WORD_COUNT                  0x1
#define APS_FRSC_PGO_MISC_0_RESET_VAL                   _MK_MASK_CONST(0x290063)
#define APS_FRSC_PGO_MISC_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_0_FN_PGO_MISC_SHIFT                   _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_0_FN_PGO_MISC_FIELD                   _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_0_FN_PGO_MISC_SHIFT)
#define APS_FRSC_PGO_MISC_0_FN_PGO_MISC_RANGE                   23:0
#define APS_FRSC_PGO_MISC_0_FN_PGO_MISC_WOFFSET                 0x0
#define APS_FRSC_PGO_MISC_0_FN_PGO_MISC_DEFAULT                 _MK_MASK_CONST(0x290063)
#define APS_FRSC_PGO_MISC_0_FN_PGO_MISC_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_0_FN_PGO_MISC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_0_FN_PGO_MISC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_1_0
#define APS_FRSC_PGO_MISC_PGO_1_0                       _MK_ADDR_CONST(0x54)
#define APS_FRSC_PGO_MISC_PGO_1_0_SECURE                        0x0
#define APS_FRSC_PGO_MISC_PGO_1_0_SCR                   0
#define APS_FRSC_PGO_MISC_PGO_1_0_WORD_COUNT                    0x1
#define APS_FRSC_PGO_MISC_PGO_1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_1_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_1_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_1_0_FN_PERIPH_PGO_1_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_1_0_FN_PERIPH_PGO_1_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_1_0_FN_PERIPH_PGO_1_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_1_0_FN_PERIPH_PGO_1_RANGE                 23:0
#define APS_FRSC_PGO_MISC_PGO_1_0_FN_PERIPH_PGO_1_WOFFSET                       0x0
#define APS_FRSC_PGO_MISC_PGO_1_0_FN_PERIPH_PGO_1_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_1_0_FN_PERIPH_PGO_1_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_1_0_FN_PERIPH_PGO_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_1_0_FN_PERIPH_PGO_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_2_0
#define APS_FRSC_PGO_MISC_PGO_2_0                       _MK_ADDR_CONST(0x58)
#define APS_FRSC_PGO_MISC_PGO_2_0_SECURE                        0x0
#define APS_FRSC_PGO_MISC_PGO_2_0_SCR                   0
#define APS_FRSC_PGO_MISC_PGO_2_0_WORD_COUNT                    0x1
#define APS_FRSC_PGO_MISC_PGO_2_0_RESET_VAL                     _MK_MASK_CONST(0xaa5500)
#define APS_FRSC_PGO_MISC_PGO_2_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_2_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_2_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_2_0_FN_PERIPH_PGO_2_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_2_0_FN_PERIPH_PGO_2_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_2_0_FN_PERIPH_PGO_2_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_2_0_FN_PERIPH_PGO_2_RANGE                 23:0
#define APS_FRSC_PGO_MISC_PGO_2_0_FN_PERIPH_PGO_2_WOFFSET                       0x0
#define APS_FRSC_PGO_MISC_PGO_2_0_FN_PERIPH_PGO_2_DEFAULT                       _MK_MASK_CONST(0xaa5500)
#define APS_FRSC_PGO_MISC_PGO_2_0_FN_PERIPH_PGO_2_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_2_0_FN_PERIPH_PGO_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_2_0_FN_PERIPH_PGO_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_3_0
#define APS_FRSC_PGO_MISC_PGO_3_0                       _MK_ADDR_CONST(0x5c)
#define APS_FRSC_PGO_MISC_PGO_3_0_SECURE                        0x0
#define APS_FRSC_PGO_MISC_PGO_3_0_SCR                   0
#define APS_FRSC_PGO_MISC_PGO_3_0_WORD_COUNT                    0x1
#define APS_FRSC_PGO_MISC_PGO_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_3_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_3_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_3_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_3_0_FN_PERIPH_PGO_3_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_3_0_FN_PERIPH_PGO_3_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_3_0_FN_PERIPH_PGO_3_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_3_0_FN_PERIPH_PGO_3_RANGE                 23:0
#define APS_FRSC_PGO_MISC_PGO_3_0_FN_PERIPH_PGO_3_WOFFSET                       0x0
#define APS_FRSC_PGO_MISC_PGO_3_0_FN_PERIPH_PGO_3_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_3_0_FN_PERIPH_PGO_3_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_3_0_FN_PERIPH_PGO_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_3_0_FN_PERIPH_PGO_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_4_0
#define APS_FRSC_PGO_MISC_PGO_4_0                       _MK_ADDR_CONST(0x60)
#define APS_FRSC_PGO_MISC_PGO_4_0_SECURE                        0x0
#define APS_FRSC_PGO_MISC_PGO_4_0_SCR                   0
#define APS_FRSC_PGO_MISC_PGO_4_0_WORD_COUNT                    0x1
#define APS_FRSC_PGO_MISC_PGO_4_0_RESET_VAL                     _MK_MASK_CONST(0x100000)
#define APS_FRSC_PGO_MISC_PGO_4_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_4_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_4_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_4_0_FN_PERIPH_PGO_4_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_4_0_FN_PERIPH_PGO_4_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_4_0_FN_PERIPH_PGO_4_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_4_0_FN_PERIPH_PGO_4_RANGE                 23:0
#define APS_FRSC_PGO_MISC_PGO_4_0_FN_PERIPH_PGO_4_WOFFSET                       0x0
#define APS_FRSC_PGO_MISC_PGO_4_0_FN_PERIPH_PGO_4_DEFAULT                       _MK_MASK_CONST(0x100000)
#define APS_FRSC_PGO_MISC_PGO_4_0_FN_PERIPH_PGO_4_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_4_0_FN_PERIPH_PGO_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_4_0_FN_PERIPH_PGO_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_5_0
#define APS_FRSC_PGO_MISC_PGO_5_0                       _MK_ADDR_CONST(0x64)
#define APS_FRSC_PGO_MISC_PGO_5_0_SECURE                        0x0
#define APS_FRSC_PGO_MISC_PGO_5_0_SCR                   0
#define APS_FRSC_PGO_MISC_PGO_5_0_WORD_COUNT                    0x1
#define APS_FRSC_PGO_MISC_PGO_5_0_RESET_VAL                     _MK_MASK_CONST(0xd0b480)
#define APS_FRSC_PGO_MISC_PGO_5_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_5_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_5_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_5_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_5_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_5_0_FN_PERIPH_PGO_5_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_5_0_FN_PERIPH_PGO_5_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_5_0_FN_PERIPH_PGO_5_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_5_0_FN_PERIPH_PGO_5_RANGE                 23:0
#define APS_FRSC_PGO_MISC_PGO_5_0_FN_PERIPH_PGO_5_WOFFSET                       0x0
#define APS_FRSC_PGO_MISC_PGO_5_0_FN_PERIPH_PGO_5_DEFAULT                       _MK_MASK_CONST(0xd0b480)
#define APS_FRSC_PGO_MISC_PGO_5_0_FN_PERIPH_PGO_5_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_5_0_FN_PERIPH_PGO_5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_5_0_FN_PERIPH_PGO_5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_6_0
#define APS_FRSC_PGO_MISC_PGO_6_0                       _MK_ADDR_CONST(0x68)
#define APS_FRSC_PGO_MISC_PGO_6_0_SECURE                        0x0
#define APS_FRSC_PGO_MISC_PGO_6_0_SCR                   0
#define APS_FRSC_PGO_MISC_PGO_6_0_WORD_COUNT                    0x1
#define APS_FRSC_PGO_MISC_PGO_6_0_RESET_VAL                     _MK_MASK_CONST(0x903)
#define APS_FRSC_PGO_MISC_PGO_6_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_6_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_6_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_6_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_6_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_6_0_FN_PERIPH_PGO_6_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_6_0_FN_PERIPH_PGO_6_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_6_0_FN_PERIPH_PGO_6_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_6_0_FN_PERIPH_PGO_6_RANGE                 23:0
#define APS_FRSC_PGO_MISC_PGO_6_0_FN_PERIPH_PGO_6_WOFFSET                       0x0
#define APS_FRSC_PGO_MISC_PGO_6_0_FN_PERIPH_PGO_6_DEFAULT                       _MK_MASK_CONST(0x903)
#define APS_FRSC_PGO_MISC_PGO_6_0_FN_PERIPH_PGO_6_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_6_0_FN_PERIPH_PGO_6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_6_0_FN_PERIPH_PGO_6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_7_0
#define APS_FRSC_PGO_MISC_PGO_7_0                       _MK_ADDR_CONST(0x6c)
#define APS_FRSC_PGO_MISC_PGO_7_0_SECURE                        0x0
#define APS_FRSC_PGO_MISC_PGO_7_0_SCR                   0
#define APS_FRSC_PGO_MISC_PGO_7_0_WORD_COUNT                    0x1
#define APS_FRSC_PGO_MISC_PGO_7_0_RESET_VAL                     _MK_MASK_CONST(0xf000)
#define APS_FRSC_PGO_MISC_PGO_7_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_7_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_7_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_7_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_7_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_7_0_FN_PERIPH_PGO_7_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_7_0_FN_PERIPH_PGO_7_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_7_0_FN_PERIPH_PGO_7_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_7_0_FN_PERIPH_PGO_7_RANGE                 23:0
#define APS_FRSC_PGO_MISC_PGO_7_0_FN_PERIPH_PGO_7_WOFFSET                       0x0
#define APS_FRSC_PGO_MISC_PGO_7_0_FN_PERIPH_PGO_7_DEFAULT                       _MK_MASK_CONST(0xf000)
#define APS_FRSC_PGO_MISC_PGO_7_0_FN_PERIPH_PGO_7_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_7_0_FN_PERIPH_PGO_7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_7_0_FN_PERIPH_PGO_7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_8_0
#define APS_FRSC_PGO_MISC_PGO_8_0                       _MK_ADDR_CONST(0x70)
#define APS_FRSC_PGO_MISC_PGO_8_0_SECURE                        0x0
#define APS_FRSC_PGO_MISC_PGO_8_0_SCR                   0
#define APS_FRSC_PGO_MISC_PGO_8_0_WORD_COUNT                    0x1
#define APS_FRSC_PGO_MISC_PGO_8_0_RESET_VAL                     _MK_MASK_CONST(0x2)
#define APS_FRSC_PGO_MISC_PGO_8_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_8_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_8_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_8_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_8_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_8_0_FN_PERIPH_PGO_8_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_8_0_FN_PERIPH_PGO_8_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_8_0_FN_PERIPH_PGO_8_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_8_0_FN_PERIPH_PGO_8_RANGE                 23:0
#define APS_FRSC_PGO_MISC_PGO_8_0_FN_PERIPH_PGO_8_WOFFSET                       0x0
#define APS_FRSC_PGO_MISC_PGO_8_0_FN_PERIPH_PGO_8_DEFAULT                       _MK_MASK_CONST(0x2)
#define APS_FRSC_PGO_MISC_PGO_8_0_FN_PERIPH_PGO_8_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_8_0_FN_PERIPH_PGO_8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_8_0_FN_PERIPH_PGO_8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_9_0
#define APS_FRSC_PGO_MISC_PGO_9_0                       _MK_ADDR_CONST(0x74)
#define APS_FRSC_PGO_MISC_PGO_9_0_SECURE                        0x0
#define APS_FRSC_PGO_MISC_PGO_9_0_SCR                   0
#define APS_FRSC_PGO_MISC_PGO_9_0_WORD_COUNT                    0x1
#define APS_FRSC_PGO_MISC_PGO_9_0_RESET_VAL                     _MK_MASK_CONST(0x1e)
#define APS_FRSC_PGO_MISC_PGO_9_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_9_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_9_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_9_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_9_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_9_0_FN_PERIPH_PGO_9_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_9_0_FN_PERIPH_PGO_9_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_9_0_FN_PERIPH_PGO_9_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_9_0_FN_PERIPH_PGO_9_RANGE                 23:0
#define APS_FRSC_PGO_MISC_PGO_9_0_FN_PERIPH_PGO_9_WOFFSET                       0x0
#define APS_FRSC_PGO_MISC_PGO_9_0_FN_PERIPH_PGO_9_DEFAULT                       _MK_MASK_CONST(0x1e)
#define APS_FRSC_PGO_MISC_PGO_9_0_FN_PERIPH_PGO_9_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_9_0_FN_PERIPH_PGO_9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_9_0_FN_PERIPH_PGO_9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_10_0
#define APS_FRSC_PGO_MISC_PGO_10_0                      _MK_ADDR_CONST(0x78)
#define APS_FRSC_PGO_MISC_PGO_10_0_SECURE                       0x0
#define APS_FRSC_PGO_MISC_PGO_10_0_SCR                  0
#define APS_FRSC_PGO_MISC_PGO_10_0_WORD_COUNT                   0x1
#define APS_FRSC_PGO_MISC_PGO_10_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_10_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_10_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_10_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_10_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_10_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_10_0_FN_PERIPH_PGO_10_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_10_0_FN_PERIPH_PGO_10_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_10_0_FN_PERIPH_PGO_10_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_10_0_FN_PERIPH_PGO_10_RANGE                       23:0
#define APS_FRSC_PGO_MISC_PGO_10_0_FN_PERIPH_PGO_10_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_PGO_10_0_FN_PERIPH_PGO_10_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_10_0_FN_PERIPH_PGO_10_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_10_0_FN_PERIPH_PGO_10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_10_0_FN_PERIPH_PGO_10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_11_0
#define APS_FRSC_PGO_MISC_PGO_11_0                      _MK_ADDR_CONST(0x7c)
#define APS_FRSC_PGO_MISC_PGO_11_0_SECURE                       0x0
#define APS_FRSC_PGO_MISC_PGO_11_0_SCR                  0
#define APS_FRSC_PGO_MISC_PGO_11_0_WORD_COUNT                   0x1
#define APS_FRSC_PGO_MISC_PGO_11_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_11_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_11_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_11_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_11_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_11_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_11_0_FN_PERIPH_PGO_11_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_11_0_FN_PERIPH_PGO_11_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_11_0_FN_PERIPH_PGO_11_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_11_0_FN_PERIPH_PGO_11_RANGE                       23:0
#define APS_FRSC_PGO_MISC_PGO_11_0_FN_PERIPH_PGO_11_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_PGO_11_0_FN_PERIPH_PGO_11_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_11_0_FN_PERIPH_PGO_11_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_11_0_FN_PERIPH_PGO_11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_11_0_FN_PERIPH_PGO_11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_12_0
#define APS_FRSC_PGO_MISC_PGO_12_0                      _MK_ADDR_CONST(0x80)
#define APS_FRSC_PGO_MISC_PGO_12_0_SECURE                       0x0
#define APS_FRSC_PGO_MISC_PGO_12_0_SCR                  0
#define APS_FRSC_PGO_MISC_PGO_12_0_WORD_COUNT                   0x1
#define APS_FRSC_PGO_MISC_PGO_12_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_12_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_12_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_12_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_12_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_12_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_12_0_FN_PERIPH_PGO_12_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_12_0_FN_PERIPH_PGO_12_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_12_0_FN_PERIPH_PGO_12_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_12_0_FN_PERIPH_PGO_12_RANGE                       23:0
#define APS_FRSC_PGO_MISC_PGO_12_0_FN_PERIPH_PGO_12_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_PGO_12_0_FN_PERIPH_PGO_12_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_12_0_FN_PERIPH_PGO_12_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_12_0_FN_PERIPH_PGO_12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_12_0_FN_PERIPH_PGO_12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_13_0
#define APS_FRSC_PGO_MISC_PGO_13_0                      _MK_ADDR_CONST(0x84)
#define APS_FRSC_PGO_MISC_PGO_13_0_SECURE                       0x0
#define APS_FRSC_PGO_MISC_PGO_13_0_SCR                  0
#define APS_FRSC_PGO_MISC_PGO_13_0_WORD_COUNT                   0x1
#define APS_FRSC_PGO_MISC_PGO_13_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_13_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_13_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_13_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_13_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_13_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_13_0_FN_PERIPH_PGO_13_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_13_0_FN_PERIPH_PGO_13_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_13_0_FN_PERIPH_PGO_13_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_13_0_FN_PERIPH_PGO_13_RANGE                       23:0
#define APS_FRSC_PGO_MISC_PGO_13_0_FN_PERIPH_PGO_13_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_PGO_13_0_FN_PERIPH_PGO_13_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_13_0_FN_PERIPH_PGO_13_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_13_0_FN_PERIPH_PGO_13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_13_0_FN_PERIPH_PGO_13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_14_0
#define APS_FRSC_PGO_MISC_PGO_14_0                      _MK_ADDR_CONST(0x88)
#define APS_FRSC_PGO_MISC_PGO_14_0_SECURE                       0x0
#define APS_FRSC_PGO_MISC_PGO_14_0_SCR                  0
#define APS_FRSC_PGO_MISC_PGO_14_0_WORD_COUNT                   0x1
#define APS_FRSC_PGO_MISC_PGO_14_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_14_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_14_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_14_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_14_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_14_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_14_0_FN_PERIPH_PGO_14_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_14_0_FN_PERIPH_PGO_14_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_14_0_FN_PERIPH_PGO_14_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_14_0_FN_PERIPH_PGO_14_RANGE                       23:0
#define APS_FRSC_PGO_MISC_PGO_14_0_FN_PERIPH_PGO_14_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_PGO_14_0_FN_PERIPH_PGO_14_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_14_0_FN_PERIPH_PGO_14_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_14_0_FN_PERIPH_PGO_14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_14_0_FN_PERIPH_PGO_14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_PGO_15_0
#define APS_FRSC_PGO_MISC_PGO_15_0                      _MK_ADDR_CONST(0x8c)
#define APS_FRSC_PGO_MISC_PGO_15_0_SECURE                       0x0
#define APS_FRSC_PGO_MISC_PGO_15_0_SCR                  0
#define APS_FRSC_PGO_MISC_PGO_15_0_WORD_COUNT                   0x1
#define APS_FRSC_PGO_MISC_PGO_15_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_15_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_15_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_15_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_15_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_15_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_15_0_FN_PERIPH_PGO_15_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_PGO_15_0_FN_PERIPH_PGO_15_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_PGO_15_0_FN_PERIPH_PGO_15_SHIFT)
#define APS_FRSC_PGO_MISC_PGO_15_0_FN_PERIPH_PGO_15_RANGE                       23:0
#define APS_FRSC_PGO_MISC_PGO_15_0_FN_PERIPH_PGO_15_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_PGO_15_0_FN_PERIPH_PGO_15_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_15_0_FN_PERIPH_PGO_15_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_PGO_15_0_FN_PERIPH_PGO_15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_PGO_15_0_FN_PERIPH_PGO_15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_0
#define APS_FRSC_PGO_MISC_GI_0                  _MK_ADDR_CONST(0x90)
#define APS_FRSC_PGO_MISC_GI_0_SECURE                   0x0
#define APS_FRSC_PGO_MISC_GI_0_SCR                      0
#define APS_FRSC_PGO_MISC_GI_0_WORD_COUNT                       0x1
#define APS_FRSC_PGO_MISC_GI_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_0_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_0_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_0_FN_PERIPH_GI_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_0_FN_PERIPH_GI_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_0_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_0_FN_PERIPH_GI_RANGE                       23:0
#define APS_FRSC_PGO_MISC_GI_0_FN_PERIPH_GI_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_GI_0_FN_PERIPH_GI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_0_FN_PERIPH_GI_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_0_FN_PERIPH_GI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_0_FN_PERIPH_GI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI
#define APS_FRSC_PGO_MISC_GI                    _MK_ADDR_CONST(0x90)
#define APS_FRSC_PGO_MISC_GI_SECURE                     0x0
#define APS_FRSC_PGO_MISC_GI_SCR                        0
#define APS_FRSC_PGO_MISC_GI_WORD_COUNT                         0x1
#define APS_FRSC_PGO_MISC_GI_RESET_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_RESET_MASK                         _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_READ_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_FN_PERIPH_GI_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_FN_PERIPH_GI_FIELD                 _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_FN_PERIPH_GI_RANGE                 23:0
#define APS_FRSC_PGO_MISC_GI_FN_PERIPH_GI_WOFFSET                       0x0
#define APS_FRSC_PGO_MISC_GI_FN_PERIPH_GI_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_FN_PERIPH_GI_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_FN_PERIPH_GI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_FN_PERIPH_GI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_1
#define APS_FRSC_PGO_MISC_GI_1                  _MK_ADDR_CONST(0x94)
#define APS_FRSC_PGO_MISC_GI_1_SECURE                   0x0
#define APS_FRSC_PGO_MISC_GI_1_SCR                      0
#define APS_FRSC_PGO_MISC_GI_1_WORD_COUNT                       0x1
#define APS_FRSC_PGO_MISC_GI_1_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_1_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_1_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_1_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_1_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_1_FN_PERIPH_GI_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_1_FN_PERIPH_GI_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_1_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_1_FN_PERIPH_GI_RANGE                       23:0
#define APS_FRSC_PGO_MISC_GI_1_FN_PERIPH_GI_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_GI_1_FN_PERIPH_GI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_1_FN_PERIPH_GI_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_1_FN_PERIPH_GI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_1_FN_PERIPH_GI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_2
#define APS_FRSC_PGO_MISC_GI_2                  _MK_ADDR_CONST(0x98)
#define APS_FRSC_PGO_MISC_GI_2_SECURE                   0x0
#define APS_FRSC_PGO_MISC_GI_2_SCR                      0
#define APS_FRSC_PGO_MISC_GI_2_WORD_COUNT                       0x1
#define APS_FRSC_PGO_MISC_GI_2_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_2_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_2_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_2_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_2_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_2_FN_PERIPH_GI_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_2_FN_PERIPH_GI_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_2_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_2_FN_PERIPH_GI_RANGE                       23:0
#define APS_FRSC_PGO_MISC_GI_2_FN_PERIPH_GI_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_GI_2_FN_PERIPH_GI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_2_FN_PERIPH_GI_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_2_FN_PERIPH_GI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_2_FN_PERIPH_GI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_3
#define APS_FRSC_PGO_MISC_GI_3                  _MK_ADDR_CONST(0x9c)
#define APS_FRSC_PGO_MISC_GI_3_SECURE                   0x0
#define APS_FRSC_PGO_MISC_GI_3_SCR                      0
#define APS_FRSC_PGO_MISC_GI_3_WORD_COUNT                       0x1
#define APS_FRSC_PGO_MISC_GI_3_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_3_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_3_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_3_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_3_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_3_FN_PERIPH_GI_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_3_FN_PERIPH_GI_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_3_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_3_FN_PERIPH_GI_RANGE                       23:0
#define APS_FRSC_PGO_MISC_GI_3_FN_PERIPH_GI_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_GI_3_FN_PERIPH_GI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_3_FN_PERIPH_GI_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_3_FN_PERIPH_GI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_3_FN_PERIPH_GI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_4
#define APS_FRSC_PGO_MISC_GI_4                  _MK_ADDR_CONST(0xa0)
#define APS_FRSC_PGO_MISC_GI_4_SECURE                   0x0
#define APS_FRSC_PGO_MISC_GI_4_SCR                      0
#define APS_FRSC_PGO_MISC_GI_4_WORD_COUNT                       0x1
#define APS_FRSC_PGO_MISC_GI_4_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_4_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_4_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_4_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_4_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_4_FN_PERIPH_GI_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_4_FN_PERIPH_GI_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_4_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_4_FN_PERIPH_GI_RANGE                       23:0
#define APS_FRSC_PGO_MISC_GI_4_FN_PERIPH_GI_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_GI_4_FN_PERIPH_GI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_4_FN_PERIPH_GI_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_4_FN_PERIPH_GI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_4_FN_PERIPH_GI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_5
#define APS_FRSC_PGO_MISC_GI_5                  _MK_ADDR_CONST(0xa4)
#define APS_FRSC_PGO_MISC_GI_5_SECURE                   0x0
#define APS_FRSC_PGO_MISC_GI_5_SCR                      0
#define APS_FRSC_PGO_MISC_GI_5_WORD_COUNT                       0x1
#define APS_FRSC_PGO_MISC_GI_5_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_5_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_5_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_5_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_5_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_5_FN_PERIPH_GI_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_5_FN_PERIPH_GI_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_5_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_5_FN_PERIPH_GI_RANGE                       23:0
#define APS_FRSC_PGO_MISC_GI_5_FN_PERIPH_GI_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_GI_5_FN_PERIPH_GI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_5_FN_PERIPH_GI_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_5_FN_PERIPH_GI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_5_FN_PERIPH_GI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_6
#define APS_FRSC_PGO_MISC_GI_6                  _MK_ADDR_CONST(0xa8)
#define APS_FRSC_PGO_MISC_GI_6_SECURE                   0x0
#define APS_FRSC_PGO_MISC_GI_6_SCR                      0
#define APS_FRSC_PGO_MISC_GI_6_WORD_COUNT                       0x1
#define APS_FRSC_PGO_MISC_GI_6_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_6_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_6_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_6_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_6_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_6_FN_PERIPH_GI_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_6_FN_PERIPH_GI_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_6_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_6_FN_PERIPH_GI_RANGE                       23:0
#define APS_FRSC_PGO_MISC_GI_6_FN_PERIPH_GI_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_GI_6_FN_PERIPH_GI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_6_FN_PERIPH_GI_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_6_FN_PERIPH_GI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_6_FN_PERIPH_GI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_7
#define APS_FRSC_PGO_MISC_GI_7                  _MK_ADDR_CONST(0xac)
#define APS_FRSC_PGO_MISC_GI_7_SECURE                   0x0
#define APS_FRSC_PGO_MISC_GI_7_SCR                      0
#define APS_FRSC_PGO_MISC_GI_7_WORD_COUNT                       0x1
#define APS_FRSC_PGO_MISC_GI_7_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_7_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_7_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_7_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_7_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_7_FN_PERIPH_GI_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_7_FN_PERIPH_GI_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_7_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_7_FN_PERIPH_GI_RANGE                       23:0
#define APS_FRSC_PGO_MISC_GI_7_FN_PERIPH_GI_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_GI_7_FN_PERIPH_GI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_7_FN_PERIPH_GI_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_7_FN_PERIPH_GI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_7_FN_PERIPH_GI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_8
#define APS_FRSC_PGO_MISC_GI_8                  _MK_ADDR_CONST(0xb0)
#define APS_FRSC_PGO_MISC_GI_8_SECURE                   0x0
#define APS_FRSC_PGO_MISC_GI_8_SCR                      0
#define APS_FRSC_PGO_MISC_GI_8_WORD_COUNT                       0x1
#define APS_FRSC_PGO_MISC_GI_8_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_8_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_8_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_8_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_8_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_8_FN_PERIPH_GI_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_8_FN_PERIPH_GI_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_8_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_8_FN_PERIPH_GI_RANGE                       23:0
#define APS_FRSC_PGO_MISC_GI_8_FN_PERIPH_GI_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_GI_8_FN_PERIPH_GI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_8_FN_PERIPH_GI_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_8_FN_PERIPH_GI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_8_FN_PERIPH_GI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_9
#define APS_FRSC_PGO_MISC_GI_9                  _MK_ADDR_CONST(0xb4)
#define APS_FRSC_PGO_MISC_GI_9_SECURE                   0x0
#define APS_FRSC_PGO_MISC_GI_9_SCR                      0
#define APS_FRSC_PGO_MISC_GI_9_WORD_COUNT                       0x1
#define APS_FRSC_PGO_MISC_GI_9_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_9_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_9_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_9_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_9_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_9_FN_PERIPH_GI_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_9_FN_PERIPH_GI_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_9_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_9_FN_PERIPH_GI_RANGE                       23:0
#define APS_FRSC_PGO_MISC_GI_9_FN_PERIPH_GI_WOFFSET                     0x0
#define APS_FRSC_PGO_MISC_GI_9_FN_PERIPH_GI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_9_FN_PERIPH_GI_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_9_FN_PERIPH_GI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_9_FN_PERIPH_GI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_10
#define APS_FRSC_PGO_MISC_GI_10                 _MK_ADDR_CONST(0xb8)
#define APS_FRSC_PGO_MISC_GI_10_SECURE                  0x0
#define APS_FRSC_PGO_MISC_GI_10_SCR                     0
#define APS_FRSC_PGO_MISC_GI_10_WORD_COUNT                      0x1
#define APS_FRSC_PGO_MISC_GI_10_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_10_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_10_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_10_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_10_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_10_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_10_FN_PERIPH_GI_SHIFT                      _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_10_FN_PERIPH_GI_FIELD                      _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_10_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_10_FN_PERIPH_GI_RANGE                      23:0
#define APS_FRSC_PGO_MISC_GI_10_FN_PERIPH_GI_WOFFSET                    0x0
#define APS_FRSC_PGO_MISC_GI_10_FN_PERIPH_GI_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_10_FN_PERIPH_GI_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_10_FN_PERIPH_GI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_10_FN_PERIPH_GI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_11
#define APS_FRSC_PGO_MISC_GI_11                 _MK_ADDR_CONST(0xbc)
#define APS_FRSC_PGO_MISC_GI_11_SECURE                  0x0
#define APS_FRSC_PGO_MISC_GI_11_SCR                     0
#define APS_FRSC_PGO_MISC_GI_11_WORD_COUNT                      0x1
#define APS_FRSC_PGO_MISC_GI_11_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_11_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_11_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_11_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_11_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_11_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_11_FN_PERIPH_GI_SHIFT                      _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_11_FN_PERIPH_GI_FIELD                      _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_11_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_11_FN_PERIPH_GI_RANGE                      23:0
#define APS_FRSC_PGO_MISC_GI_11_FN_PERIPH_GI_WOFFSET                    0x0
#define APS_FRSC_PGO_MISC_GI_11_FN_PERIPH_GI_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_11_FN_PERIPH_GI_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_11_FN_PERIPH_GI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_11_FN_PERIPH_GI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_12
#define APS_FRSC_PGO_MISC_GI_12                 _MK_ADDR_CONST(0xc0)
#define APS_FRSC_PGO_MISC_GI_12_SECURE                  0x0
#define APS_FRSC_PGO_MISC_GI_12_SCR                     0
#define APS_FRSC_PGO_MISC_GI_12_WORD_COUNT                      0x1
#define APS_FRSC_PGO_MISC_GI_12_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_12_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_12_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_12_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_12_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_12_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_12_FN_PERIPH_GI_SHIFT                      _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_12_FN_PERIPH_GI_FIELD                      _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_12_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_12_FN_PERIPH_GI_RANGE                      23:0
#define APS_FRSC_PGO_MISC_GI_12_FN_PERIPH_GI_WOFFSET                    0x0
#define APS_FRSC_PGO_MISC_GI_12_FN_PERIPH_GI_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_12_FN_PERIPH_GI_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_12_FN_PERIPH_GI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_12_FN_PERIPH_GI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register APS_FRSC_PGO_MISC_GI_13
#define APS_FRSC_PGO_MISC_GI_13                 _MK_ADDR_CONST(0xc4)
#define APS_FRSC_PGO_MISC_GI_13_SECURE                  0x0
#define APS_FRSC_PGO_MISC_GI_13_SCR                     0
#define APS_FRSC_PGO_MISC_GI_13_WORD_COUNT                      0x1
#define APS_FRSC_PGO_MISC_GI_13_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_13_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_13_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_13_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_13_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_13_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_13_FN_PERIPH_GI_SHIFT                      _MK_SHIFT_CONST(0)
#define APS_FRSC_PGO_MISC_GI_13_FN_PERIPH_GI_FIELD                      _MK_FIELD_CONST(0xffffff, APS_FRSC_PGO_MISC_GI_13_FN_PERIPH_GI_SHIFT)
#define APS_FRSC_PGO_MISC_GI_13_FN_PERIPH_GI_RANGE                      23:0
#define APS_FRSC_PGO_MISC_GI_13_FN_PERIPH_GI_WOFFSET                    0x0
#define APS_FRSC_PGO_MISC_GI_13_FN_PERIPH_GI_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_13_FN_PERIPH_GI_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define APS_FRSC_PGO_MISC_GI_13_FN_PERIPH_GI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_PGO_MISC_GI_13_FN_PERIPH_GI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_CTXT_0
#define APS_FRSC_GI_CTXT_0                      _MK_ADDR_CONST(0xc8)
#define APS_FRSC_GI_CTXT_0_SECURE                       0x0
#define APS_FRSC_GI_CTXT_0_SCR                  0
#define APS_FRSC_GI_CTXT_0_WORD_COUNT                   0x1
#define APS_FRSC_GI_CTXT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_0_FN_GI_CTXT_SHIFT                     _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_CTXT_0_FN_GI_CTXT_FIELD                     _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_CTXT_0_FN_GI_CTXT_SHIFT)
#define APS_FRSC_GI_CTXT_0_FN_GI_CTXT_RANGE                     23:0
#define APS_FRSC_GI_CTXT_0_FN_GI_CTXT_WOFFSET                   0x0
#define APS_FRSC_GI_CTXT_0_FN_GI_CTXT_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_0_FN_GI_CTXT_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_0_FN_GI_CTXT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_0_FN_GI_CTXT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_CTXT
#define APS_FRSC_GI_CTXT                        _MK_ADDR_CONST(0xc8)
#define APS_FRSC_GI_CTXT_SECURE                         0x0
#define APS_FRSC_GI_CTXT_SCR                    0
#define APS_FRSC_GI_CTXT_WORD_COUNT                     0x1
#define APS_FRSC_GI_CTXT_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FN_GI_CTXT_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_CTXT_FN_GI_CTXT_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_CTXT_FN_GI_CTXT_SHIFT)
#define APS_FRSC_GI_CTXT_FN_GI_CTXT_RANGE                       23:0
#define APS_FRSC_GI_CTXT_FN_GI_CTXT_WOFFSET                     0x0
#define APS_FRSC_GI_CTXT_FN_GI_CTXT_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FN_GI_CTXT_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_FN_GI_CTXT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_FN_GI_CTXT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_CTXT_1
#define APS_FRSC_GI_CTXT_1                      _MK_ADDR_CONST(0xcc)
#define APS_FRSC_GI_CTXT_1_SECURE                       0x0
#define APS_FRSC_GI_CTXT_1_SCR                  0
#define APS_FRSC_GI_CTXT_1_WORD_COUNT                   0x1
#define APS_FRSC_GI_CTXT_1_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_1_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_1_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_1_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_1_FN_GI_CTXT_SHIFT                     _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_CTXT_1_FN_GI_CTXT_FIELD                     _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_CTXT_1_FN_GI_CTXT_SHIFT)
#define APS_FRSC_GI_CTXT_1_FN_GI_CTXT_RANGE                     23:0
#define APS_FRSC_GI_CTXT_1_FN_GI_CTXT_WOFFSET                   0x0
#define APS_FRSC_GI_CTXT_1_FN_GI_CTXT_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_1_FN_GI_CTXT_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_CTXT_1_FN_GI_CTXT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_CTXT_1_FN_GI_CTXT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_STAT_0
#define APS_FRSC_GI_STAT_0                      _MK_ADDR_CONST(0xd0)
#define APS_FRSC_GI_STAT_0_SECURE                       0x0
#define APS_FRSC_GI_STAT_0_SCR                  0
#define APS_FRSC_GI_STAT_0_WORD_COUNT                   0x1
#define APS_FRSC_GI_STAT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_0_FN_GI_STAT_SHIFT                     _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_STAT_0_FN_GI_STAT_FIELD                     _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_STAT_0_FN_GI_STAT_SHIFT)
#define APS_FRSC_GI_STAT_0_FN_GI_STAT_RANGE                     23:0
#define APS_FRSC_GI_STAT_0_FN_GI_STAT_WOFFSET                   0x0
#define APS_FRSC_GI_STAT_0_FN_GI_STAT_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_0_FN_GI_STAT_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_0_FN_GI_STAT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_0_FN_GI_STAT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_STAT
#define APS_FRSC_GI_STAT                        _MK_ADDR_CONST(0xd0)
#define APS_FRSC_GI_STAT_SECURE                         0x0
#define APS_FRSC_GI_STAT_SCR                    0
#define APS_FRSC_GI_STAT_WORD_COUNT                     0x1
#define APS_FRSC_GI_STAT_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_FN_GI_STAT_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_STAT_FN_GI_STAT_FIELD                       _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_STAT_FN_GI_STAT_SHIFT)
#define APS_FRSC_GI_STAT_FN_GI_STAT_RANGE                       23:0
#define APS_FRSC_GI_STAT_FN_GI_STAT_WOFFSET                     0x0
#define APS_FRSC_GI_STAT_FN_GI_STAT_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_FN_GI_STAT_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_FN_GI_STAT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_FN_GI_STAT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_STAT_1
#define APS_FRSC_GI_STAT_1                      _MK_ADDR_CONST(0xd4)
#define APS_FRSC_GI_STAT_1_SECURE                       0x0
#define APS_FRSC_GI_STAT_1_SCR                  0
#define APS_FRSC_GI_STAT_1_WORD_COUNT                   0x1
#define APS_FRSC_GI_STAT_1_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_1_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_1_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_1_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_1_FN_GI_STAT_SHIFT                     _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_STAT_1_FN_GI_STAT_FIELD                     _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_STAT_1_FN_GI_STAT_SHIFT)
#define APS_FRSC_GI_STAT_1_FN_GI_STAT_RANGE                     23:0
#define APS_FRSC_GI_STAT_1_FN_GI_STAT_WOFFSET                   0x0
#define APS_FRSC_GI_STAT_1_FN_GI_STAT_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_1_FN_GI_STAT_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_1_FN_GI_STAT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_1_FN_GI_STAT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_STAT_2
#define APS_FRSC_GI_STAT_2                      _MK_ADDR_CONST(0xd8)
#define APS_FRSC_GI_STAT_2_SECURE                       0x0
#define APS_FRSC_GI_STAT_2_SCR                  0
#define APS_FRSC_GI_STAT_2_WORD_COUNT                   0x1
#define APS_FRSC_GI_STAT_2_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_2_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_2_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_2_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_2_FN_GI_STAT_SHIFT                     _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_STAT_2_FN_GI_STAT_FIELD                     _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_STAT_2_FN_GI_STAT_SHIFT)
#define APS_FRSC_GI_STAT_2_FN_GI_STAT_RANGE                     23:0
#define APS_FRSC_GI_STAT_2_FN_GI_STAT_WOFFSET                   0x0
#define APS_FRSC_GI_STAT_2_FN_GI_STAT_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_2_FN_GI_STAT_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_2_FN_GI_STAT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_2_FN_GI_STAT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APS_FRSC_GI_STAT_3
#define APS_FRSC_GI_STAT_3                      _MK_ADDR_CONST(0xdc)
#define APS_FRSC_GI_STAT_3_SECURE                       0x0
#define APS_FRSC_GI_STAT_3_SCR                  0
#define APS_FRSC_GI_STAT_3_WORD_COUNT                   0x1
#define APS_FRSC_GI_STAT_3_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_3_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_3_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_3_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_3_FN_GI_STAT_SHIFT                     _MK_SHIFT_CONST(0)
#define APS_FRSC_GI_STAT_3_FN_GI_STAT_FIELD                     _MK_FIELD_CONST(0xffffff, APS_FRSC_GI_STAT_3_FN_GI_STAT_SHIFT)
#define APS_FRSC_GI_STAT_3_FN_GI_STAT_RANGE                     23:0
#define APS_FRSC_GI_STAT_3_FN_GI_STAT_WOFFSET                   0x0
#define APS_FRSC_GI_STAT_3_FN_GI_STAT_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_3_FN_GI_STAT_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
#define APS_FRSC_GI_STAT_3_FN_GI_STAT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_GI_STAT_3_FN_GI_STAT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APS_FRSC_INTERRUPT_0
#define APS_FRSC_INTERRUPT_0                    _MK_ADDR_CONST(0xe0)
#define APS_FRSC_INTERRUPT_0_SECURE                     0x0
#define APS_FRSC_INTERRUPT_0_SCR                        0
#define APS_FRSC_INTERRUPT_0_WORD_COUNT                         0x1
#define APS_FRSC_INTERRUPT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_INTERRUPT_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define APS_FRSC_INTERRUPT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APS_FRSC_INTERRUPT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APS_FRSC_INTERRUPT_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define APS_FRSC_INTERRUPT_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define APS_FRSC_INTERRUPT_0_SYSINTR_SHIFT                      _MK_SHIFT_CONST(1)
#define APS_FRSC_INTERRUPT_0_SYSINTR_FIELD                      _MK_FIELD_CONST(0x1, APS_FRSC_INTERRUPT_0_SYSINTR_SHIFT)
#define APS_FRSC_INTERRUPT_0_SYSINTR_RANGE                      1:1
#define APS_FRSC_INTERRUPT_0_SYSINTR_WOFFSET                    0x0
#define APS_FRSC_INTERRUPT_0_SYSINTR_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_INTERRUPT_0_SYSINTR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APS_FRSC_INTERRUPT_0_SYSINTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_INTERRUPT_0_SYSINTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APS_FRSC_INTERRUPT_0_SYSINTL_SHIFT                      _MK_SHIFT_CONST(0)
#define APS_FRSC_INTERRUPT_0_SYSINTL_FIELD                      _MK_FIELD_CONST(0x1, APS_FRSC_INTERRUPT_0_SYSINTL_SHIFT)
#define APS_FRSC_INTERRUPT_0_SYSINTL_RANGE                      0:0
#define APS_FRSC_INTERRUPT_0_SYSINTL_WOFFSET                    0x0
#define APS_FRSC_INTERRUPT_0_SYSINTL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_INTERRUPT_0_SYSINTL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APS_FRSC_INTERRUPT_0_SYSINTL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_INTERRUPT_0_SYSINTL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register APS_FRSC_AXIM_ERR_STS_0
#define APS_FRSC_AXIM_ERR_STS_0                 _MK_ADDR_CONST(0xe4)
#define APS_FRSC_AXIM_ERR_STS_0_SECURE                  0x0
#define APS_FRSC_AXIM_ERR_STS_0_SCR                     0
#define APS_FRSC_AXIM_ERR_STS_0_WORD_COUNT                      0x1
#define APS_FRSC_AXIM_ERR_STS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIM_ERR_STS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_READ_MASK                       _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIM_ERR_STS_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIM_ERR_STS_0_AXIMCORR0_SHIFT                 _MK_SHIFT_CONST(5)
#define APS_FRSC_AXIM_ERR_STS_0_AXIMCORR0_FIELD                 _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_STS_0_AXIMCORR0_SHIFT)
#define APS_FRSC_AXIM_ERR_STS_0_AXIMCORR0_RANGE                 5:5
#define APS_FRSC_AXIM_ERR_STS_0_AXIMCORR0_WOFFSET                       0x0
#define APS_FRSC_AXIM_ERR_STS_0_AXIMCORR0_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIMCORR0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_STS_0_AXIMCORR0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIMCORR0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_R_SHIFT                  _MK_SHIFT_CONST(4)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_R_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_R_SHIFT)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_R_RANGE                  4:4
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_R_WOFFSET                        0x0
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_R_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AR_SHIFT                 _MK_SHIFT_CONST(3)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AR_FIELD                 _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AR_SHIFT)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AR_RANGE                 3:3
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AR_WOFFSET                       0x0
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AR_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_B_SHIFT                  _MK_SHIFT_CONST(2)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_B_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_B_SHIFT)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_B_RANGE                  2:2
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_B_WOFFSET                        0x0
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_B_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_B_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_B_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_B_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_W_SHIFT                  _MK_SHIFT_CONST(1)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_W_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_W_SHIFT)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_W_RANGE                  1:1
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_W_WOFFSET                        0x0
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_W_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AW_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AW_FIELD                 _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AW_SHIFT)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AW_RANGE                 0:0
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AW_WOFFSET                       0x0
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_STS_0_AXIM_FATAL_ERR_AW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_AXIM_ERR_EN_0
#define APS_FRSC_AXIM_ERR_EN_0                  _MK_ADDR_CONST(0xe8)
#define APS_FRSC_AXIM_ERR_EN_0_SECURE                   0x0
#define APS_FRSC_AXIM_ERR_EN_0_SCR                      0
#define APS_FRSC_AXIM_ERR_EN_0_WORD_COUNT                       0x1
#define APS_FRSC_AXIM_ERR_EN_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_RESET_MASK                       _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIM_ERR_EN_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_READ_MASK                        _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIM_ERR_EN_0_WRITE_MASK                       _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIM_ERR_EN_0_AXIMCORR0_EN_SHIFT                       _MK_SHIFT_CONST(5)
#define APS_FRSC_AXIM_ERR_EN_0_AXIMCORR0_EN_FIELD                       _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_EN_0_AXIMCORR0_EN_SHIFT)
#define APS_FRSC_AXIM_ERR_EN_0_AXIMCORR0_EN_RANGE                       5:5
#define APS_FRSC_AXIM_ERR_EN_0_AXIMCORR0_EN_WOFFSET                     0x0
#define APS_FRSC_AXIM_ERR_EN_0_AXIMCORR0_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIMCORR0_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_EN_0_AXIMCORR0_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIMCORR0_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_R_EN_SHIFT                        _MK_SHIFT_CONST(4)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_R_EN_FIELD                        _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_R_EN_SHIFT)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_R_EN_RANGE                        4:4
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_R_EN_WOFFSET                      0x0
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_R_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_R_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_R_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_R_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AR_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AR_EN_FIELD                       _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AR_EN_SHIFT)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AR_EN_RANGE                       3:3
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AR_EN_WOFFSET                     0x0
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AR_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AR_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AR_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AR_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_B_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_B_EN_FIELD                        _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_B_EN_SHIFT)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_B_EN_RANGE                        2:2
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_B_EN_WOFFSET                      0x0
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_B_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_B_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_B_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_B_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_W_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_W_EN_FIELD                        _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_W_EN_SHIFT)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_W_EN_RANGE                        1:1
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_W_EN_WOFFSET                      0x0
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_W_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_W_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_W_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_W_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AW_EN_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AW_EN_FIELD                       _MK_FIELD_CONST(0x1, APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AW_EN_SHIFT)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AW_EN_RANGE                       0:0
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AW_EN_WOFFSET                     0x0
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_EN_0_AXIM_FATAL_ERR_AW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_AXIM_ERR_ADDR_0
#define APS_FRSC_AXIM_ERR_ADDR_0                        _MK_ADDR_CONST(0xec)
#define APS_FRSC_AXIM_ERR_ADDR_0_SECURE                         0x0
#define APS_FRSC_AXIM_ERR_ADDR_0_SCR                    0
#define APS_FRSC_AXIM_ERR_ADDR_0_WORD_COUNT                     0x1
#define APS_FRSC_AXIM_ERR_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0xfffffff8)
#define APS_FRSC_AXIM_ERR_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_ADDR_0_READ_MASK                      _MK_MASK_CONST(0xfffffff8)
#define APS_FRSC_AXIM_ERR_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_ADDR_0_MERRADDR0_SHIFT                        _MK_SHIFT_CONST(3)
#define APS_FRSC_AXIM_ERR_ADDR_0_MERRADDR0_FIELD                        _MK_FIELD_CONST(0x1fffffff, APS_FRSC_AXIM_ERR_ADDR_0_MERRADDR0_SHIFT)
#define APS_FRSC_AXIM_ERR_ADDR_0_MERRADDR0_RANGE                        31:3
#define APS_FRSC_AXIM_ERR_ADDR_0_MERRADDR0_WOFFSET                      0x0
#define APS_FRSC_AXIM_ERR_ADDR_0_MERRADDR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_ADDR_0_MERRADDR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1fffffff)
#define APS_FRSC_AXIM_ERR_ADDR_0_MERRADDR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIM_ERR_ADDR_0_MERRADDR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register APS_FRSC_PPX_ERR_STS_0
#define APS_FRSC_PPX_ERR_STS_0                  _MK_ADDR_CONST(0xf0)
#define APS_FRSC_PPX_ERR_STS_0_SECURE                   0x0
#define APS_FRSC_PPX_ERR_STS_0_SCR                      0
#define APS_FRSC_PPX_ERR_STS_0_WORD_COUNT                       0x1
#define APS_FRSC_PPX_ERR_STS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_RESET_MASK                       _MK_MASK_CONST(0x3f)
#define APS_FRSC_PPX_ERR_STS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_READ_MASK                        _MK_MASK_CONST(0x3f)
#define APS_FRSC_PPX_ERR_STS_0_WRITE_MASK                       _MK_MASK_CONST(0x3f)
#define APS_FRSC_PPX_ERR_STS_0_PPXCORR0_SHIFT                   _MK_SHIFT_CONST(5)
#define APS_FRSC_PPX_ERR_STS_0_PPXCORR0_FIELD                   _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_STS_0_PPXCORR0_SHIFT)
#define APS_FRSC_PPX_ERR_STS_0_PPXCORR0_RANGE                   5:5
#define APS_FRSC_PPX_ERR_STS_0_PPXCORR0_WOFFSET                 0x0
#define APS_FRSC_PPX_ERR_STS_0_PPXCORR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPXCORR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_STS_0_PPXCORR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPXCORR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_R_SHIFT                    _MK_SHIFT_CONST(4)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_R_FIELD                    _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_R_SHIFT)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_R_RANGE                    4:4
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_R_WOFFSET                  0x0
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_R_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AR_SHIFT                   _MK_SHIFT_CONST(3)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AR_FIELD                   _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AR_SHIFT)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AR_RANGE                   3:3
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AR_WOFFSET                 0x0
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AR_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_B_SHIFT                    _MK_SHIFT_CONST(2)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_B_FIELD                    _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_B_SHIFT)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_B_RANGE                    2:2
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_B_WOFFSET                  0x0
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_B_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_B_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_B_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_B_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_W_SHIFT                    _MK_SHIFT_CONST(1)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_W_FIELD                    _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_W_SHIFT)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_W_RANGE                    1:1
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_W_WOFFSET                  0x0
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_W_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AW_SHIFT                   _MK_SHIFT_CONST(0)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AW_FIELD                   _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AW_SHIFT)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AW_RANGE                   0:0
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AW_WOFFSET                 0x0
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_STS_0_PPX_FATAL_ERR_AW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register APS_FRSC_PPX_ERR_EN_0
#define APS_FRSC_PPX_ERR_EN_0                   _MK_ADDR_CONST(0xf4)
#define APS_FRSC_PPX_ERR_EN_0_SECURE                    0x0
#define APS_FRSC_PPX_ERR_EN_0_SCR                       0
#define APS_FRSC_PPX_ERR_EN_0_WORD_COUNT                        0x1
#define APS_FRSC_PPX_ERR_EN_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_RESET_MASK                        _MK_MASK_CONST(0x3f)
#define APS_FRSC_PPX_ERR_EN_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_READ_MASK                         _MK_MASK_CONST(0x3f)
#define APS_FRSC_PPX_ERR_EN_0_WRITE_MASK                        _MK_MASK_CONST(0x3f)
#define APS_FRSC_PPX_ERR_EN_0_PPXCORR0_EN_SHIFT                 _MK_SHIFT_CONST(5)
#define APS_FRSC_PPX_ERR_EN_0_PPXCORR0_EN_FIELD                 _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_EN_0_PPXCORR0_EN_SHIFT)
#define APS_FRSC_PPX_ERR_EN_0_PPXCORR0_EN_RANGE                 5:5
#define APS_FRSC_PPX_ERR_EN_0_PPXCORR0_EN_WOFFSET                       0x0
#define APS_FRSC_PPX_ERR_EN_0_PPXCORR0_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPXCORR0_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_EN_0_PPXCORR0_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPXCORR0_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_R_EN_SHIFT                  _MK_SHIFT_CONST(4)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_R_EN_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_R_EN_SHIFT)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_R_EN_RANGE                  4:4
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_R_EN_WOFFSET                        0x0
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_R_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_R_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_R_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_R_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AR_EN_SHIFT                 _MK_SHIFT_CONST(3)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AR_EN_FIELD                 _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AR_EN_SHIFT)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AR_EN_RANGE                 3:3
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AR_EN_WOFFSET                       0x0
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AR_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_B_EN_SHIFT                  _MK_SHIFT_CONST(2)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_B_EN_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_B_EN_SHIFT)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_B_EN_RANGE                  2:2
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_B_EN_WOFFSET                        0x0
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_B_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_B_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_B_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_B_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_W_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_W_EN_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_W_EN_SHIFT)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_W_EN_RANGE                  1:1
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_W_EN_WOFFSET                        0x0
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_W_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_W_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_W_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_W_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AW_EN_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AW_EN_FIELD                 _MK_FIELD_CONST(0x1, APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AW_EN_SHIFT)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AW_EN_RANGE                 0:0
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AW_EN_WOFFSET                       0x0
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AW_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AW_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AW_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_PPX_ERR_EN_0_PPX_FATAL_ERR_AW_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_AXIS_ERR_STS_0
#define APS_FRSC_AXIS_ERR_STS_0                 _MK_ADDR_CONST(0xf8)
#define APS_FRSC_AXIS_ERR_STS_0_SECURE                  0x0
#define APS_FRSC_AXIS_ERR_STS_0_SCR                     0
#define APS_FRSC_AXIS_ERR_STS_0_WORD_COUNT                      0x1
#define APS_FRSC_AXIS_ERR_STS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIS_ERR_STS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_READ_MASK                       _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIS_ERR_STS_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIS_ERR_STS_0_AXISCORR0_SHIFT                 _MK_SHIFT_CONST(5)
#define APS_FRSC_AXIS_ERR_STS_0_AXISCORR0_FIELD                 _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_STS_0_AXISCORR0_SHIFT)
#define APS_FRSC_AXIS_ERR_STS_0_AXISCORR0_RANGE                 5:5
#define APS_FRSC_AXIS_ERR_STS_0_AXISCORR0_WOFFSET                       0x0
#define APS_FRSC_AXIS_ERR_STS_0_AXISCORR0_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXISCORR0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_STS_0_AXISCORR0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXISCORR0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_R_SHIFT                  _MK_SHIFT_CONST(4)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_R_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_R_SHIFT)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_R_RANGE                  4:4
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_R_WOFFSET                        0x0
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_R_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AR_SHIFT                 _MK_SHIFT_CONST(3)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AR_FIELD                 _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AR_SHIFT)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AR_RANGE                 3:3
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AR_WOFFSET                       0x0
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AR_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_B_SHIFT                  _MK_SHIFT_CONST(2)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_B_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_B_SHIFT)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_B_RANGE                  2:2
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_B_WOFFSET                        0x0
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_B_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_B_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_B_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_B_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_W_SHIFT                  _MK_SHIFT_CONST(1)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_W_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_W_SHIFT)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_W_RANGE                  1:1
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_W_WOFFSET                        0x0
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_W_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AW_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AW_FIELD                 _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AW_SHIFT)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AW_RANGE                 0:0
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AW_WOFFSET                       0x0
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_STS_0_AXIS_FATAL_ERR_AW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_AXIS_ERR_EN_0
#define APS_FRSC_AXIS_ERR_EN_0                  _MK_ADDR_CONST(0xfc)
#define APS_FRSC_AXIS_ERR_EN_0_SECURE                   0x0
#define APS_FRSC_AXIS_ERR_EN_0_SCR                      0
#define APS_FRSC_AXIS_ERR_EN_0_WORD_COUNT                       0x1
#define APS_FRSC_AXIS_ERR_EN_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_RESET_MASK                       _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIS_ERR_EN_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_READ_MASK                        _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIS_ERR_EN_0_WRITE_MASK                       _MK_MASK_CONST(0x3f)
#define APS_FRSC_AXIS_ERR_EN_0_AXISCORR0_EN_SHIFT                       _MK_SHIFT_CONST(5)
#define APS_FRSC_AXIS_ERR_EN_0_AXISCORR0_EN_FIELD                       _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_EN_0_AXISCORR0_EN_SHIFT)
#define APS_FRSC_AXIS_ERR_EN_0_AXISCORR0_EN_RANGE                       5:5
#define APS_FRSC_AXIS_ERR_EN_0_AXISCORR0_EN_WOFFSET                     0x0
#define APS_FRSC_AXIS_ERR_EN_0_AXISCORR0_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXISCORR0_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_EN_0_AXISCORR0_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXISCORR0_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_R_EN_SHIFT                        _MK_SHIFT_CONST(4)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_R_EN_FIELD                        _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_R_EN_SHIFT)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_R_EN_RANGE                        4:4
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_R_EN_WOFFSET                      0x0
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_R_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_R_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_R_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_R_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AR_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AR_EN_FIELD                       _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AR_EN_SHIFT)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AR_EN_RANGE                       3:3
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AR_EN_WOFFSET                     0x0
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AR_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AR_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AR_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AR_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_B_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_B_EN_FIELD                        _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_B_EN_SHIFT)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_B_EN_RANGE                        2:2
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_B_EN_WOFFSET                      0x0
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_B_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_B_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_B_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_B_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_W_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_W_EN_FIELD                        _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_W_EN_SHIFT)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_W_EN_RANGE                        1:1
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_W_EN_WOFFSET                      0x0
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_W_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_W_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_W_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_W_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AW_EN_SHIFT                       _MK_SHIFT_CONST(0)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AW_EN_FIELD                       _MK_FIELD_CONST(0x1, APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AW_EN_SHIFT)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AW_EN_RANGE                       0:0
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AW_EN_WOFFSET                     0x0
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_EN_0_AXIS_FATAL_ERR_AW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APS_FRSC_AXIS_ERR_ADDR_0
#define APS_FRSC_AXIS_ERR_ADDR_0                        _MK_ADDR_CONST(0x100)
#define APS_FRSC_AXIS_ERR_ADDR_0_SECURE                         0x0
#define APS_FRSC_AXIS_ERR_ADDR_0_SCR                    0
#define APS_FRSC_AXIS_ERR_ADDR_0_WORD_COUNT                     0x1
#define APS_FRSC_AXIS_ERR_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0x7ffff8)
#define APS_FRSC_AXIS_ERR_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_ADDR_0_READ_MASK                      _MK_MASK_CONST(0x7ffff8)
#define APS_FRSC_AXIS_ERR_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_ADDR_0_SERRADDR0_SHIFT                        _MK_SHIFT_CONST(3)
#define APS_FRSC_AXIS_ERR_ADDR_0_SERRADDR0_FIELD                        _MK_FIELD_CONST(0xfffff, APS_FRSC_AXIS_ERR_ADDR_0_SERRADDR0_SHIFT)
#define APS_FRSC_AXIS_ERR_ADDR_0_SERRADDR0_RANGE                        22:3
#define APS_FRSC_AXIS_ERR_ADDR_0_SERRADDR0_WOFFSET                      0x0
#define APS_FRSC_AXIS_ERR_ADDR_0_SERRADDR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_ADDR_0_SERRADDR0_DEFAULT_MASK                 _MK_MASK_CONST(0xfffff)
#define APS_FRSC_AXIS_ERR_ADDR_0_SERRADDR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_AXIS_ERR_ADDR_0_SERRADDR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register APS_FRSC_BTCM_ERR_CTL_0
#define APS_FRSC_BTCM_ERR_CTL_0                 _MK_ADDR_CONST(0x104)
#define APS_FRSC_BTCM_ERR_CTL_0_SECURE                  0x0
#define APS_FRSC_BTCM_ERR_CTL_0_SCR                     0
#define APS_FRSC_BTCM_ERR_CTL_0_WORD_COUNT                      0x1
#define APS_FRSC_BTCM_ERR_CTL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_RESET_MASK                      _MK_MASK_CONST(0xffff3f7f)
#define APS_FRSC_BTCM_ERR_CTL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_READ_MASK                       _MK_MASK_CONST(0xffff3f7f)
#define APS_FRSC_BTCM_ERR_CTL_0_WRITE_MASK                      _MK_MASK_CONST(0xffff3f7f)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_SHIFT                     _MK_SHIFT_CONST(16)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_FIELD                     _MK_FIELD_CONST(0xffff, APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_SHIFT)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_RANGE                     31:16
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_WOFFSET                   0x0
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_RELOAD_SHIFT                       _MK_SHIFT_CONST(8)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_RELOAD_FIELD                       _MK_FIELD_CONST(0x3f, APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_RELOAD_SHIFT)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_RELOAD_RANGE                       13:8
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_RELOAD_WOFFSET                     0x0
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_RELOAD_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_RELOAD_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_RELOAD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_RELOAD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_EN_SHIFT                   _MK_SHIFT_CONST(6)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_EN_FIELD                   _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_EN_SHIFT)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_EN_RANGE                   6:6
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_EN_WOFFSET                 0x0
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_BIT_CNT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_SEL_SHIFT                  _MK_SHIFT_CONST(5)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_SEL_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_SEL_SHIFT)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_SEL_RANGE                  5:5
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_SEL_WOFFSET                        0x0
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_EN_FIELD                   _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_EN_SHIFT)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_EN_RANGE                   4:4
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_EN_WOFFSET                 0x0
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_CPU_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TYPE_EN_SHIFT                  _MK_SHIFT_CONST(3)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TYPE_EN_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TYPE_EN_SHIFT)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TYPE_EN_RANGE                  3:3
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TYPE_EN_WOFFSET                        0x0
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TYPE_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TYPE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TYPE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TYPE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_FORCE_ERR_SHIFT                    _MK_SHIFT_CONST(2)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_FORCE_ERR_FIELD                    _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_CTL_0_BTCM_FORCE_ERR_SHIFT)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_FORCE_ERR_RANGE                    2:2
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_FORCE_ERR_WOFFSET                  0x0
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_FORCE_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_FORCE_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_FORCE_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_FORCE_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_EN_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_EN_SHIFT)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_EN_RANGE                  1:1
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_EN_WOFFSET                        0x0
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_RELOAD_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_EN_SHIFT                 _MK_SHIFT_CONST(0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_EN_FIELD                 _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_EN_SHIFT)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_EN_RANGE                 0:0
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_EN_WOFFSET                       0x0
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_CTL_0_BTCM_ERR_TIMER_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APS_FRSC_BTCM_ERR_LOG_0
#define APS_FRSC_BTCM_ERR_LOG_0                 _MK_ADDR_CONST(0x108)
#define APS_FRSC_BTCM_ERR_LOG_0_SECURE                  0x0
#define APS_FRSC_BTCM_ERR_LOG_0_SCR                     0
#define APS_FRSC_BTCM_ERR_LOG_0_WORD_COUNT                      0x1
#define APS_FRSC_BTCM_ERR_LOG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_RESET_MASK                      _MK_MASK_CONST(0xfffff03f)
#define APS_FRSC_BTCM_ERR_LOG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_READ_MASK                       _MK_MASK_CONST(0xfffff03f)
#define APS_FRSC_BTCM_ERR_LOG_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff03f)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_ADDR_SHIFT                     _MK_SHIFT_CONST(12)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_ADDR_FIELD                     _MK_FIELD_CONST(0xfffff, APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_ADDR_SHIFT)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_ADDR_RANGE                     31:12
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_ADDR_WOFFSET                   0x0
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xfffff)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_WORD_SHIFT                     _MK_SHIFT_CONST(5)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_WORD_FIELD                     _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_WORD_SHIFT)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_WORD_RANGE                     5:5
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_WORD_WOFFSET                   0x0
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_WORD_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_WORD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_WORD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_WORD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CHANNEL_SHIFT                  _MK_SHIFT_CONST(4)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CHANNEL_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CHANNEL_SHIFT)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CHANNEL_RANGE                  4:4
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CHANNEL_WOFFSET                        0x0
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_TYPE_SHIFT                     _MK_SHIFT_CONST(3)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_TYPE_FIELD                     _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_TYPE_SHIFT)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_TYPE_RANGE                     3:3
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_TYPE_WOFFSET                   0x0
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_TYPE_DEFAULT                   _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_TYPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_TYPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_TYPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_SHIFT                      _MK_SHIFT_CONST(2)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_FIELD                      _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_SHIFT)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_RANGE                      2:2
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_WOFFSET                    0x0
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_DEFAULT                    _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_VAL_SHIFT                  _MK_SHIFT_CONST(1)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_VAL_FIELD                  _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_VAL_SHIFT)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_VAL_RANGE                  1:1
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_VAL_WOFFSET                        0x0
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_CPU_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_VALID_SHIFT                    _MK_SHIFT_CONST(0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_VALID_FIELD                    _MK_FIELD_CONST(0x1, APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_VALID_SHIFT)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_VALID_RANGE                    0:0
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_VALID_WOFFSET                  0x0
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_VALID_DEFAULT                  _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_ERR_LOG_0_BTCM_ERR_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register APS_FRSC_BTCM_BIT_ERR_LOC_0
#define APS_FRSC_BTCM_BIT_ERR_LOC_0                     _MK_ADDR_CONST(0x10c)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_SECURE                      0x0
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_SCR                         0
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_WORD_COUNT                  0x1
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_BTCM_ERR_BIT_SHIFT                  _MK_SHIFT_CONST(0)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_BTCM_ERR_BIT_FIELD                  _MK_FIELD_CONST(0x3f, APS_FRSC_BTCM_BIT_ERR_LOC_0_BTCM_ERR_BIT_SHIFT)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_BTCM_ERR_BIT_RANGE                  5:0
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_BTCM_ERR_BIT_WOFFSET                        0x0
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_BTCM_ERR_BIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_BTCM_ERR_BIT_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_BTCM_ERR_BIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APS_FRSC_BTCM_BIT_ERR_LOC_0_BTCM_ERR_BIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


//
// REGISTER LIST
//
#define LIST_ARAPS_FRSC_REGS(_op_) \
_op_(APS_FRSC_SC_CTL_0) \
_op_(APS_FRSC_SC_STS_0) \
_op_(APS_FRSC_PGO_0_DATA_0) \
_op_(APS_FRSC_PGO_1_DATA_0) \
_op_(APS_FRSC_GI_INDIRECT_ACCESS_0) \
_op_(APS_FRSC_SC_MODEIN_0) \
_op_(APS_FRSC_PGO_ALARM_INJ_0) \
_op_(APS_FRSC_PGO_ALARM_INJ) \
_op_(APS_FRSC_PGO_ALARM_INJ_1) \
_op_(APS_FRSC_GI_ALARMS_0) \
_op_(APS_FRSC_GI_ALARMS) \
_op_(APS_FRSC_GI_ALARMS_1) \
_op_(APS_FRSC_GI_CTXT_FA_0) \
_op_(APS_FRSC_GI_CTXT_FA) \
_op_(APS_FRSC_GI_CTXT_FA_1) \
_op_(APS_FRSC_PGO_EVENT_MASK_0) \
_op_(APS_FRSC_PGO_EVENT_MASK) \
_op_(APS_FRSC_PGO_EVENT_MASK_1) \
_op_(APS_FRSC_PGO_ALARMS_ROUTING_0A_0) \
_op_(APS_FRSC_PGO_ALARMS_ROUTING_0B_0) \
_op_(APS_FRSC_PGO_ALARMS_ROUTING_1A_0) \
_op_(APS_FRSC_PGO_ALARMS_ROUTING_1B_0) \
_op_(APS_FRSC_PGO_LOGS_RST_0) \
_op_(APS_FRSC_PGO_DUMMYADR_0) \
_op_(APS_FRSC_PGO_MISC_0) \
_op_(APS_FRSC_PGO_MISC_PGO_1_0) \
_op_(APS_FRSC_PGO_MISC_PGO_2_0) \
_op_(APS_FRSC_PGO_MISC_PGO_3_0) \
_op_(APS_FRSC_PGO_MISC_PGO_4_0) \
_op_(APS_FRSC_PGO_MISC_PGO_5_0) \
_op_(APS_FRSC_PGO_MISC_PGO_6_0) \
_op_(APS_FRSC_PGO_MISC_PGO_7_0) \
_op_(APS_FRSC_PGO_MISC_PGO_8_0) \
_op_(APS_FRSC_PGO_MISC_PGO_9_0) \
_op_(APS_FRSC_PGO_MISC_PGO_10_0) \
_op_(APS_FRSC_PGO_MISC_PGO_11_0) \
_op_(APS_FRSC_PGO_MISC_PGO_12_0) \
_op_(APS_FRSC_PGO_MISC_PGO_13_0) \
_op_(APS_FRSC_PGO_MISC_PGO_14_0) \
_op_(APS_FRSC_PGO_MISC_PGO_15_0) \
_op_(APS_FRSC_PGO_MISC_GI_0) \
_op_(APS_FRSC_PGO_MISC_GI) \
_op_(APS_FRSC_PGO_MISC_GI_1) \
_op_(APS_FRSC_PGO_MISC_GI_2) \
_op_(APS_FRSC_PGO_MISC_GI_3) \
_op_(APS_FRSC_PGO_MISC_GI_4) \
_op_(APS_FRSC_PGO_MISC_GI_5) \
_op_(APS_FRSC_PGO_MISC_GI_6) \
_op_(APS_FRSC_PGO_MISC_GI_7) \
_op_(APS_FRSC_PGO_MISC_GI_8) \
_op_(APS_FRSC_PGO_MISC_GI_9) \
_op_(APS_FRSC_PGO_MISC_GI_10) \
_op_(APS_FRSC_PGO_MISC_GI_11) \
_op_(APS_FRSC_PGO_MISC_GI_12) \
_op_(APS_FRSC_PGO_MISC_GI_13) \
_op_(APS_FRSC_GI_CTXT_0) \
_op_(APS_FRSC_GI_CTXT) \
_op_(APS_FRSC_GI_CTXT_1) \
_op_(APS_FRSC_GI_STAT_0) \
_op_(APS_FRSC_GI_STAT) \
_op_(APS_FRSC_GI_STAT_1) \
_op_(APS_FRSC_GI_STAT_2) \
_op_(APS_FRSC_GI_STAT_3) \
_op_(APS_FRSC_INTERRUPT_0) \
_op_(APS_FRSC_AXIM_ERR_STS_0) \
_op_(APS_FRSC_AXIM_ERR_EN_0) \
_op_(APS_FRSC_AXIM_ERR_ADDR_0) \
_op_(APS_FRSC_PPX_ERR_STS_0) \
_op_(APS_FRSC_PPX_ERR_EN_0) \
_op_(APS_FRSC_AXIS_ERR_STS_0) \
_op_(APS_FRSC_AXIS_ERR_EN_0) \
_op_(APS_FRSC_AXIS_ERR_ADDR_0) \
_op_(APS_FRSC_BTCM_ERR_CTL_0) \
_op_(APS_FRSC_BTCM_ERR_LOG_0) \
_op_(APS_FRSC_BTCM_BIT_ERR_LOC_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_APS_FRSC   0x00000000

//
// ARAPS_FRSC REGISTER BANKS
//

#define APS_FRSC0_FIRST_REG 0x0000 // APS_FRSC_SC_CTL_0
#define APS_FRSC0_LAST_REG 0x010c // APS_FRSC_BTCM_BIT_ERR_LOC_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARAPS_FRSC_H_INC_
